Joel Brobecker
61baf725ec
update copyright year range in GDB files
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This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.
gdb/ChangeLog:
Update copyright year range in all GDB files.
2017-01-01 10:52:34 +04:00
Joel Brobecker
618f726fcb
GDB copyright headers update after running GDB's copyright.py script.
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gdb/ChangeLog:
Update year range in copyright notice of all files.
2016-01-01 08:43:22 +04:00
Nick Clifton
63c72d1ae4
Fix typo in check for valid register number in RX sim.
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PR sim/18273
* reg.c (put_reg): Fix check for valid register number.
2015-04-24 15:31:36 +01:00
Joel Brobecker
32d0add0a6
Update year range in copyright notice of all files owned by the GDB project.
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gdb/ChangeLog:
Update year range in copyright notice of all files.
2015-01-01 13:32:14 +04:00
Joel Brobecker
ecd75fc8ee
Update Copyright year range in all files maintained by GDB.
2014-01-01 07:54:24 +04:00
Joel Brobecker
8acc9f485b
Update years in copyright notice for the GDB files.
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Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
2013-01-01 06:41:43 +00:00
Joel Brobecker
c5a5708100
Copyright year update in most files of the GDB Project.
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gdb/ChangeLog:
Copyright year update in most files of the GDB Project.
2012-01-04 08:28:28 +00:00
Joel Brobecker
7b6bb8daac
run copyright.sh for 2011.
2011-01-01 15:34:07 +00:00
DJ Delorie
933786524e
[sim/rx]
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* README.txt: New.
* config.h (CYCLE_ACCURATE, CYCLE_STATS): New.
* configure.in (--enable-cycle-accurate, --enable-cycle-stats):
New. Default to enabled.
* configure: Regenerate.
* cpu.h (regs_type): Add cycle tracking info.
(reset_pipeline_stats): Declare.
(halt_pipeline_stats): Declare.
(pipeline_stats): Declare.
* main.c (done): Call pipeline_stats().
* mem.h (rx_mem_ptr): Moved to here ...
* mem.c (mem_ptr): ... from here. Rename throughout.
(mem_put_byte): Move LEDs to Port A. Add Port B to control cycle
statistics. Move UART to SCI4.
(mem_put_hi): Add TPU 1-2. TPU 1 and 2 count CPU cycles.
* reg.c (init_regs): Set Rt reg to -1 (no reg).
* rx.c: Add cycle counting and statistics throughout.
(rx_get_byte): Optimize for speed.
(decode_opcode): Likewise.
(reset_pipeline_stats): New.
(halt_pipeline_stats): New.
(pipeline_stats): New.
* trace.c (sim_disasm_one): Print cycle count.
[include/opcode]
* rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
2010-07-28 21:58:22 +00:00
Nick Clifton
32b269aeb2
* reg.c (set_oszc): Use unsigned int for the mask.
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(set_szc, set_osz, set_sz): Likewise.
2010-06-08 09:15:17 +00:00
Joel Brobecker
dc3cf14f35
Update copyright notices to add year 2010.
2010-01-01 10:03:36 +00:00
DJ Delorie
4f8d4a3861
[sim]
...
* rx: New directory.
* configure.ac: Add entry for Renesas RX.
* configure: Regenerate.
[include/gdb]
* sim-rx.h: New.
2009-11-24 19:22:45 +00:00
