A branch in a non-exec section that needs a stub can lead to this
assertion.
* powerpc.cc (Powerpc_relobj::stub_table): Return NULL rather
then asserting.
Follow-up to commit 14f6890677.
global_thread_id_to_ptid expects global thread numbers, which are nowadays only
used in MI, never presented to the user in the CLI. Since this is a CLI
command, it should accept the inferior-qualified format instead.
gdb/
* gnu-nat.c (set_sig_thread_cmd): Use parse_thread_id instead of
global_thread_id_to_ptid.
..., so handle these in "C" mode still:
gdb/
* config/i386/i386gnu.mh (%_S.o %_U.o): Add "-x c" to
"COMPILE.post".
* gnu-nat.c: #include Mach/Hurd headers before all others. Wrap
Mach/Hurd headers and MIG stubs' prototypes in 'extern "C"'.
* i386-gnu-nat.c: Likewise.
GNU/Hurd uses its own "typedef enum __error_t_codes error_t;"
([glibc]/sysdeps/mach/hurd/bits/errno.h), contrary to the default
"typedef int error_t;" ([glibc]/stdlib/errno.h).
The Mach/Hurd RPCs return kern_return_t values, for which, upon assigning them
to an error_t variable, GCC in C++ mode tells us "error: invalid conversion
from 'kern_return_t {aka int}' to 'error_t {aka __error_t_codes}'". Instead of
casting all these RPC return values to "error_t", just use "kern_return_t"
variables:
gdb/
* gnu-nat.c (proc_get_exception_port, proc_set_exception_port)
(INF_RESUME_MSGPORT_RPC, proc_get_state, _proc_get_exc_port)
(proc_steal_exc_port, proc_restore_exc_port, make_proc)
(inf_startup, inf_set_pid, inf_validate_procinfo)
(inf_validate_task_sc, inf_set_traced, inf_validate_procs)
(inf_signal, inf_continue, gnu_wait, S_exception_raise_request)
(do_mach_notify_dead_name, S_proc_wait_reply)
(S_msg_sig_post_untraced_reply, S_msg_sig_post_reply)
(port_msgs_queued, gnu_read_inferior, gnu_write_inferior)
(gnu_find_memory_regions, steal_exc_port, thread_takeover_sc_cmd)
(flush_inferior_icache): Instead of "error_t" use "kern_return_t".
* i386-gnu-nat.c (fetch_fpregs, store_fpregs, i386_gnu_dr_get)
(i386_gnu_dr_set): Likewise.
... by a bit of code refactoring:
gdb/
* gnu-nat.c (set_task_pause_cmd, set_signals_cmd)
(set_exceptions_cmd): Add variants taking an "int arg" instead of
a "char *". Make the "char *" variants use the former.
(set_noninvasive_cmd): Also use the "int arg" variants.
C++ doesn't do implicit type conversions from "void *", so we have to...
gdb/
* i386-gnu-nat.c (i386_gnu_dr_set_control_one)
(i386_gnu_dr_set_addr_one): Explicitly cast "void *".
Replace a global `mips_opts.isa' reference in `is_opcode_valid' and use
a local copy just made in `isa'. No functional change.
gas/
* config/tc-mips.c (is_opcode_valid): Use local `isa'
consistently.
Adds a new option, defaulting to off, that allows a group of stubs to
serve multiple output sections. Prior to this patch powerpc gold
allowed this unconditionally, which is a little unsafe with clever
code that discards/reuses sections at runtime.
* options.h (--stub-group-multi): New PowerPC option.
* powerpc.cc (Stub_control): Add multi_os_ var and param
to constructor. Sort start_ var later. Comment State.
(Stub_control::can_add_to_stub_group): Heed multi_os_.
(Target_powerpc::group_sections): Update.
Gold attaches stubs to an existing section in contrast to ld.bfd which
inserts a new section for stubs. If we want stubs before branches,
then the stubs must be added to the previous section. Adding to the
previous section is a disaster if there is a large gap between the
previous section and the group.
PR gold/20878
* powerpc.cc (Stub_control): Replace stubs_always_before_branch_
with stubs_always_after_branch_, group_end_addr_ with
group_start_addr_.
(Stub_control::can_add_to_stub_group): Rewrite to suit scanning
sections by increasing address.
(Target_powerpc::group_sections): Scan that way. Delete corner
case.
* options.h (--stub-group-size): Update help string.
Some more debug output, and a little hardening.
* powerpc.cc (Stub_table_owner): Provide constructor.
(Powerpc_relobj::set_stub_table): Resize fill with -1.
(Target_powerpc::Branch_info::make_stub): Provide target debug
output on returning false.
In the case where we switch to a non-running inferior, we do a
"find_inferior_id (num)", although we did the same call right before.
gdb/ChangeLog:
* inferior.c (inferior_command): Remove duplicate
find_inferior_id call.
PR binutils/20930
* objcopy.c (mark_symbols_used_in_relocations): Check for a null
symbol pointer pointer before attempting to mark the symbol as
kept.
This patch adds asserts where the value's lval must be lval_register.
This triggers an error in frame_register_unwind because VALUE_REGNUM
is used but value's lval is not lval_register.
This also reveals a design issue in frame_register_unwind, that is
arguments addrp and realnump are mutually exclusive, we either use
addrp (for lval_memory), or use realnump (for lval_register). This
can be done in a separate patch.
gdb:
2016-12-06 Yao Qi <yao.qi@linaro.org>
* frame.c (frame_register_unwind): Set *realnump if *lvalp is
lval_register.
* value.c (deprecated_value_next_frame_id_hack): Assert
value->lval is lval_register.
(deprecated_value_regnum_hack): Likewise.
Recognize power9 and a few other insns from older machines. Fixes
linker complaints like "toc optimization is not supported for
0xf4090002 instruction". 0xf4090002 is stxsd v0,0(r9)
bfd/
* elf64-ppc.c (ok_lo_toc_insn): Add r_type param. Recognize
lq,lfq,lxv,lxsd,lxssp,lfdp,stq,stfq,stxv,stxsd,stxssp,stfdp.
Don't match lmd and stmd.
ld/
* testsuite/ld-powerpc/tocopt7.s,
* testsuite/ld-powerpc/tocopt7.out,
* testsuite/ld-powerpc/tocopt7.d: New test.
* testsuite/ld-powerpc/tocopt8.s,
* testsuite/ld-powerpc/tocopt8.d: New test.
* testsuite/ld-powerpc/powerpc.exp: Run them.
Add support for VCMLA and VCADD advanced SIMD complex number instructions.
The command line option is -march=armv8.3-a+fp16+simd for enabling all
instructions.
In arm-dis.c the formatting syntax was abused a bit to select between
0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of
duplicating entries in the opcode table.
gas/
* config/tc-arm.c (do_vcmla, do_vcadd): Define.
(neon_scalar_for_vcmla): Define.
(enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
(NEON_ENC_TAB): Add DDSI and QQSI variants.
(insns): Add vcmla and vcadd.
* testsuite/gas/arm/armv8_3-a-simd.d: New.
* testsuite/gas/arm/armv8_3-a-simd.s: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.s: New.
opcodes/
* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
(print_insn_coprocessor): Add 'V' format for neon D or Q regs.
ARMv8.3 is an architectural extension of ARMv8. Add the
feature macro and -march=armv8.3-a gas command line option
for the ARM target.
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
gas/
* config/tc-arm.c (arm_archs): Add "armv8.3-a".
* doc/c-arm.texi (-march): Add "armv8.3-a".
include/
* opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
(ARM_ARCH_V8_3A): New.
bfd/ChangeLog:
2016-12-05 Alyssa Milburn <amilburn@zall.org>
* elfxx-sparc.c: Do not stop processing relocations after
partially relaxing a call with WDISP30.
ld/ChangeLog:
2016-12-05 Alyssa Milburn <amilburn@zall.org>
* testsuite/ld-sparc/wdispcall.s: New file.
* testsuite/ld-sparc/wdispcall.dd: Likewise.
* testsuite/ld-sparc/sparc.exp: Run new test.
