I found an odd special case for data-directory in gdb's Makefile. I
don't see a reason to have this, so this removes it in favor of having
this code work in the most ordinary way for a subdirectory build.
gdb/ChangeLog
2021-06-01 Tom Tromey <tromey@adacore.com>
* Makefile.in (all-data-directory): Remove.
(data-directory/Makefile): Remove.
The old testsuite configure did not use AS_HELP_STRING, and it had a
typo in the help for --enable-shared. This patch fixes these
problems.
gdb/ChangeLog
2021-06-01 Tom Tromey <tromey@adacore.com>
* configure: Rebuild.
* configure.ac: Use AS_HELP_STRING for enable-shared. Fix typo.
This applies the silent-rules.mk treatment to gdb/testsuite/Makefile.
gdb/ChangeLog
2021-06-01 Tom Tromey <tromey@adacore.com>
* silent-rules.mk (ECHO_CC): New variable.
gdb/testsuite/ChangeLog
2021-06-01 Tom Tromey <tromey@adacore.com>
* Makefile.in (all): Don't print anything.
($(abs_builddir)/site.exp site.exp): Use $(ECHO_GEN).
(expect-read1): Likewise.
(read1.so): Use $(ECHO_CC).
Include silent-rules.mk.
gdb's Makefile currently excludes testsuite from the subdirectories to
build. I don't think there's a good reason for this, so this patch
adds testsuite to the SUBDIRS list and removes a special case from
'all'.
gdb/ChangeLog
2021-06-01 Tom Tromey <tromey@adacore.com>
* Makefile.in (SUBDIRS): Add testsuite.
(all): Don't exclude testsuite.
I didn't see a strong reason to have a separate configure script in
gdb/testsuite, so this patch removes it. The few relevant configury
bits are moved into gdb's configure script. Some of the old
testsuite/configure script (e.g., the header check) is dead code.
This also adds a Makefile rule to rebuild lib/pdtrace. This was
missing from the old code.
'read1' is now a dependency of check-read1, rather than extra code at
configure time.
Finally, the old "ENABLE_LIBCTF" subst in gdb/configure was not used;
nor was the variable defined, so this was always empty. However, the
lower-case variant was used by the testsuite, so this patch renames
the subst.
gdb/ChangeLog
2021-06-01 Tom Tromey <tromey@adacore.com>
* configure.ac: Copy some code from testsuite/configure.ac.
(enable_libctf): Subst this, not ENABLE_LIBCTF.
* configure: Rebuild.
gdb/testsuite/ChangeLog
2021-06-01 Tom Tromey <tromey@adacore.com>
* aclocal.m4, configure.ac, configure: Remove.
* Makefile.in (EXTRA_RULES): Remove.
($(abs_builddir)/site.exp site.exp): Don't depend on
config.status.
(distclean maintainer-clean realclean, Makefile): Update.
(config.status): Remove target.
(lib/pdtrace): New target.
(all): Don't depend on EXTRA_RULES.
(check-read1): Depend on read1.so, expect-read1.
Consider the test-case contained in this patch, compiled for c using gcc-10:
...
$ gcc-10 -x c src/gdb/testsuite/gdb.cp/cold-clone.cc -O2 -g -Wall -Wextra
...
When setting a breakpoint on foo, we get one breakpoint location:
...
$ gdb -q -batch a.out -ex "b foo"
Breakpoint 1 at 0x400560: file cold-clone.cc, line 28.
...
However, when we compile for c++ instead, we get two breakpoint locations:
...
$ gdb -q -batch a.out -ex "b foo" -ex "info break"
Breakpoint 1 at 0x400430: foo. (2 locations)
Num Type Disp Enb Address What
1 breakpoint keep y <MULTIPLE>
1.1 y 0x0000000000400430 in foo() at cold-clone.cc:30
1.2 y 0x0000000000400560 in foo() at cold-clone.cc:28
...
The additional breakpoint location at 0x400430 corresponds to the cold clone:
...
$ nm a.out | grep foo
0000000000400560 t _ZL3foov
0000000000400430 t _ZL3foov.cold
...
which demangled looks like this:
...
$ nm -C a.out | grep foo
0000000000400560 t foo()
0000000000400430 t foo() [clone .cold]
...
[ Or, in the case of the cc1 mentioned in PR23710:
...
$ nm cc1 | grep do_rpo_vn.*cold
000000000058659d t \
_ZL9do_rpo_vnP8functionP8edge_defP11bitmap_headbb.cold.138
$ nm -C cc1 | grep do_rpo_vn.*cold
000000000058659d t \
do_rpo_vn(function*, edge_def*, bitmap_head*, bool, bool) [clone .cold.138]
... ]
The cold clone is a part of the function that is split off from the rest of
the function because it's considered cold (not frequently executed). So while
the symbol points to code that is part of a function, it doesn't point to a
function entry, so the desirable behaviour for "break foo" is to ignore this
symbol.
When compiling for c, the symbol "foo.cold" is entered as minimal symbol
with the search name "foo.cold", and the lookup using "foo" fails to find that
symbol.
But when compiling for c++, the symbol "foo.cold" is entered as minimal symbol
with both the mangled and demangled name, and for the demangled name
"foo() [clone .cold]" we get the search name "foo" (because
cp_search_name_hash stops hashing at '('), and the lookup using "foo" succeeds.
Fix this by recognizing the cold clone suffix and returning false for such a
minimal symbol in msymbol_is_function.
Tested on x86_64-linux.
gdb/ChangeLog:
2021-06-01 Tom de Vries <tdevries@suse.de>
PR symtab/26096
* minsyms.c (msymbol_is_cold_clone): New function.
(msymbol_is_function): Use msymbol_is_cold_clone.
gdb/testsuite/ChangeLog:
2021-06-01 Tom de Vries <tdevries@suse.de>
PR symtab/26096
* gdb.cp/cold-clone.cc: New test.
* gdb.cp/cold-clone.exp: New file.
I spotted that 'maint selftest' with an executable loaded into GDB,
would (when GDB was compiled for all targets) crash GDB. I fixed this
with a commit to bfd:
commit 427e4066af
Date: Thu May 20 09:16:41 2021 +0100
gdb/bfd: avoid crash when architecture is forced to csky or riscv
However, this issue was not spotted as we currently only run 'maint
selftest' without an executable loaded.
This commit extends the testsuite to run 'maint selftest' both with
and without an executable loaded into GDB.
Currently, when no executable is loaded into GDB all of the selftest
pass (i.e. the fail count is 0), however, when running with an
executable loaded, I am seeing 1 failure (on an x86-64 GNU/Linux
host).
This failure is from the ARM disassembler tests, it appears that the
disassembler somehow gets itself into a state where it thinks it is in
thumb mode; when running the same test without an executable loaded
this doesn't happen.
This commit doesn't fix the ARM disassembler issue, but I thought it
was worth adding this anyway, as this will spot if GDB again starts to
crash when 'maint selftest' is run.
gdb/testsuite/ChangeLog:
* gdb.gdb/unittest.c: New file.
* gdb.gdb/unittest.exp: Run with and without a binary file loaded
into GDB.
This commit adds support for bare metal core dumps on the ARM target,
and is based off of this patch submitted to the mailing list:
https://sourceware.org/pipermail/gdb-patches/2020-October/172845.html
Compared to the version linked above this version is updated to take
account of recent changes to the core dump infrastructure in GDB,
there is now more shared infrastructure for core dumping within GDB,
and also some common bare metal core dumping infrastructure. As a
result this patch is smaller than the original proposed patch.
Further, the original patch included some unrelated changes to the
simulator that have been removed from this version.
I have written a ChangeLog entry as the original patch was missing
one.
I have done absolutely no testing of this patch. It is based on the
original submitted patch, which I assume was tested, but after my
modifications things might have been broken, however, the original
patch author has tested this version and reported it as being good:
https://sourceware.org/pipermail/gdb-patches/2021-May/178900.html
The core dump format is based around generating an ELF containing
sections for the writable regions of memory that a user could be
using. Which regions are dumped rely on GDB's existing common core
dumping code, GDB will attempt to figure out the stack and heap as
well as copying out writable data sections as identified by the
original ELF.
Register information is added to the core dump using notes, just as it
is for Linux of FreeBSD core dumps. The note types used consist of
the 2 basic types you would expect in a OS based core dump,
NT_PRPSINFO, NT_PRSTATUS, along with the architecture specific
NT_ARM_VFP note.
The data layouts for each note type are described below, in all cases,
all padding fields should be set to zero.
Note NT_PRPSINFO is optional. Its data layout is:
struct prpsinfo_t
{
uint8_t padding[28];
char fname[16];
char psargs[80];
}
Field 'fname' - null terminated string consisting of the basename of
(up to the fist 15 characters of) the executable. Any additional
space should be set to zero. If there's no executable name then
this field can be set to all zero.
Field 'psargs' - a null terminated string up to 80 characters in
length. Any additional space should be filled with zero. This
field contains the full executable path and any arguments passed
to the executable. If there's nothing sensible to write in this
field then fill it with zero.
Note NT_PRSTATUS is required, its data layout is:
struct prstatus_t
{
uint8_t padding_1[12];
uint16_t sig;
uint8_t padding_2[10];
uint32_t thread_id;
uint8_t padding_3[44];
uint32_t gregs[18];
}
Field 'sig' - the signal that stopped this thread. It's implementation
defined what this field actually means. Within GDB this will be
the signal number that the remote target reports as the stop
reason for this thread.
Field 'thread_is' - the thread id for this thread. It's implementation
defined what this field actually means. Within GDB this will be
thread thread-id that is assigned to each remote thread.
Field 'gregs' - holds the general purpose registers $a1 through to $pc
at indices 0 to 15. At index 16 the program status register.
Index 17 should be set to zero.
Note NT_ARM_VFP is optional, its data layout is:
armvfp_t
{
uint64_t regs[32];
uint32_t fpscr;
}
Field 'regs' - holds the 32 d-registers 0 to 31 in order.
Field 'fpscr' - holds the fpscr register.
The rules for ordering the notes is the same as for Linux. The
NT_PRSTATUS note must come before any other notes about additional
register sets. And for multi-threaded targets all registers for a
single thread should be grouped together. This is because only
NT_PRSTATUS includes a thread-id, all additional register notes after
a NT_PRSTATUS are assumed to belong to the same thread until a
different NT_PRSTATUS is seen.
gdb/ChangeLog:
PR gdb/14383
* Makefile.in (ALL_TARGET_OBS): Add arm-none-tdep.o.
(ALLDEPFILES): Add arm-none-tdep.c
* arm-none-tdep.c: New file.
* configure.tgt (arm*-*-*): Add arm-none-tdep.o to cpu_obs.
Consider the following chain of events:
* GDB is performing an inferior call, and
* the inferior calls longjmp, and
* GDB detects that the longjmp has completed, stops, and enters
check_longjmp_breakpoint_for_call_dummy (in breakpoint.c), and
* GDB tries to unwind the stack in order to check that the dummy
frame (setup for the inferior call) is still on the stack, but
* The unwind fails, possibly due to missing debug information, so
* GDB incorrectly concludes that the inferior has longjmp'd past the
dummy frame, and so deletes the dummy frame, including the dummy
frame breakpoint, but then
* The inferior continues, and eventually returns to the dummy frame,
which is usually (always?) on the stack, the inferior starts
trying to execute the random contents of the stack, this results
in undefined behaviour.
This situation is already warned about in the comment on the function
check_longjmp_breakpoint_for_call_dummy where we say:
You should call this function only at places where it is safe to currently
unwind the whole stack. Failed stack unwind would discard live dummy
frames.
The warning here is fine, the problem is that, even though we call the
function from a location within GDB where we hope to be able to
unwind, sometime the state of the inferior means that the unwind will
not succeed.
This commit tries to improve the situation by adding the following
additional check; when GDB fails to find the dummy frame on the stack,
instead of just assuming that the dummy frame can be garbage
collected, first find the stop_reason for the last frame on the stack.
If this stop_reason indicates that the stack unwinding may have failed
then we assume that the dummy frame is still in use. However, if the
last frame's stop_reason indicates that the stack unwind completed
successfully then we can be confident that the dummy frame is no
longer in use, and we garbage collect it.
Tested on x86-64 GNU/Linux.
gdb/ChangeLog:
* breakpoint.c (check_longjmp_breakpoint_for_call_dummy): Add
check for why the backtrace stopped.
gdb/testsuite/ChangeLog:
* gdb.base/premature-dummy-frame-removal.c: New file.
* gdb.base/premature-dummy-frame-removal.exp: New file.
* gdb.base/premature-dummy-frame-removal.py: New file.
Change-Id: I8f330cfe0f3f33beb3a52a36994094c4abada07e
All signatured_type constucted (even those used only for lookups in hash
maps) need a signature. Enforce that by passing the signature all the
way to the signatured_type constructor.
gdb/ChangeLog:
* dwarf2/read.h (struct structured_type) <signatured_type>: New.
Update all callers.
(struct dwarf2_per_bfd) <allocate_signatured_type>: Add
signature parameter, update all callers.
* dwar2/read.c (dwarf2_per_bfd::allocate_signatured_type): Add
signature parameter.
Change-Id: I99bc1f88f54127666aa133ddbbabb7f7668fa14a
Add an alias for std::unique_ptr<signatured_type> and use it where
possible.
gdb/ChangeLog:
* dwarf2/read.h (signatured_type_up): New, use where possible.
Change-Id: I5a41e8345551434c8beeb9f269b03bdcf27989be
Move them up before dwarf2_per_bfd, this will allow adding and using
signatured_type_up in the next patch.
gdb/ChangeLog:
* dwarf2/read.h (signatured_type, dwarf2_per_cu_data): Move up.
Change-Id: I85acad4476c8236930b6f9e53ddb8bbbad009e5e
2021-05-31 Nelson Chu <nelson.chu@sifive.com>
Lifang Xia <lifang_xia@c-sky.com>
The data segment phase exp_seg_relro_adjust means we are still adjusting the
relro segments, so we will get the symbol values which havn't consider the
relro. It is dangerous and we shouldn't do the relaxations at this stage.
Otherwise, we may get the truncated fails when the relax range crossing the
data segment.
One of the solution is that, we use a pointer to monitor the data segment
phase while relaxing, to know whether the relro has been handled or not.
Once we check the phase is exp_seg_relro_adjust, we should skip this round
of relaxations, since the incorrect symbol values will affect the correctness
of relaxations. I think we probably need to record more information about
data segment or alignments in the future, to make sure it is safe to doing
relaxations.
For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get
the following truncated errors when using toolchains, which enable relro:
(.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o
After applying this patch, the truncated errors should be resolved.
However, only linux toolchains support -z relro, so we only test these
two testcases when supporting shared library.
bfd/
PR 27566
* elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer
to monitor the data segment phase.
(bfd_elfNN_riscv_set_data_segment_info): New function called by
after_allocation, to set the data_segment_phase from expld.dataseg.
(_bfd_riscv_relax_section): Don't relax when data_segment_phase is
exp_seg_relro_adjust (0x4).
* elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern.
(bfd_elf64_riscv_set_data_segment_info): Likewise.
ld/
PR 27566
* emultempl/riscvelf.em (after_allocation): Call
riscv_set_data_segment_info to set data segment phase before relaxing.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase.
* testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
All callers of allocate_signatured_type set the is_debug_types flag on
the result -- in fact, they are required to, because this is the sign
that downcasting the object to signatured_type is safe. This patch
moves this assignment into the allocation function.
2021-05-30 Tom Tromey <tom@tromey.com>
* dwarf2/read.c (dwarf2_per_bfd::allocate_signatured_type): Set
is_debug_types.
(create_signatured_type_table_from_index)
(create_signatured_type_table_from_debug_names, add_type_unit)
(read_comp_units_from_section): Update.
Now that CUs and TUs are stored together in all_comp_units, the
m_num_psymtabs member is no longer needed -- it is always identical to
the length of the vector. This patch removes it.
2021-05-30 Tom Tromey <tom@tromey.com>
* dwarf2/read.h (struct dwarf2_per_bfd) <num_psymtabs,
m_num_psymtabs>: Remove.
(resize_symtabs): Update.
* dwarf2/read.c (dwarf2_per_bfd::allocate_per_cu)
(dwarf2_per_bfd::allocate_signatured_type): Update.
If the OS headers define the "errno" symbol, it breaks some of these
funcs that were using "int errno" itself. Rename local vars to "err"
to avoid that, and delete the old "extern int errno".
The execv prototypes on Windows via mingw64 include extra const
markings on the argv/envp pointers than what POSIX specifies.
Cast them to void* as a hack to get it working on all platforms.
This is a bit of a hack, but it matches the hack we use in other
places in the sim currently. This fixes building for e.g. Windows.
The signal fallback logic needs a bit of love in general at some
point across all sim code.
Some modules might require extra linking depending on the platform
(e.g. Windows might need -lws2_32), so include the existing extra
gnulib libs setting.
Argument fobj was only available in the constructor.
gdb/doc/ChangeLog:
2021-05-29 Hannes Domani <ssbssa@yahoo.de>
* python.texi (Writing a Frame Filter): Fix example.
opcodes/
* ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
Don't special case PPC_OPCODE_RAW.
(lookup_prefix): Likewise.
(lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
(print_insn_powerpc): ..update caller.
* ppc-opc.c (EXT): Define.
(powerpc_opcodes): Mark extended mnemonics with EXT.
(prefix_opcodes, vle_opcodes): Likewise.
(XISEL, XISEL_MASK): Add cr field and simplify.
(powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
all isel variants to where the base mnemonic belongs. Sort dstt,
dststt and dssall.
gas/
* testsuite/gas/ppc/raw.s,
* testsuite/gas/ppc/raw.d: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Splitting up help strings makes it more likely that at least some of
the help translation survives adding new options.
* readelf.c (parse_args): Call dwarf_select_sections_all on
--debug-dump without optarg.
(usage): Associate -w and --debug-dump options closely.
Split up help message. Remove extraneous blank lines around
ctf help.
* objdump.c (usage): Similarly.
Group legacy instructions using the COP0, COP2, COP3 opcodes together
and by their coprocessor number, and move them towards the end of the
opcode table. No functional change.
With the addition of explicit ISA exclusions this is maybe not strictly
necessary anymore as the individual legacy instructions are not supposed
to match ISA levels or CPU implementations that have discarded them or
replaced with a new instruction each, but let's not have them scattered
randomly across blocks of unrelated instruction sets where someone chose
to put them previously. Perhaps they could be put back in alphabetical
order in the main instruction block, but let's leave it for another
occasion.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
COP3 opcode instructions.
Add tests for the generic C0, C1, C2, C3 coprocessor instructions.
gas/
* testsuite/gas/mips/c0.d: New test.
* testsuite/gas/mips/mips1@c0.d: New test.
* testsuite/gas/mips/mips2@c0.d: New test.
* testsuite/gas/mips/mips3@c0.d: New test.
* testsuite/gas/mips/mips4@c0.d: New test.
* testsuite/gas/mips/mips5@c0.d: New test.
* testsuite/gas/mips/mips32@c0.d: New test.
* testsuite/gas/mips/mips64@c0.d: New test.
* testsuite/gas/mips/r3000@c0.d: New test.
* testsuite/gas/mips/r3900@c0.d: New test.
* testsuite/gas/mips/r4000@c0.d: New test.
* testsuite/gas/mips/vr5400@c0.d: New test.
* testsuite/gas/mips/r5900@c0.d: New test.
* testsuite/gas/mips/sb1@c0.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c0.d: New test.
* testsuite/gas/mips/octeon@c0.d: New test.
* testsuite/gas/mips/xlr@c0.d: New test.
* testsuite/gas/mips/c1.d: New test.
* testsuite/gas/mips/mips1@c1.d: New test.
* testsuite/gas/mips/mips2@c1.d: New test.
* testsuite/gas/mips/mips3@c1.d: New test.
* testsuite/gas/mips/mips4@c1.d: New test.
* testsuite/gas/mips/mips5@c1.d: New test.
* testsuite/gas/mips/mips32@c1.d: New test.
* testsuite/gas/mips/mips64@c1.d: New test.
* testsuite/gas/mips/mipsr6@c1.d: New test.
* testsuite/gas/mips/r3000@c1.d: New test.
* testsuite/gas/mips/r3900@c1.d: New test.
* testsuite/gas/mips/r4000@c1.d: New test.
* testsuite/gas/mips/vr5400@c1.d: New test.
* testsuite/gas/mips/r5900@c1.d: New test.
* testsuite/gas/mips/sb1@c1.d: New test.
* testsuite/gas/mips/interaptiv-mr2@c1.d: New test.
* testsuite/gas/mips/octeon@c1.d: New test.
* testsuite/gas/mips/xlr@c1.d: New test.
* testsuite/gas/mips/c2.d: New test.
* testsuite/gas/mips/vr5400@c2.d: New test.
* testsuite/gas/mips/r5900@c2.d: New test.
* testsuite/gas/mips/octeon@c2.d: New test.
* testsuite/gas/mips/c3.d: New test.
* testsuite/gas/mips/mips1@c3.d: New test.
* testsuite/gas/mips/mips2@c3.d: New test.
* testsuite/gas/mips/mips32@c3.d: New test.
* testsuite/gas/mips/r3000@c3.d: New test.
* testsuite/gas/mips/r3900@c3.d: New test.
* testsuite/gas/mips/c0.l: New test stderr output.
* testsuite/gas/mips/c2.l: New test stderr output.
* testsuite/gas/mips/c3.l: New test stderr output.
* testsuite/gas/mips/c0.s: New test source.
* testsuite/gas/mips/c1.s: New test source.
* testsuite/gas/mips/c2.s: New test source.
* testsuite/gas/mips/c3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Verify that the RFE instruction is not only accepted where supported,
but rejected where it is not as well.
gas/
* testsuite/gas/mips/mips.exp: Run RFE test across all ISAs.
* testsuite/gas/mips/rfe.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@rfe.d: New test.
* testsuite/gas/mips/mips2@rfe.d: New test.
* testsuite/gas/mips/r3000@rfe.d: New test.
* testsuite/gas/mips/r3900@rfe.d: New test.
* testsuite/gas/mips/rfe.l: New test stderr output.
Verify that individual coprocessor instructions are not only accepted
where supported, but rejected where they are not as well.
gas/
* testsuite/gas/mips/mips.exp: Run coprocessor tests across all
ISAs.
* testsuite/gas/mips/cp0b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0c.d: Update for ISA exclusions.
* testsuite/gas/mips/cp0m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3b.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3bl.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3m.d: Update for ISA exclusions.
* testsuite/gas/mips/cp3d.d: Update for ISA exclusions.
* testsuite/gas/mips/mips1@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0b.d: New test.
* testsuite/gas/mips/mips3@cp0b.d: New test.
* testsuite/gas/mips/r3000@cp0b.d: New test.
* testsuite/gas/mips/r3900@cp0b.d: New test.
* testsuite/gas/mips/r4000@cp0b.d: New test.
* testsuite/gas/mips/r5900@cp0b.d: New test.
* testsuite/gas/mips/mips2@cp0bl.d: New test.
* testsuite/gas/mips/mips3@cp0bl.d: New test.
* testsuite/gas/mips/r3900@cp0bl.d: New test.
* testsuite/gas/mips/r4000@cp0bl.d: New test.
* testsuite/gas/mips/r5900@cp0bl.d: New test.
* testsuite/gas/mips/mips1@cp0c.d: New test.
* testsuite/gas/mips/mips2@cp0c.d: New test.
* testsuite/gas/mips/mips3@cp0c.d: New test.
* testsuite/gas/mips/mips4@cp0c.d: New test.
* testsuite/gas/mips/mips5@cp0c.d: New test.
* testsuite/gas/mips/r3000@cp0c.d: New test.
* testsuite/gas/mips/r3900@cp0c.d: New test.
* testsuite/gas/mips/r4000@cp0c.d: New test.
* testsuite/gas/mips/vr5400@cp0c.d: New test.
* testsuite/gas/mips/r5900@cp0c.d: New test.
* testsuite/gas/mips/mips1@cp0m.d: New test.
* testsuite/gas/mips/r3000@cp0m.d: New test.
* testsuite/gas/mips/octeon@cp2.d: New test.
* testsuite/gas/mips/mipsr6@cp2b.d: New test.
* testsuite/gas/mips/vr5400@cp2b.d: New test.
* testsuite/gas/mips/octeon@cp2b.d: New test.
* testsuite/gas/mips/mips1@cp2bl.d: New test.
* testsuite/gas/mips/mipsr6@cp2bl.d: New test.
* testsuite/gas/mips/r3000@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2bl.d: New test.
* testsuite/gas/mips/octeon@cp2bl.d: New test.
* testsuite/gas/mips/vr5400@cp2m.d: New test.
* testsuite/gas/mips/r5900@cp2m.d: New test.
* testsuite/gas/mips/octeon@cp2m.d: New test.
* testsuite/gas/mips/mips1@cp2d.d: New test.
* testsuite/gas/mips/r3000@cp2d.d: New test.
* testsuite/gas/mips/r3900@cp2d.d: New test.
* testsuite/gas/mips/vr5400@cp2d.d: New test.
* testsuite/gas/mips/r5900@cp2d.d: New test.
* testsuite/gas/mips/octeon@cp2d.d: New test.
* testsuite/gas/mips/mips1@cp2-64.d: New test.
* testsuite/gas/mips/mips2@cp2-64.d: New test.
* testsuite/gas/mips/mips32@cp2-64.d: New test.
* testsuite/gas/mips/mips32r2@cp2-64.d: New test.
* testsuite/gas/mips/mips32r3@cp2-64.d: New test.
* testsuite/gas/mips/mips32r5@cp2-64.d: New test.
* testsuite/gas/mips/mips32r6@cp2-64.d: New test.
* testsuite/gas/mips/r3000@cp2-64.d: New test.
* testsuite/gas/mips/r3900@cp2-64.d: New test.
* testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test.
* testsuite/gas/mips/mips1@cp3.d: New test.
* testsuite/gas/mips/mips2@cp3.d: New test.
* testsuite/gas/mips/mips32@cp3.d: New test.
* testsuite/gas/mips/r3000@cp3.d: New test.
* testsuite/gas/mips/r3900@cp3.d: New test.
* testsuite/gas/mips/mips1@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3b.d: New test.
* testsuite/gas/mips/mips32@cp3b.d: New test.
* testsuite/gas/mips/r3000@cp3b.d: New test.
* testsuite/gas/mips/r3900@cp3b.d: New test.
* testsuite/gas/mips/mips2@cp3bl.d: New test.
* testsuite/gas/mips/mips32@cp3bl.d: New test.
* testsuite/gas/mips/r3900@cp3bl.d: New test.
* testsuite/gas/mips/mips1@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3m.d: New test.
* testsuite/gas/mips/r3000@cp3m.d: New test.
* testsuite/gas/mips/r3900@cp3m.d: New test.
* testsuite/gas/mips/mips2@cp3d.d: New test.
* testsuite/gas/mips/cp0b.l: New test stderr output.
* testsuite/gas/mips/cp0bl.l: New test stderr output.
* testsuite/gas/mips/cp0c.l: New test stderr output.
* testsuite/gas/mips/cp0m.l: New test stderr output.
* testsuite/gas/mips/cp2.l: New test stderr output.
* testsuite/gas/mips/cp2-64.l: New test stderr output.
* testsuite/gas/mips/cp2b.l: New test stderr output.
* testsuite/gas/mips/cp2bl.l: New test stderr output.
* testsuite/gas/mips/cp2m.l: New test stderr output.
* testsuite/gas/mips/cp2d.l: New test stderr output.
* testsuite/gas/mips/cp3.l: New test stderr output.
* testsuite/gas/mips/cp3b.l: New test stderr output.
* testsuite/gas/mips/cp3bl.l: New test stderr output.
* testsuite/gas/mips/cp3m.l: New test stderr output.
* testsuite/gas/mips/cp3d.l: New test stderr output.
Adjust opcode table entries for coprocessor instructions that have been
removed from certain ISA levels or CPU implementations as follows:
- remove CP0 memory access instructions from MIPS II up as the LWC0 and
SWC0 opcodes have been reused for the LL and SC instructions
respectively[1]; strictly speaking LWC0 and SWC0 have never really
been defined in the first place[2], but let's keep them for now in
case an odd implementation did,
- remove CP0 branch instructions from MIPS IV[3] and MIPS32[4] up, as
they have been removed as from those ISAs,
- remove CP0 control register move instructions from MIPS32 up, as they
have been removed as from that ISA[5],
- remove the RFE instruction from MIPS III[6] and MIPS32[7] up, as it
has been removed as from those ISAs in favour to ERET,
- remove CP2 instructions from Vr5400 CPUs as their encodings have been
reused for the multimedia instruction set extensions[8] and no CP2
registers exist[9],
- remove CP3 memory access instructions from MIPS III up as coprocessor
3 has been removed as from that ISA[10][11] and from MIPS32 up as the
LWC3 opcode has been reused for the PREF instruction and consequently
all the four memory access instructions removed from the ISA (though
the COP3 opcode has been retained)[12].
Update the testsuite accordingly.
References:
[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Table A-38 "CPU Instruction Encoding
- MIPS II Architecture", p. A-178
[2] same, Section A.2.5.1 "Coprocessor Load and Store", p. A-12
[3] "MIPS R10000 Microprocessor User's Manual", Version 2.0, MIPS
Technologies, Inc., January 29, 1997, Section 14.25 "CP0
Instructions", Subsection "Branch on Coprocessor 0", p. 285
[4] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number:
MD00086, Revision 1.00, June 9, 2003, Table A-9 "MIPS32 COP0
Encoding of rs Field", p. 242
[5] same
[6] Joe Heinrich, "MIPS R4000 Microprocessor User's Manual", Second
Edition, MIPS Technologies, Inc., April 1, 1994, Figure A-2 "R4000
Opcode Bit Encoding", p. A-182
[8] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 1",
NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
Section 1.2.3 "CPU Instruction Set Overview", p. 9
[9] "Vr5432 64-bit MIPS RISC Microprocessor User's Manual, Volume 2",
NEC Electronics Inc., Document No. U13751EU5V0UM00, May 2000,
Section 19.2 "Multimedia Instruction Format", p. 681
[10] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 -
COP3 and CP3 load/store", p. A-176
[11] same, Table A-39 "CPU Instruction Encoding - MIPS III
Architecture", p. A-179
[12] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number:
MD00086, Revision 1.00, August 29, 2002, Table A-2 "MIPS32 Encoding
of the Opcode Field", p. 241
opcodes/
* mips-opc.c (mips_builtin_opcodes): Update exclusion list for
"ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
"swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
"bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
"bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
"mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
"cop2", and "cop3" entries.
gas/
* testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3
instruction removal.
* testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
Coprocessor 3 has been removed from the MIPS ISA as from MIPS III[1][2]
with the LDC3 and SDC3 instructions having been replaced with LD and SD
instructions respectively and therefore the doubleword move instructions
from and to that coprocessor have never materialized (for 32-bit ISAs
coprocessor 3 has likewise been removed as from MIPS32r2[3]). Remove
the DMFC3 and DMTC3 instructions from the opcode table then to avoid
confusion.
References:
[1] Charles Price, "MIPS IV Instruction Set", MIPS Technologies, Inc.,
Revision 3.2, September, 1995, Section A 8.3.4 "Coprocessor 3 - COP3
and CP3 load/store", p. A-176
[2] same, Table A-39 "CPU Instruction Encoding - MIPS III Architecture",
p. A-179
[3] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 2.00, June 9, 2003, Table A-2 "MIPS32 Encoding of the
Opcode Field", p. 317
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
entries and associated comments.
Cover basic CP0, CP2, CP3 branch and branch-likely instructions across
the relevant ISA levels. Omit CP1 branches, covered elsewhere.
gas/
* testsuite/gas/mips/cp0b.d: New test.
* testsuite/gas/mips/cp0bl.d: New test.
* testsuite/gas/mips/cp2b.d: New test.
* testsuite/gas/mips/micromips@cp2b.d: New test.
* testsuite/gas/mips/cp2bl.d: New test.
* testsuite/gas/mips/micromips@cp2bl.d: New test.
* testsuite/gas/mips/cp3b.d: New test.
* testsuite/gas/mips/cp3bl.d: New test.
* testsuite/gas/mips/cp0b.s: New test source.
* testsuite/gas/mips/cp0bl.s: New test source.
* testsuite/gas/mips/cp2b.s: New test source.
* testsuite/gas/mips/cp2bl.s: New test source.
* testsuite/gas/mips/cp3b.s: New test source.
* testsuite/gas/mips/cp3bl.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Fix a commit b015e599c7 ("[MIPS] Add new virtualization instructions"),
<https://sourceware.org/ml/binutils/2013-05/msg00118.html>, regression
and bring the disassembly of the RFE instruction back for the relevant
ISA levels.
It is because the "rfe" opcode table entry was incorrectly moved behind
the catch-all generic "c0" entry for CP0 instructions, causing output
like:
00: 42000010 c0 0x10
to be produced rather than:
00: 42000010 rfe
even for ISA levels that do include the RFE instruction.
Move the "rfe" entry ahead of "c0" then, correcting the problem. Add a
suitable test case.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
of "c0".
gas/
* testsuite/gas/mips/rfe.d: New test.
* testsuite/gas/mips/rfe.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and
handle the exclusion for any ISA levels properly in `opcode_is_member'.
Flatten the structure of the `if' statements there. No functional
change for the existing opcode tables.
include/
* opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA
exclusion.
(opcode_is_member): Handle ISA level exclusion.
In preparation for the next change factor out code for ISA matching
against instruction flags used in MIPS opcode tables, similarly to how
CPU matching is already done. No functional change, though for clarity
split the single `if' statement into multiple ones and use temporaries
rather than repeated expressions.
include/
* opcode/mips.h (isa_is_member): New inline function, factored
out from...
(opcode_is_member): ... here.
The two CP1 control registers defined by legacy ISAs used to be referred
to by various names, such as FCR0, FCR31, FSR, however their documented
full names have always been the Implementation and Revision, and Control
and Status respectively, so the FIR and FCSR acronyms coming from modern
ISA revisions will be just as unambiguous while improving the clarity of
disassembly. Do not update the TX39 though as it did not have an FPU.
opcodes/
* mips-dis.c (mips_cp1_names_mips): New variable.
(mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
"r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
"r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
"r12000", "r14000", "r16000", "mips5", "loongson2e", and
"loongson2f".
gas/
* testsuite/gas/mips/cp1-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
* testsuite/gas/mips/branch-misc-3.d: Update disassembly
according to changes to opcodes.
* testsuite/gas/mips/cp1-names-r3000.d: Likewise.
* testsuite/gas/mips/cp1-names-r4000.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips1.d: Likewise.
* testsuite/gas/mips/relax-swap1-mips2.d: Likewise.
* testsuite/gas/mips/trunc.d: Likewise.
Cover basic CP0, CP2, CP3 move, load and store instructions across the
relevant ISA levels. Omit CP0 move and CP1 instructions as they are
covered elsewhere.
gas/
* testsuite/gas/mips/cp0c.d: New test.
* testsuite/gas/mips/cp0m.d: New test.
* testsuite/gas/mips/r3900@cp0m.d: New test.
* testsuite/gas/mips/cp2.d: New test.
* testsuite/gas/mips/micromips@cp2.d: New test.
* testsuite/gas/mips/cp2m.d: New test.
* testsuite/gas/mips/mipsr6@cp2m.d: New test.
* testsuite/gas/mips/micromips@cp2m.d: New test.
* testsuite/gas/mips/cp2d.d: New test.
* testsuite/gas/mips/mipsr6@cp2d.d: New test.
* testsuite/gas/mips/micromips@cp2d.d: New test.
* testsuite/gas/mips/cp2-64.d: New test.
* testsuite/gas/mips/micromips@cp2-64.d: New test.
* testsuite/gas/mips/cp3.d: New test.
* testsuite/gas/mips/cp3m.d: New test.
* testsuite/gas/mips/cp3d.d: New test.
* testsuite/gas/mips/cp0c.s: New test source.
* testsuite/gas/mips/cp0m.s: New test source.
* testsuite/gas/mips/cp2.s: New test source.
* testsuite/gas/mips/cp2m.s: New test source.
* testsuite/gas/mips/cp2d.s: New test source.
* testsuite/gas/mips/cp2-64.s: New test source.
* testsuite/gas/mips/cp3.s: New test source.
* testsuite/gas/mips/cp3m.s: New test source.
* testsuite/gas/mips/cp3d.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
The CP0 control register set has never been defined, however encodings
for the CFC0 and CTC0 instructions remained available for implementers
up until the MIPS32 ISA declared them invalid and causing the Reserved
Instruction exception[1]. Therefore we handle them for both assembly
and disassembly, however in the latter case the names of CP0 registers
from the regular set are incorrectly printed if named registers are
requested. This is because we do not define separate operand classes
for coprocessor regular and control registers respectively, which means
the disassembler has no way to tell the two cases apart. Consequently
nonsensical disassembly is produced like:
cfc0 v0,c0_random
Later the MIPSr5 ISA reused the encodings for XPA ASE MFHC0 and MTHC0
instructions[2] although it failed to document them in the relevant
opcode table until MIPSr6 only.
Correct the issue then by defining a new register class, OP_REG_CONTROL,
and corresponding operand codes, `g' and `y' for the two positions in
the machine instruction a control register operand can take. Adjust the
test cases affected accordingly.
While at it swap the regular MIPS opcode table "cfc0" and "ctc0" entries
with each other so that they come in the alphabetical order.
References:
[1] "MIPS32 Architecture For Programmers, Volume II: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 1.00, August 29, 2002, Table A-9 "MIPS32 COP0 Encoding of
rs Field", p. 242
[2] "MIPS Architecture For Programmers, Volume II-A: The MIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00086,
Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of
Instructions", pp. 195, 216
include/
* opcode/mips.h: Document `g' and `y' operand codes.
(mips_reg_operand_type): Add OP_REG_CONTROL enumeration
constant.
gas/
* tc-mips.c (convert_reg_type) <OP_REG_CONTROL>: New case.
(macro) <M_TRUNCWS, M_TRUNCWD>: Use the `g' rather than `G'
operand code.
opcodes/
* mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
handling code over to...
<OP_REG_CONTROL>: ... this new case.
* mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
(mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
"cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
replacing the `G' operand code with `g'. Update "cftc1" and
"cftc2" entries replacing the `E' operand code with `y'.
* micromips-opc.c (decode_micromips_operand) <'g'>: New case.
(micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
entries replacing the `G' operand code with `g'.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Correct CFC0
operand disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
The TX39 core has its distinct set of CP0 registers[1], so it needs a
separate table to hold their names. Add a test case accordingly.
References:
[1] "32-Bit RISC Microprocessor TX39 Family Core Architecture User's
Manual", Toshiba, Jul. 27, 1995, Section 2.2.2 "System control
coprocessor (CP0) registers", pp. 9-10
opcodes/
* mips-dis.c (mips_cp0_names_r3900): New variable.
(mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
for "r3900".
gas/
* testsuite/gas/mips/cp0-names-r3900.d: New test.
* testsuite/gas/mips/mips.exp: Run it.
Fix commit 9785fc2a4d ("MIPS: Fix XPA base and Virtualization ASE
instruction handling") and explicitly use the `mips:3000' machine for
disassembly across the XPA base and XPA Virtualization ASE test cases,
providing actual coverage for the `virt' and `xpa' disassembler options
and removing failures for targets that default to those ASEs enabled:
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa32r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r2el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r3el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r5el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-elf -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 1
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 2
mipsisa64r6el-linux -FAIL: MIPS XPA and Virtualization ASE instruction disassembly 3
This is because the test cases rely on these ASEs being disabled for
disassembly by default and expect instructions belonging to these ASEs
not to be shown unless explicitly enabled. The `mips-xpa-virt-4' test
case passes regardless, but we want it to verify the explicit options do
work, so use the `mips:3000' machine to set the defaults there as well.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: Use `mips:3000'
machine for disassembly.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: Likewise.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: Likewise.
In the operand handling rewrite made for the MIPS disassembler with
commit ab90248154 ("Add structures to describe MIPS operands"),
<https://sourceware.org/ml/binutils/2013-07/msg00135.html>, the `g'
operand code has become redundant for the regular MIPS instruction set
by duplicating the OP_REG_COPRO semantics of the `G' operand code.
Later commit 351cdf24d2 ("Implement O32 FPXX, FP64 and FP64A ABI
extensions") converted the CTTC1 instruction from the `g' to the `G'
operand code, but still left a few instructions behind.
Convert the three remaining instructions still using the `g' code then,
namely: CTTC2, MTTC2 and MTTHC2, and remove all traces of the operand
code, freeing it up for other use.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
and "mtthc2" to using the `G' rather than `g' operand code for
the coprocessor control register referred.
include/
* opcode/mips.h: Complement change made to opcodes and remove
references to the `g' regular MIPS ISA operand code.
