This used to hold a pair of pointers to the previous and next function segment
that belong to this function call. Replace with a pair of indices into the
vector of function segments.
This used to hold a pair of pointers to the previous and next function segment
in execution flow order. It is no longer necessary as the previous and next
function segments now are simply the previous and next elements in the vector
of function segments.
These are no longer needed and might hold invalid addresses once we change the
vector of function segment pointers into a vector of function segment objects
where a reallocation of the vector changes the address of its elements.
Directly insert new btrace_function pointers into the vector and have the
vector own these pointers. This allows us to later retrieve these objects by
their number directly after creation whereas at the moment we have to wait
until the vector is fully populated.
This requires to pull btrace_thread_info through different functions but
cleans up the code for freeing the trace.
Change the GDB 8.0 section of the NEWS file to try to follow this order:
* Functional changes
* Added and removed configurations and targets
* New commands
* New options
* MI changes
In particular, there were two "New commands" sections.
gdb/ChangeLog:
* NEWS (Changes in GDB 8.0): Remove extra empty line. Move
"Removed targets and native configurations" up. Merge duplicate
"New commands" sub-sections. Add "New options" sub-sections.
This test requires calling a function in the inferior, and therefore it
doesn't make sense to run it if the target doesn't support calling
functions from GDB.
gdb/testsuite/ChangeLog:
* gdb.base/watch-cond-infcall.exp: Don't run if target doesn't
support function calls from GDB.
This patch adds missing variants of ipte and idte instructions added with later CPU
generations.
ipte got an optional operand with z196 and another one with zEC12.
idte got an optional operand with zEC12
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-opc.c: Add new idte/ipte variants.
* s390-opc.txt: Likewise.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/s390/zarch-z196.d: Add new idte/ipte variants.
* testsuite/gas/s390/zarch-z196.s: Likewise.
* testsuite/gas/s390/zarch-zEC12.d: Likewise.
* testsuite/gas/s390/zarch-zEC12.s: Likewise.
So far we only had an instruction flag which made an arbitrary number
of operands optional. This limits error checking capabilities for
instructions marked that way. With this patch the optparm flag only
allows a single optional parameter and another one is added (optparm2)
allowing 2 optional arguments. Hopefully we won't need more than that
in the future. So far there will be only a single use of optparm2.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Support new optparm2
instruction flag.
include/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h: Add new instruction flags optparm2.
opcodes/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-dis.c (s390_print_insn_with_opcode): Support new optparm2
instruction flag.
* s390-mkopc.c (main): Recognize the new instruction flag when
parsing instruction list.
The per operand optional flag hasn't been used for quite some time.
Cleanup some remains.
include/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h: Remove S390_OPERAND_OPTIONAL.
gas/ChangeLog:
2017-05-30 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Remove code dealing with
S390_OPERAND_OPTIONAL.
Use these to replace instances of MAX_REGISTER_SIZE.
* defs.h (copy_integer_to_size): New declaration.
* findvar.c (copy_integer_to_size): New function.
(do_cint_test): New selftest function.
(copy_integer_to_size_test): Likewise.
(_initialize_findvar): Likewise.
* mips-fbsd-tdep.c (mips_fbsd_supply_reg): Use raw_supply_integer.
(mips_fbsd_collect_reg): Use raw_collect_integer.
* mips-linux-tdep.c (supply_32bit_reg): Use raw_supply_integer.
(mips64_fill_gregset): Use raw_collect_integer
(mips64_fill_fpregset): Use raw_supply_integer.
* regcache.c (regcache::raw_supply_integer): New function.
(regcache::raw_collect_integer): Likewise.
* regcache.h: (regcache::raw_supply_integer): New declaration.
(regcache::raw_collect_integer): Likewise.
This patch adds one unit test for gdbarch methods register_to_value and
value_to_register. The test pass different combinations of {regnu, type}
to gdbarch_register_to_value and gdbarch_value_to_register. In order
to do the test, add a new function create_new_frame to create a fake
frame. It can be improved after we converted frame_info to class.
In order to isolate regcache (from target_ops operations on writing
registers, like target_store_registers), the sub-class of regcache in the
test override raw_write. Also, in order to get the right regcache from
get_thread_arch_aspace_regcache, the sub-class of regcache inserts itself
to current_regcache.
Suppose I incorrectly modified the size of buffer as below,
@@ -1228,7 +1228,7 @@ ia64_register_to_value (struct frame_info *frame, int regnum,
int *optimizedp, int *unavailablep)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
- gdb_byte in[MAX_REGISTER_SIZE];
+ gdb_byte in[1];
/* Convert to TYPE. */
if (!get_frame_register_bytes (frame, regnum, 0,
build GDB with "-fsanitize=address" and run unittest.exp, asan can detect
such error
==2302==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fff98193870 at pc 0xbd55ea bp 0x7fff981935a0 sp 0x7fff98193598
WRITE of size 16 at 0x7fff98193870 thread T0
#0 0xbd55e9 in frame_register_unwind(frame_info*, int, int*, int*, lval_type*, unsigned long*, int*, unsigned char*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1119
#1 0xbd58c8 in frame_register(frame_info*, int, int*, int*, lval_type*, unsigned long*, int*, unsigned char*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1147
#2 0xbd6e25 in get_frame_register_bytes(frame_info*, int, unsigned long, int, unsigned char*, int*, int*) /home/yao/SourceCode/gnu/gdb/git/gdb/frame.c:1427
#3 0x70080a in ia64_register_to_value /home/yao/SourceCode/gnu/gdb/git/gdb/ia64-tdep.c:1236
#4 0xbf570e in gdbarch_register_to_value(gdbarch*, frame_info*, int, type*, unsigned char*, int*, int*) /home/yao/SourceCode/gnu/gdb/git/gdb/gdbarch.c:2619
#5 0xc05975 in register_to_value_test /home/yao/SourceCode/gnu/gdb/git/gdb/gdbarch-selftests.c:131
Or, even if GDB is not built with asan, GDB just crashes.
*** stack smashing detected ***: ./gdb terminated
Aborted (core dumped)
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* Makefile.in (SFILES): Add gdbarch-selftests.c.
(COMMON_OBS): Add gdbarch-selftests.o.
* frame.c [GDB_SELF_TESTS] (create_new_frame): New function.
* frame.h [GDB_SELF_TESTS] (create_new_frame): Declare.
* gdbarch-selftests.c: New file.
* regcache.h (regcache) <~regcache>: Mark it virtual if
GDB_SELF_TEST.
<raw_write>: Likewise.
This patches moves global variable current_regcache to a class regcache
static variable (protected) so that the unit test I add in the following
patch can access it (by means of extending class regcache in unit test).
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* regcache.c (current_regcache): Change it to
regcache::current_regcache.
(regcache_observer_target_changed): Update.
(regcache_thread_ptid_changed): Make it a regcache static
method.
(regcache_thread_ptid_changed): Update.
(class regcache_access): New.
(current_regcache_test): Update.
(_initialize_regcache): Update.
* regcache.h: Include forward_list.
(regcache): Declare regcache_thread_ptid_changed and declare
registers_changed_ptid as friend.
We should use register_size to get register contents instead of
TYPE_LENGTH.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* i387-tdep.c (i387_register_to_value): Use register_size
instead of TYPE_LENGTH.
* m68k-tdep.c (m68k_register_to_value): Likewise.
This patch restricts alpha_convert_register_p from
"TYPE_LENGTH (type) != 8" to "TYPE_LENGTH (type) == 4", because,
- we have check "TYPE_LENGTH (valtype) == 4" in alpha_register_to_value
and alpha_value_to_register,
- alpha lds and sts instruction access 4 bytes,
- comments "It might need to convert the [float] register into the
corresponding [integer] type (see Alpha)" and integer is 4-byte on
alpha,
I think it is the right restrict condition to "TYPE_LENGTH (valtype) == 4".
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* alpha-tdep.c (alpha_convert_register_p): Return true if type
length is 4.
(alpha_register_to_value): Remove type length check.
(alpha_value_to_register): Likewise.
We need to convert register if the type is float. Suppose we get a value
from float point register, but its type is integer, we don't have to convert.
This case may not exist in real code, but exist in my unit test case.
warning: Cannot convert floating-point register value to non-floating-point type.
Self test failed: arch m68k: self-test failed at gdb/git/gdb/findvar.c:1072
ok = gdbarch_register_to_value (gdbarch, frame, regnum, type,
buf.data (), &optim, &unavail);
1072: SELF_CHECK (ok);
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* m68k-tdep.c (m68k_convert_register_p): Check type's code is
TYPE_CODE_FLT or not.
GDB has some global variables, like sentinel_frame,
current_thread_arch, and etc, we need to reset them after each unit
tests.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* selftest-arch.c (tests_with_arch): Call registers_changed
and reinit_frame_cache.
* selftest.c (run_self_tests): Likewise.
Nowadays, rs6000 disassembler is selected in different ways in
opcodes and gdb,
opcodes:
case bfd_arch_rs6000:
if (mach == bfd_mach_ppc_620)
disassemble = print_insn_big_powerpc;
else
disassemble = print_insn_rs6000;
break;
gdb:
if (arch == bfd_arch_rs6000)
set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
else
set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
I am not sure which one is the right one. However, such selection
should be done in one place instead of two.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* rs6000-tdep.c (gdb_print_insn_powerpc): Remove.
(rs6000_gdbarch_init): Don't call set_gdbarch_print_insn.
This patch changes rl78 to let disassble.c:disassembler select
disassembler. rl78_get_disassembler doesn't handle the case
that abfd is NULL, so this patch also fix it.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* rl78-tdep.c (rl78_gdbarch_init): Don't call
set_gdbarch_print_insn.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* rl78-dis.c (rl78_get_disassembler): If parameter abfd
is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
opcodes/disassble.c:disassembler select h8300 disassembler like this,
if (mach == bfd_mach_h8300h || mach == bfd_mach_h8300hn)
disassemble = print_insn_h8300h;
else if (mach == bfd_mach_h8300s
|| mach == bfd_mach_h8300sn
|| mach == bfd_mach_h8300sx
|| mach == bfd_mach_h8300sxn)
disassemble = print_insn_h8300s;
else
disassemble = print_insn_h8300;
which is the same as what gdb/h8300-tdpe.c does,
switch (info.bfd_arch_info->mach)
{
case bfd_mach_h8300:
...
set_gdbarch_print_insn (gdbarch, print_insn_h8300);
case bfd_mach_h8300h:
case bfd_mach_h8300hn:
...
set_gdbarch_print_insn (gdbarch, print_insn_h8300h);
case bfd_mach_h8300s:
case bfd_mach_h8300sn:
...
set_gdbarch_print_insn (gdbarch, print_insn_h8300s);
so we can leave disassble.c:disassembler doing the selection.
gdb:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* h8300-tdep.c (h8300_gdbarch_init): Don't call
set_gdbarch_print_insn.
Nowadays, opcodes/disassemble.c:disassembler selects the proper
disassembler according to ABFD only. However, it actually
selects disassemblers according to arch, mach, endianess, and
abfd. This patch adds them to the parameters of disassembler,
so that its caller can still select disassemblers in case that
abfd is NULL (a typical case in GDB).
There isn't any functionality change.
binutils:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* objdump.c (disassemble_data): Caller update.
include:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* dis-asm.h (disassembler): Update declaration.
opcodes:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* disassemble.c (disassembler): Add arguments a, big and mach.
Use them.
sim/common:
2017-05-24 Yao Qi <yao.qi@linaro.org>
* sim-trace.c (trace_disasm): Caller update.
Compare against the "raw" PC register number instead of the cooked
register number when determining if a register was handled by
PT_GETREGS. Previously the register fetch/store operations only tried
PT_GETREGS to fetch any individual register. The result was that
fetching or storing an individual register not covered by PT_GETREGS
(such as floating point registers) did not work.
While here, remove an early exit to simplify the code flow from the
PT_GETREGS / PT_SETREGS case, and add a getfpregs_supplies similar to
getregs_supplies to describe the registers supplied by PT_GETFPREGS
and PT_SETFPREGS.
gdb/ChangeLog:
* mips-fbsd-nat.c (getregs_supplies): Fix upper bound comparison.
(getpfpregs_supplies): New function.
(mips_fbsd_fetch_inferior_registers): Remove early exit and use
getfpregs_supplies.
(mips_fbsd_store_inferior_registers): Likewise.
It is required to parse instructions like ldb.x.a.di.
include/
2017-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (MAX_INSN_FLGS): Update to 4.
