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682 Commits

Author SHA1 Message Date
Jiong Wang
b8ec4e871e [ARM] Add FP16 feature extension for ARMv8.2 architecture 
include/
  * opcode/arm.h (ARM_EXT2_FP16_INSN): New.

gas/
  * config/tc-arm.c (arm_ext_fp16): New.
  (arm_extensions): New entry for "fp16".
 2016-02-19 14:27:23 +00:00
Claudiu Zissulescu
4670103e86 Add support for ARC instruction relaxation in the assembler. 
gas/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot <jvanoirs@synopsys.com>

        * config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
        (MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
        Define.
        (arc_flags, arc_relax_type): New structure.
        * config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
	(RELAX_TABLE_ENTRY_MAX): New define.
        (relaxation_state, md_relax_table, arc_relaxable_insns)
	(arc_num_relaxable_ins): New variable.
	(rlx_operand_type, arc_rlx_types): New enums.
	(arc_relaxable_ins): New structure.
        (OPTION_RELAX): New option.
        (arc_insn): New relax member.
        (arc_flags): Remove.
        (relax_insn_p): New function.
        (apply_fixups): Likewise.
        (relaxable_operand): Likewise.
        (may_relax_expr): Likewise.
        (relaxable_flag): Likewise.
        (arc_pcrel_adjust): Likewise.
        (md_estimate_size_before_relax): Implement.
        (md_convert_frag): Likewise.
        (md_parse_option): Handle new mrelax option.
        (md_show_usage): Likewise.
        (assemble_insn): Set relax member.
        (emit_insn0): New function.
        (emit_insn1): Likewise.
        (emit_insn): Handle relaxation case.
	* NEWS: Mention the new relaxation option.
	* doc/c-arc.texi (ARC Options): Document new mrelax option.

gas/testsuite
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>

        * gas/arc/relax-avoid1.d: New file.
        * gas/arc/relax-avoid1.s: Likewise.
        * gas/arc/relax-avoid2.d: Likewise.
        * gas/arc/relax-avoid2.s: Likewise.
        * gas/arc/relax-avoid3.d: Likewise.
        * gas/arc/relax-avoid3.s: Likewise.
	* gas/arc/relax-b.d: Likewise.
        * gas/arc/relax-b.s: Likewise.

include/opcode/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot  <jvanoirs@synopsys.com>

        * arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
        Declare.

opcodes/
2016-01-26  Claudiu Zissulescu  <claziss@synopsys.com>
	    Janek van Oirschot  <jvanoirs@synopsys.com>

        * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
        variable.
 2016-02-10 12:09:01 +00:00
Nick Clifton
609332f15c Fix compile time warnings building the binutils with a gcc6 compiler. 
include	* opcode/metag.h (metag_scondtab): Mark as possibly unused.
	* opcode/nds32.h (nds32_r45map): Likewise.
	(nds32_r54map): Likewise.
	* opcode/visium.h (gen_reg_table): Likewise.
	(fp_reg_table, cc_table, opcode_table): Likewise.

bfd	* oasys.c (oasys_archive_p): Fix indentation.
	* elf32-nds32.c (nds32_elf_relax_section): Use an unsigned
	constant for left shifting.
 2016-02-09 16:34:24 +00:00
Nick Clifton
c1d9289fef Fix the encoding of the MSP430's RRUX instruction. 
PR target/19561
opcdoe	* msp430-dis.c (print_insn_msp430): Add a special case for
	decoding an RRC instruction with the ZC bit set in the extension
	word.

include	* opcode/msp430.h (IGNORE_CARRY_BIT): New define.
	(RRUX): Synthesise using case 2 rather than 7.

gas	* config/tc-msp430.c (msp430_operands): Remove case 7.  Use case 2
	to handle encoding of RRUX instruction.
	* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
	shift instructions.
	* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
 2016-02-04 09:55:10 +00:00
Miranda Cupertino
34e967a5f3 Add PIC and TLS support to the ARC target. 
bfd/ChangeLog:
	* arc-plt.def: New file.
	* arc-plt.h: Likewise.
	* elf32-arc.c (elf_arc_abs_plt0_entry, elf_arc_abs_pltn_entry,
		       elf_arcV2_abs_plt0_entry, elf_arcV2_abs_pltn_entry,
		       elf_arc_pic_plt0_entry, elf_arc_pic_pltn_entry,
		       elf_arcV2_pic_plt0_entry, elf_arcV2_pic_pltn_entry): Remove.
	(name_for_global_symbol): Added.
	(ADD_RELA): Helper to create dynamic relocs.
	(new_got_entry_to_list): Create a new got entry in linked list.
	(symbol_has_entry_of_type): Search for specific type of entry in
	list.
	(is_reloc_for_GOT): return FALSE for any TLS related relocs.
	(is_reloc_for_TLS, arc_elf_set_private_flags)
	(arc_elf_print_private_bfd_data, arc_elf_copy_private_bfd_data)
	(arc_elf_merge_private_bfd_data): New functions.
	(debug_arc_reloc): Cleaned debug info printing.
	(PDATA reloc): Changed not to perform address alignment.
	(reverse_me): Added. Fix for ARC_32 relocs.
	(arc_do_relocation): Return bfd_reloc_of when no relocation should
	occur.
	(arc_get_local_got_ents): Renamed from arc_get_local_got_offsets.
	Changed function to access an array of list of GOT entries instead
	of just an array of offsets.
	(elf_arc_relocate_section): Added support for PIC and TLS related relocations.
	(elf_arc_check_relocs): Likewise.
	(elf_arc_adjust_dynamic_symbol, elf_arc_finish_dynamic_symbol,
	(elf_arc_finish_dynamic_sections): Likewise
	(arc_create_dynamic_sections): Modified conditions to create
	dynamic sections.
	(ADD_SYMBOL_REF_SEC_AND_RELOC): New macro.
	(plt_do_relocs_for_symbol, relocate_plt_for_symbol)
	(relocate_plt_for_entry): Changed to support new way to define PLT
	related code.
	(add_symbol_to_plt): Likewise.
	(arc_elf_link_hash_table_create): New function.

include/ChangeLog:
	* elf/arc-reloc.def (ARC_32, ARC_GOTPC, ARC_TLS_GD_GOT)
	(ARC_TLS_IE_GOT, ARC_TLS_DTPOFF, ARC_TLS_DTPOFF_S9, ARC_TLS_LE_S9)
	(ARC_TLS_LE_32): Fixed formula.
	(ARC_TLS_GD_LD): Use new special function.
	* opcode/arc-func.h: Changed all the replacement
	functions to clear the patching bits before doing an or it with the value
	argument.
 2016-01-19 15:25:58 +00:00
Maciej W. Rozycki
b31e480331 MIPS/include: opcode/mips.h: Add a summary of MIPS16 operand codes 
include/
	* opcode/mips.h: Add a summary of MIPS16 operand codes.
 2016-01-06 18:37:58 +00:00
Alan Modra
6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
Alan Modra
4120fa118f binutils ChangeLog rotation 2016-01-01 22:59:17 +10:30
Alan Modra
331e61312e Fix assorted ChangeLog errors 2015-12-30 11:44:35 +10:30
Thomas Preud'homme
ff8646eef8 Add assembler support for ARMv8-M Baseline 
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
    (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards
    to merging with ARMv8-M Baseline.

binutils/
    * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch
    value.

gas/
    * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions
    shared between ARMv6T2 and ARMv8-M.
    (move_or_literal_pool): Check mov.w/mvn and movw availability against
    arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking
    arm_arch_t2.
    (do_t_branch): Error out for wide conditional branch instructions if
    targetting ARMv8-M Baseline.
    (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions
    in ARMv8-M Baseline.
    (wide_insn_ok): New function.
    (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and
    adapt error message for unsupported wide instruction to ARMv8-M
    Baseline.
    (insns): Reorganize instructions shared by ARMv8-M Baseline and
    ARMv6t2 architecture.
    (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and
    marvell-whitney cores.
    (arm_archs): Define armv8-m.base architecture.
    (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version.
    (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for
    ARMv8-M Mainline.  Set Tag_DIV_use for ARMv8-M Baseline as well.

gas/testsuite/
    * gas/arm/archv8m-base.d: New file.
    * gas/arm/attr-march-armv8m.base.d: Likewise.
    * gas/arm/armv8m.base-idiv.d: Likewise.
    * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline.

include/elf/
    * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare.

include/opcode/
    * arm.h (ARM_EXT2_V6T2_V8M): New extension bit.
    (ARM_AEXT2_V8A): New architecture extension bitfield.
    (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
    (ARM_AEXT_V8M_BASE): New architecture extension bitfield.
    (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M.
    (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension
    bitfield.
    (ARM_ARCH_V6KT2): Likewise.
    (ARM_ARCH_V6ZT2): Likewise.
    (ARM_ARCH_V6KZT2): Likewise.
    (ARM_ARCH_V7): Likewise.
    (ARM_ARCH_V7A): Likewise.
    (ARM_ARCH_V7VE): Likewise.
    (ARM_ARCH_V7R): Likewise.
    (ARM_ARCH_V7M): Likewise.
    (ARM_ARCH_V7EM): Likewise.
    (ARM_ARCH_V8A): Likewise.
    (ARM_ARCH_V8M_BASE): New architecture bitfield.
    (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M.
    (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension
    bitfield and reindent.
    (ARM_ARCH_V7A_MP_SEC): Likewise.
    (ARM_ARCH_V7R_IDIV): Likewise.
    (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
    (ARM_ARCH_V8A_SIMD): Likewise.
    (ARM_ARCH_V8A_CRYPTOV1): Likewise.

opcodes/
    * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex,
    ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by
    ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
 2015-12-24 17:27:21 +08:00
Thomas Preud'homme
4ed7ed8db2 Add assembler support for ARMv8-M Mainline 
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
    (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
    for new TAG_CPU_ARCH_V4T_PLUS_V6_M value.  Deal with NULL values in
    comb array.

binutils/
    * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
    value.
    (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
    value.

gas/
    * config/tc-arm.c (arm_ext_m): Include ARMv8-M.
    (arm_ext_v8m): New feature for ARMv8-M.
    (arm_ext_atomics): New feature for ARMv8 atomics.
    (do_tt): New encoding function for TT* instructions.
    (insns): Add new entries for ARMv8-M specific instructions and
    reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
    (arm_archs): Define armv8-m.main architecture.
    (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
    clarify the ordering rule.
    (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
    Tag_CPU_arch values for ARMv7e-M detection.  Add logic to keep setting
    Tag_CPU_arch to ARMv8-A for -march=all.  Also set Tag_CPU_arch_profile
    to 'A' if extension bit for atomic instructions is set, unless it is
    ARMv8-M.  Set Tag_THUMB_ISA_use to 3 for ARMv8-M.  Set Tag_DIV_use to 0
    for ARMv8-M Mainline.

gas/testsuite/
    * gas/arm/archv8m.s: New file.
    * gas/arm/archv8m-main.d: Likewise.
    * gas/arm/attr-march-armv8m.main.d: Likewise.
    * gas/arm/any-armv8m.s: Likewise.
    * gas/arm/any-armv8m.d: Likewise.

include/elf/
    * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
    (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
    (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.

include/opcode/
    * arm.h (ARM_EXT2_ATOMICS): New extension bit.
    (ARM_EXT2_V8M): Likewise.
    (ARM_EXT_V8): Adjust comment with regards to atomics and remove
    mention of legacy use for that bit.
    (ARM_AEXT2_V8_1A): New architecture extension bitfield.
    (ARM_AEXT2_V8_2A): Likewise.
    (ARM_AEXT_V8M_MAIN): Likewise.
    (ARM_AEXT2_V8M): Likewise.
    (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
    (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
    (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
    (ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
    (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
    and reindent.
    (ARM_ARCH_V8A_SIMD): Likewise.
    (ARM_ARCH_V8A_CRYPTOV1): Likewise.
    (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
    feature bits.
    (ARM_ARCH_V8_1A_SIMD): Likewise.
    (ARM_ARCH_V8_1A_CRYPTOV1): Likewise.

opcodes/
    * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
    stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
    ARM_EXT_V8.
    (thumb32_opcodes): Add entries for wide ARMv8-M instructions.
 2015-12-24 17:26:54 +08:00
Thomas Preud'homme
fc289b0a83 Consolidate Thumb-1/Thumb-2 ISA detection 
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
    * config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw
    availability against arm_ext_v6t2 instead of checking arm_arch_t2,
    fixing comments along the way.
    (handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to
    generate IT instruction.
    (t1_isa_t32_only_insn): New function.
    (md_assemble): Use above new function to check for invalid wide
    instruction for CPU Thumb ISA and to determine what Thumb extension
    bit is necessary for that instruction.
    (md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if
    branch is out of range.

include/opcode/
    * arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and
    remove extension bit not including any Thumb-2 instruction.
 2015-12-24 17:03:50 +08:00
Ramana Radhakrishnan
10c9892b66 [Patch ARM] Fix build attributes for armv8-a in case of assembler files that contain no directives. 
There is currently a problem in the way in which we produce
build attributes for simple assembler files that have armv8-a
instructions.

In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2
and set the architecture profile to be 'A' rather than not
setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use
to be Thumb-1.

This is a pre-requisite for any v8-m patches that have been posted.
arm-none-eabi gas testsuite run. no regressions.

2015-12-17  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust
	TAG_ARCH_profile for armv8-a.
	* gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test.
	* gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test.
	* gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test.
	* gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
 2015-12-17 11:34:39 +00:00
Matthew Wahab
29b1539538 [ARM] Enable CRC by default for ARMv8.1 and later. 
ARMv8.1 includes CRC as a required extension but the +crc feature isn't
enabled by -march=armv8.1-a as it should be. This patch fixes that.

opcode/include
2015-12-15  Matthew Wahab  <matthew.wahab@arm.com>

	* arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
	feature macro.
	(ARM_ARCH_V8_2A): Likewise.

Change-Id: Id1fe0e6fa51dede19d61e1fd08e68628ea1b1e9e
 2015-12-15 16:38:58 +00:00
Yoshinori Sato
a117b0a51c Add support for RX V2 Instruction Set 
binutils
	* readelf.c(get_machine_flags): Add v2 flag.

gas
	* config/rx-defs.h(rx_cpu_type): Add RXV2 type.
	* config/tc-rx.c(cpu_type_list): New type lookup table.
	(md_parse_option): Use lookup table for choose cpu.
	(md_show_usage): Add rxv2 for mcpu option.
	* doc/c-rx.texi: Likewise.
	* config/rx-parse.y: Add v2 instructions and ACC register.
	(rx_check_v2): check v2 type.

include/elf
	* rx.h(E_FLAG_RX_V2): New RXv2 type.

include/opcode
	* rx.h: Add new instructions.

opcoes
	* rx-deocde.opc(rx_decode_opcode): Add new instructions pattern.
	* rx-dis.c(register_name): Add new register.

gas/testsuite
	* gas/rx/emaca.d: New.
	* gas/rx/emaca.sm: New.
	* gas/rx/emsba.d: New.
	* gas/rx/emsba.sm: New.
	* gas/rx/emula.d: New.
	* gas/rx/emula.sm: New.
	* gas/rx/fadd.d: Add new pattern.
	* gas/rx/fadd.sm: Add new pattern.
	* gas/rx/fmul.d: Add new pattern.
	* gas/rx/fmul.sm: Add new pattern.
	* gas/rx/fsqrt.d: New.
	* gas/rx/fsqrt.sm: New.
	* gas/rx/fsub.d: Add new pattern.
 	* gas/rx/fsub.sm: Add new pattern.
	* gas/rx/ftou.d: New.
	* gas/rx/ftou.sm: New.
	* gas/rx/maclh.d: New.
	* gas/rx/maclh.sm: New.
	* gas/rx/maclo.d: Add new pattern.
	* gas/rx/maclo.sm: Add new pattern.
	* gas/rx/macros.inc: Add new register.
	* gas/rx/movco.d: New.
	* gas/rx/movco.sm: New.
	* gas/rx/movli.d: New.
	* gas/rx/movli.sm: New.
	* gas/rx/msbhi.d: New.
	* gas/rx/msbhi.sm: New.
	* gas/rx/msblh.d: New.
	* gas/rx/msblh.sm: New.
	* gas/rx/msblo.d: New.
	* gas/rx/msblo.sm: New.
	* gas/rx/mullh.d: New.
	* gas/rx/mullh.sm: New.
	* gas/rx/mvfacgu.d: New.
	* gas/rx/mvfacgu.sm: New.
	* gas/rx/mvfachi.d: Add new pattern.
	* gas/rx/mvfachi.sm: Add new pattern.
	* gas/rx/mvfaclo.d: Add new pattern.
	* gas/rx/mvfaclo.sm: Add new pattern.
	* gas/rx/mvfacmi.d: Add new pattern.
	* gas/rx/mvfacmi.sm: Add new pattern.
	* gas/rx/mvfc.d: Add new pattern.
	* gas/rx/mvtacgu.d: New.
	* gas/rx/mvtacgu.sm: New.
	* gas/rx/mvtc.d: Add new pattern.
	* gas/rx/popc.d: Add new pattern.
	* gas/rx/pushc.d: Add new pattern.
	* gas/rx/racl.d: New.
	* gas/rx/racl.sm: New.
	* gas/rx/racw.d: Add new pattern.
	* gas/rx/racw.sm: Add new pattern.
	* gas/rx/rdacl.d: New.
	* gas/rx/rdacl.sm: New.
	* gas/rx/rdacw.d: New.
	* gas/rx/rdacw.sm: New.
	* gas/rx/rx.exp: Add option.
	* gas/rx/stnz.d: Add new pattern.
	* gas/rx/stnz.sm: Add new pattern.
	* gas/rx/stz.d: Add new pattern.
	* gas/rx/stz.sm: Add new pattern.
	* gas/rx/utof.d: New.
	* gas/rx/utof.sm: New.
 2015-12-15 09:26:56 +00:00
Matthew Wahab
3067d3b96c [AArch64][PATCH 11/14] Add support for the 2H vector type. 
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type, 2H. This patch adds
support for this vector type to binutils.

The patch adds a new operand qualifier to the enum
aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation
used by aarch64-dis.c:get_vreg_qualifier_from_value, called when
decoding an instruction. Since the new vector type is only used in FP16
scalar pairwise instructions which do not require the function, this
patch adjusts the function to ignore the new qualifier.

gas/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
	take into account new vector type 2H.
	(vectype_to_qualifier): Likewise.

include/opcode/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (enum aarch64_opnd_qualifier): Add
	AARCH64_OPND_QLF_V_2H.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.coM>

	* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
	and adjust calculation to ignore qualifier for type 2H.
	* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".

Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
 2015-12-14 17:27:52 +00:00
Matthew Wahab
1e6f4800fc [AArch64][Patch 5/5] Add instruction PSB CSYNC 
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds the instruction to
binutils as a HINT alias that takes an operand.

A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the
operand to PSB. A parser for the operand type is added to the assembler
and a printer to the disassembler. The operand name "csync" is added to
the list of HINT options with HINT number #17. Encoding and decoding of
the operand is handled by the ins_hint/ext_hint functions added in the
preceding patches.

gas/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
	(parse_barrier_psb): New.
	(parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
	(md_begin): Set up aarch64_hint_opt_hsh.

gas/testsuite/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/system-2.d: Enable the statistical profiling
	extension.  Update the expected output.
	* gas/aarch64/system-2.s: Add tests for PSB CSYNC.
	* gas/aarch64/system.d: Update the expected output.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (aarch64_hint_options): Add "csync".
	(aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
	* aarch64-tbl.h (aarch64_feature_stat_profile): New.
	(STAT_PROFILE): New.
	(aarch64_opcode_table): Add "psb".
	(AARCH64_OPERANDS): Add "BARRIER_PSB".

Change-Id: I5ffb672d26a8b15b48785478d359350a9b70ca09
 2015-12-11 10:22:40 +00:00
Matthew Wahab
9ed608f98b [AArch64][Patch 4/5] Support HINT aliases taking operands. 
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds support for aliases
of HINT which take an operand, adding a table to store operand names and
their matching hint number as well as encoding and decoding functions
for such operands. Parsing and printing the operands are deferred to any
support added for aliases with such operands.

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_hint_options): Declare.
	(aarch64_opnd_info): Add field hint_option.

opcodes/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm.c (aarch64_ins_hint): New.
	* aarch64-asm.h (aarch64_ins_hint): Declare.
	* aarch64-dis.c (aarch64_ext_hint): New.
	* aarch64-dis.h (aarch64_ext_hint): Declare.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (aarch64_hint_options): New.
	* aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.

Change-Id: I2205038fc1c47d3025d1f0bc2fbf405b5575b287
 2015-12-11 10:12:34 +00:00
Matthew Wahab
73af8ed6b1 [AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension. 
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers and a new instruction. This patch set
adds support for the extension to binutils, enabled when
-march=armv8.2-a+profile is given.

The patches in this series:
- Add the new command line option and feature flags.
- Add the new system registers.
- Adjust the maximum number of aliases permitted for an instruction.
- Add support for HINT aliases which take operands.
- Add the new instruction, an alias of the HINT instruction.

This patch adds the option "profile" to the permitted architecture
extensions, disabling it by default.

gas/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "profile".
	* doc/c-aarch64.texi (AArch64 Extensions): Add "profile".

include/opcode/
2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_PROFILE): New.

Change-Id: If9bb4a9b69a264180f96f8ffaf10b15ced273699
 2015-12-11 09:30:26 +00:00
Matthew Wahab
d6bf7ce6c2 [AArch64][PATCH 2/2] Support ARMv8.2 DC CVAP instruction. 
ARMv8.2 adds the new system instruction DC CVAP. This patch adds support
for the instruction to binutils, enabled when -march=armv8.2-a is
selected.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (parse_sys_ins_reg): Add check of
	architectural support for system register.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/sysreg-2.d: Add tests for dc instruction.
	* gas/aarch64/sysreg-2.s: Add uses of dc instruction.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
	(aarch64_sys_ins_reg_supported_p): New.

Change-Id: I3158b97d9bbee9644c2d0e2986db807412ef1053
 2015-12-10 16:40:45 +00:00
Matthew Wahab
ea2deeec92 [AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction. 
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds
support for this instruction to binutils, enabled when -march=armv8.2-a
is selected.

The AArch64 binutils record of some system registers uses a boolean
value to hold the single flag currently supported for them. To allow
these registers to be limited to specific architectures, the first patch
in this series replaces the boolean flag with a bitset and feature test.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
	(aarch64_sys_ins_reg_has_xt): Declare.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
	with aarch64_sys_ins_reg_has_xt.
	(aarch64_ext_sysins_op): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
	(F_HASXT): New.
	(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
	(aarch64_sys_regs_dc): Likewise.
	(aarch64_sys_regs_at): Likewise.
	(aarch64_sys_regs_tlbi): Likewise.
	(aarch64_sys_ins_reg_has_xt): New.

Change-Id: I363637a6c3f54d7ffff953b3a0734e8139cae819
 2015-12-10 16:40:44 +00:00
Matthew Wahab
c8a6db6fa0 [AArch64][PATCH 1/2] Add support for RAS instruction ESB. 
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.

This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.

Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/system-2.d: New.
	* gas/aarch64/system-2.s: New.
	* gas/aarch64/system.d: Adjust expected output for HINT 16.

include/opcode/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_RAS): New.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-tbl.h (aarch64_feature_ras): New.
	(RAS): New.
	(aarch64_opcode_table): Add "esb".

Change-Id: Id4713917da15cca3b977284f43febd1c9b3d9faf
 2015-12-10 14:10:15 +00:00
Matthew Wahab
af117b3cf1 [AArch64] Fix ARMv8.1 and ARMv8.2 feature settings. 
ARMv8.1 includes CRC as a required extension but this isn't reflected in
the features enabled by -march=armv8.1-a. The FP16 feature modifier also
clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2
is missing ARMv8.1 features.

This patch enables +crc for -march values of armv8.1-a and later. It
also fixes the values for AARCH64_FEATURE_F16 and makes
AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2.

gas/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.

include/opcode
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_F16): Fix clash with
	AARCH64_FEATURE_V8_1.
	(AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
	AARCH64_FEATURE_V8_1.

Change-Id: I8af5369f6df2430b28f6cec92870d2a4d14a7431
 2015-12-10 14:10:06 +00:00
Claudiu Zissulescu
24b368f853 Fix failures in the GAS testsuite for the ARC architecture. 
gas	* config/tc-arc.c (arc_option): Sets all internal gas options when
	parsing .cpu directive.
	(declare_register_set): Declare all 64 registers.
	(md_section_align): Refactor.
	(md_pcrel_from_section): Remove assert.
	(pseudo_operand_match): Fix pseudo operand match.
	(find_reloc): Use flags filed, extend matching.
	* config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT
	relocation.

testsuite	* gas/arc/bic.d: Update test.
	* gas/arc/add_s-err.s: New file.
	* gas/arc/cpu-warn1.s: Likewise.
	* gas/arc/pcl-relocs.d: Likewise.
	* gas/arc/pcl-relocs.s: Likewise.
	* gas/arc/pcrel-relocs.d: Likewise.
	* gas/arc/pcrel-relocs.s: Likewise.
	* gas/arc/pic-relocs.d: Likewise.
	* gas/arc/pic-relocs.s: Likewise.
	* gas/arc/plt-relocs.d: Likewise.
	* gas/arc/plt-relocs.s: Likewise.
	* gas/arc/pseudos.d: Likewise.
	* gas/arc/pseudos.s: Likewise.
	* gas/arc/sda-relocs.d: Likewise.
	* gas/arc/sda-relocs.s: Likewise.
	* gas/arc/sda-relocs2.d: Likewise.
	* gas/arc/sda-relocs2.s: Likewise.
	* gas/arc/tls-relocs.d: Likewise.
	* gas/arc/tls-relocs.s: Likewise.

opcode	* arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].

opcodes	* arc-dis.c (special_flag_p): Match full mnemonic.
	* arc-opc.c (print_insn_arc): Check section size to read
	appropriate number of bytes. Fix printing.
	* arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
	arguments.
 2015-12-04 10:49:57 +00:00
Matthew Wahab
d685192a58 [AArch64] Add ARMv8.2 instructions BFC and REV64. 
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as
an alias for REV. This patch set adds support for these to binutils,
enabled when the -march=armv8.2-a is given. It depends on the support
for an instruction being its preferred form which was added in an
earlier patch.

This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred
form for BFM when the source is a zero register and the conditions for
using the BFI form are met (in other words, BFC is the preferred form
for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register).

gas/testsuite/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/alias-2.d: New.
	* gas/aarch64/alias-2.s: New.

include/opcode/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (aarch64_op): Add OP_BFC.

opcodes/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-asm.c (convert_bfc_to_bfm): New.
	(convert_to_real): Add case for OP_BFC.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-dis.c: (convert_bfm_to_bfc): New.
	(convert_to_alias): Add case for OP_BFC.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
	to allow width operand in three-operand instructions.
	* aarch64-tbl.h (QL_BF1): New.
	(aarch64_feature_v8_2): New.
	(ARMV8_2): New.
	(aarch64_opcode_table): Add "bfc".

Change-Id: I6efe318b2538ba11f0caece7c6d70957441c872b
 2015-11-27 15:28:42 +00:00
Matthew Wahab
870181955b [AArch64] Add feature flags and command line for ARMv8.2 FP16 support. 
ARMv8.2 adds optional support for 16-bit operations to the FP and
Adv.SIMD instructions. This patch adds a feature macro for this support
with a new command line option "+fp16" to enable/disable it.

Although the command line option is added as an architecture extension,
it only affects instructions available with when +fp or +simd is
enabled. If +fp16 is specified then it will also enable +fp.

There are currently no FP16 instructions implemented in binutils, this
patch is to enable subsequent work on supporting the extension.

gas/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "fp16".
	* doc/c-aarch64.texi (Architecture Extensions): Add "fp16".

include/opcode/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_F16): New.
	(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
	features.

Change-Id: Id2021e0513946e16d0935c2a5b9605574cdff95a
 2015-11-27 13:19:50 +00:00
Matthew Wahab
250aafa477 [AArch64] Add support for ARMv8.1 Virtulization Host Extensions. 
The ARMv8.1 architecture includes the Virtualization Host Extensions
which add a number of system registers. This patch adds support for
these system registers, making them available when -march=armv8.1-a is
selected.

include/opcode/
2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_V8_1): New.
	(AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.

opcodes/
2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
	sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
	tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
	amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
	cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
	cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
	cnthv_ctl_el2, cnthv_cval_el2.
	(aarch64_sys_reg_supported_p): Update for the new system
	registers.

gas/testsuite/
2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/virthostext-directive.d: New.
	* gas/aarch64/virthostext.d: New.
	* gas/aarch64/virthostext.s: New.

Change-Id: Iecb370591b1b6e9e00d81c8ccd9ae3b0f71794a2
 2015-11-20 16:09:34 +00:00
Matthew Wahab
56a1b672f4 [ARM] Add ARMv8.2 architecture feature and command line option. 
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils ARM target
with GAS command line option -march=armv8.2-a.

gas/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-arm.c (arm_archs): Add "armv8.2-a".
	* doc/c-arm.texi (-march): Add "armv8.2-a".

include/opcode/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* arm.h (ARM_EXT2_V8_2A): New.
	(ARM_ARCH_V8_2A): New.

Change-Id: I9e0f50e3c6cea24e6b87b8b862fd4e1cdcc1052e
 2015-11-19 09:24:14 +00:00
Matthew Wahab
acb787b032 [AArch64] Add ARMv8.2 command line option and feature flag. 
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils AArch64 target
with GAS command line option -march=armv8.2-a.

gas/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (aarch64_archs): Add "armv8.2-a".
	* doc/c-aarch64.texi (-march): Likewise.

include/opcode/
2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (AARCH64_FEATURE_V8_2): New.
	(AARCH64_ARCH_V8_2): New.

Change-Id: I129232ab00234a07d18ce4b619607344acb3cbaf
 2015-11-19 09:12:49 +00:00
Peter Bergner
a680de9a98 Add assembler, disassembler and linker support for power9. 
include/opcode/
	* ppc.h (PPC_OPCODE_POWER9): New define.
	(PPC_OPCODE_VSX3): Likewise.

opcodes/
	* ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
	Add PPC_OPCODE_VSX3 to the vsx entry.
	(powerpc_init_dialect): Set default dialect to power9.
        * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
        insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
        extract_l1 insert_xtq6, extract_xtq6): New static functions.
        (insert_esync): Test for illegal L operand value.
	(DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
	XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
	XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
	XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
	PPCVSX3): New defines.
	(powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
	fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
	<mcrxr>: Use XBFRARB_MASK.
	<addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
	bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
	cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
	cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
	lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
	lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
	modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
	rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
	stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
	subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
	vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
	vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
	vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
	vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
	vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
	vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
	vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
	xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
	xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
	xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
	xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
	xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
	xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
	xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
	xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
	xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
	xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
	xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
	xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
	xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
	<doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
	<tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.

include/elf/
	* ppc.h (R_PPC_REL16DX_HA): New reloction.
	* ppc64.h (R_PPC64_REL16DX_HA): Likewise.

bfd/
	* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
	(ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
	(ppc_elf_addr16_ha_reloc): Likewise.
	(ppc_elf_check_relocs): Likewise.
	(ppc_elf_relocate_section): Likewise.
	(is_insn_dq_form): Handle lxv and stxv instructions.
	* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
	(ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
	(ppc64_elf_ha_reloc): Likewise.
	(ppc64_elf_check_relocs): Likewise.
	(ppc64_elf_relocate_section): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.
	* reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.

elfcpp/
	* powerpc.h (R_POWERPC_REL16DX_HA): Define.

gas/
	* doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
	* doc/c-ppc.texi (PowerPC-Opts):  Likewise.
	* config/tc-ppc.c (md_show_usage): Likewise.
	(md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
	(md_apply_fix): Likewise.
	(ppc_handle_align): Handle power9's group ending nop.

gas/testsuite/
	* gas/ppc/altivec3.s: New test.
	* gas/ppc/altivec3.d: Likewise.
	* gas/ppc/vsx3.s: Likewise.
	* gas/ppc/vsx3.d: Likewise.
	* gas/ppc/power9.s: Likewise.
	* gas/ppc/power9.d: Likewise.
	* gas/ppc/ppc.exp: Run them.
	* gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests.
	* gas/ppc/power8.d: Likewise.
	* gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ...
	<lxvd2x, stxvd2x>: ...to this.
	* gas/ppc/vsx.d: Likewise.

gold/
	* gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function.
	(Powerpc_relocate_functions::addr16dx_ha): Likewise.
	(Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA.
	(Target_powerpc::Scan::global): Likewise.
	(Target_powerpc::Relocate::relocate): Likewise.

ld/testsuite/
	* ld-powerpc/addpcis.d: New test.
	* ld-powerpc/addpcis.s: New test.
	* ld-powerpc/powerpc.exp: Run it.
 2015-11-11 19:52:52 -06:00
Nick Clifton
854eb72b00 Disassemble RX NOP instructions as such. 
opcode	* rx.h (enum RX_Opcode_ID): Add more NOP opcodes.

opcodes	* rx-decode.opc (rx_decode_opcode): Decode extra NOP
	instructions.
	* rx-decode.c: Regenerate.

tests	* gas/rx/max.d: Update expecetd disassembly.
	* gas/rx/nod.d: Likewise.
	* gas/rx/nop.sm: Add tests of more NOP instructions.
 2015-11-02 14:37:33 +00:00
Nick Clifton
e292aa7a95 Fix disassembly of RX zero-offset register indirect instructions. 
opcode	* rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.

opcodes	* rx-decode.opc (rx_disp): If the displacement is zero, set the
	type to RX_Operand_Zero_Indirect.
	* rx-decode.c: Regenerate.
	* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.

gas	* config/rx-parse.y: Allow zero value for 5-bit displacements.

tests	* gas/rx/mov.sm: Add tests for zero offset indirect moves.
	* gas/rx/mov.d: Update expected output.
 2015-11-02 14:14:22 +00:00
Yao Qi
43cdf5aeb8 Pass noaliases_p to aarch64_decode_insn 
Nowadays aarch64_decode_insn is a public interface used by both
opcodes and gdb.  However, its behaviour relies on a global variable
no_aliases, which isn't a good practise.  On the other hand, In default,
no_aliases is zero, but in GDB, we do want no alias when decoding
instructions for prologue analysis (patches to be posted), so that we
can handle both instructions "add" and "mov" (an alias of "add") as
"add".  The code in GDB can be simplified.

This patch adds a new argument in aarch64_decode_insn, and pass no_aliases
to it.  In GDB side, always pass 1 to it.

include/opcode:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_decode_insn): Update declaration.

opcodes:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c	(aarch64_decode_insn): Add one argument
	noaliases_p.  Update comments.  Pass noaliases_p rather than
	no_aliases to aarch64_opcode_decode.
	(print_insn_aarch64_word): Pass no_aliases to
	aarch64_decode_insn.

gdb:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
	aarch64_decode_insn.
 2015-10-28 14:22:57 +00:00
Yao Qi
875880c661 Avoid using 'template' C++ keyword 
'template' is used in include/opcode/aarch64.h as below,

 typedef struct
 {
   const char *template;
   uint32_t value;
   int has_xt;
 } aarch64_sys_ins_reg;

and it triggers compilation errors when GDB is built in C++ mode.

In file included from git/gdb/aarch64-tdep.c:62:0:
git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template'
   const char *template;

This patch is to rename field template to name.

gas/

	* config/tc-aarch64.c (md_begin): Access field 'name' rather
	than 'template'.

include/opcode/

	* aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
	<name>: New field.

opcodes/

	* aarch64-dis.c (aarch64_ext_sysins_op): Access field
	'name' rather than 'template'.
	* aarch64-opc.c (aarch64_print_operand): Likewise.
 2015-10-07 15:22:47 +01:00
Yao Qi
d3e12b29ae Wrap include/opcode/aarch64.h in extern "C" for C++ 
This is sufficient to link an aarch64 GDB built in C++ mode.  Pedro
did something similar in Feb
https://sourceware.org/ml/binutils/2015-02/msg00176.html

include/opcode/

2015-10-07  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h [__cplusplus]: Wrap in extern "C".
 2015-10-07 15:07:14 +01:00
Nick Clifton
886a250647 New ARC implementation. 
bfd	* archures.c: Remove support for older ARC. Added support for new
	ARC cpus (ARC600, ARC601, ARC700, ARCV2).
	* bfd-in2.h: Likewise.
	* config.bfd: Likewise.
	* cpu-arc.c: Likewise.
	* elf32-arc.c: Totally changed file with a refactored
	inplementation of the ARC port.
	* libbfd.h: Added ARC specific relocation types.
	* reloc.c: Likewise.

gas     * config/tc-arc.c: Revamped file for ARC support.
        * config/tc-arc.h: Likewise.
        * doc/as.texinfo: Add new ARC options.
        * doc/c-arc.texi: Likewise.

ld	* configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
	* emulparams/arcebelf_prof.sh: New file
	* emulparams/arcebelf.sh: Likewise.
	* emulparams/arceblinux_prof.sh: Likewise.
	* emulparams/arceblinux.sh: Likewise.
	* emulparams/arcelf_prof.sh: Likewise.
	* emulparams/arcelf.sh: Likewise.
	* emulparams/arclinux_prof.sh: Likewise.
	* emulparams/arclinux.sh: Likewise.
	* emulparams/arcv2elfx.sh: Likewise.
	* emulparams/arcv2elf.sh: Likewise.
	* emultempl/arclinux.em: Likewise.
	* scripttempl/arclinux.sc: Likewise.
	* scripttempl/elfarc.sc: Likewise.
	* scripttempl/elfarcv2.sc: Likewise
	* Makefile.am: Add new ARC emulations.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new feature.

opcodes * arc-dis.c: Revamped file for ARC support
	* arc-dis.h: Likewise.
	* arc-ext.c: Likewise.
	* arc-ext.h: Likewise.
	* arc-opc.c: Likewise.
	* arc-fxi.h: New file.
	* arc-regs.h: Likewise.
	* arc-tbl.h: Likewise.

binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
	and ARCv2.
	(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(is_none_reloc): Likewise.
	* NEWS: Mention the new feature.

include	* dis-asm.h (arc_get_disassembler): Correct declaration.
	* arc-reloc.def: Macro file with definition of all relocation
	types.
	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
	enum defining the supported relocations.
	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
	macro for EM_ARC_COMPACT2.
        * arc-func.h: New file.
        * arc.h: Likewise.
 2015-10-07 14:20:19 +01:00
Yao Qi
e141d84e89 Make aarch64_zero_register_p declaration starts from column one 
include/opcode:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_zero_register_p): Move the declaration
	to column one.
 2015-10-02 15:43:46 +01:00
Yao Qi
36f4aab18c [aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn 
We want to use disas_aarch64_insn inside GDB to decode instructions, so
this patch exposes it and rename it to aarch64_decode_insn to follow
the conventions of other interfaces.

include/opcode:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_decode_insn): Declare it.

opcodes:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c	(disas_aarch64_insn): Remove static.  Change
	argument insn type to aarch64_insn.  Rename to ...
	(aarch64_decode_insn): ... it.
	(print_insn_aarch64_word): Caller updated.
 2015-10-02 15:23:58 +01:00
Dominik Vogt
7ecc513a44 Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine zEC12+nohtm+vx" 
gas	* doc/c-s390.texi: Add documentation.
	Add missing code markup.
	* config/tc-s390.c (current_flags): New static variable.
	(s390_parse_cpu): Parse cpu flags a la "+nohtm" etc.
	(s390_setup_opcodes): Use cpu flags to determine the set of opcodes.
	Fix indentation.
	(md_parse_option): Call s390_parse_cpu with the new signature.
	(s390_machine): Likewise.
	Keep track of current_flags.
	Simplify code a bit.
	undefine MAX_HISTORY at end of function.
	(s390_machinemode): undefine MAX_HISTORY at end of function.
	Update an error message.

tests	* gas/s390/s390.exp: Add new tests.
	* gas/s390/machine-parsing-1.s: New test file.
	* gas/s390/machine-parsing-1.l: Likewise.
	* gas/s390/machine-parsing-2.s: Likewise.
	* gas/s390/machine-parsing-2.l: Likewise.
	* gas/s390/machine-parsing-3.s: Likewise.
	* gas/s390/machine-parsing-3.l: Likewise.
	* gas/s390/machine-parsing-4.s: Likewise.
	* gas/s390/machine-parsing-4.l: Likewise.
	* gas/s390/machine-parsing-5.s: Likewise.
	* gas/s390/machine-parsing-5.l: Likewise.
	* gas/s390/machine-parsing-6.s: Likewise.
	* gas/s390/machine-parsing-6.l: Likewise.

opcode	* s390.h (S390_INSTR_FLAG_HTM): New flag.
	(S390_INSTR_FLAG_VX): New flag.
	(S390_INSTR_FLAG_FACILITY_MASK): New flag mask.

opcodes	* s390-mkopc.c (main): Parse htm and vx flag.
	* s390-opc.txt: Mark instructions from the hardware transactional
	memory and vector facilities with the "htm"/"vx" flag.
 2015-09-29 13:22:07 +01:00
jamesbowman
71f4ed30fe FT32: define macros for instruction recognition. 
Other places (e.g. the gdb stack unwinder) can use these instead of
hard-coded patterns.

[include/Changelog]

2015-09-26  James Bowman  <james.bowman@ftdichip.com>

	* opcode/ft32.h: Add instruction macros FT32_*()
 2015-09-28 11:23:54 -07:00
Nick Clifton
b6518b3871 Fix compile time warnings generated when compiling with clang. 
bfd	* bout.c (b_out_slurp_reloc_table): Cast constant to unsigned in
	order to avoid problems with left shifting negative values.
	(abs32code): Likewise.
	* mach-o.c (FILE_ALIGN): Likewise.
	* coff-rs6000.c (xcoff_debug_sections): Delete unused static
	array.
	* elf32-visium.c (visium_reloc_map): Likewise.
	* elf32-arm.c (elf32_arm_final_link_relocate): Remove useless
	calls to abs function.
	* elf32-frv.c (_frvfdpic_relax_tls_entries): Likewise.
	* elf32-score.c (score_elf_final_link_relocate): Likewise.
	* elf32-score7.c (score_elf_final_link_relocate): Likewise.
	* elf32-i860.c (i860_howto_pc26_reloc): Use multiplication instead
	of shifting to create a negative mask.
	* elf32-msp430.c (elf_backend_special_sections): Define.
	* elfxx-mips.c (got_ofst_reloc_p): Delete unused function.
	(got_hi16_reloc_p): Delete unused function.
	* ppcboot.c (ppcboot_bfd_print_private_bfd_data): Fix test of
	partition name.

gas	* config/tc-ppc.c (insn_validate): Cast PPC_OPSHIFT_INV to an int.

opcode	* ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
	shifting.

ld	* emultempl/elf32.em (ehdr_start_empty): New static variable.
	(before_allocation): Use it to initialise ehdr_start_save.
	* emultempl/pe.em (write_build_id): Remove useless double
	parenthesis.
	* emultempl/pep.em (write_build_id): Likewise.

opcodes	* bfin-dis.c (fmtconst): Remove unnecessary call to the abs
	function.
	* tic30-dis.c (print_branch): Likewise.
	* cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
	value before left shifting.
	* fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
	* hppa-dis.c (print_insn_hppa): Likewise.
	* mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
	array.
	* msp430-dis.c (msp430_singleoperand): Likewise.
	(msp430_doubleoperand): Likewise.
	(print_insn_msp430): Likewise.
	* nds32-asm.c (parse_operand): Likewise.
	* sh-opc.h (MASK): Likewise.
	* v850-dis.c (get_operand_value): Likewise.
 2015-09-23 18:05:16 +01:00
Nick Clifton
f04265eceb Enhance the RX disassembler to detect and report bad instructions. 
opcode	* rx.h (enum RX_Size): Add RX_Bad_Size entry.

opcodes	* rx-decode.opc (bwl): Use RX_Bad_Size.
	(sbwl): Likewise.
	(ubwl): Likewise.  Rename to ubw.
	(uBWL): Rename to uBW.
	Replace all references to uBWL with uBW.
	* rx-decode.c: Regenerate.
	* rx-dis.c (size_names): Add entry for RX_Bad_Size.
	(opsize_names): Likewise.
	(print_insn_rx): Detect and report RX_Bad_Size.
 2015-09-22 17:21:13 +01:00
Nick Clifton
7bdf96efee Make register name tables in visium.h static in order to prevent multiple definitions. 
* visium.h (gen_reg_table): Make static.
	(fp_reg_table): Likewise.
	(cc_table): Likewise.
 2015-09-09 14:50:08 +01:00
H.J. Lu
72f4393d8c Remove leading/trailing white spaces in ChangeLog 2015-07-24 04:16:47 -07:00
Matthew Wahab
f33026a965 [ARM] Support correctly spelled ARMv6KZ architecture names 
2015-07-20  Matthew Wahab  <matthew.wahab@arm.com>

gas/
    * NEWS: Mention corrected spelling of armv6kz.
    * config/tc-arm.c (arm_cpus): Replace ARM_ARCH_V6ZK with
    ARM_ARCH_V6KZ.
    (arm_archs): Likewise. Also add "armv6kz" and "armv6kzt2".
    * doc/c-arm.texi: Replace "armv6zk" with "armv6kz".

gas/testsuite

    * gas/arm/attr-march-armv6kz.d: New.
    * gas/arm/attr-march-armv6kzt2.d: New.

include/opcode

    * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
    (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
    (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
    (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
 2015-07-21 09:43:35 +01:00
Alan Modra
ef5a96d564 Remove ppc860, ppc750cl, ppc7450 insns from common ppc. 
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations.  I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8.  This
patch fixes that problem.

Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code.  ie. you might need to modify
makefiles to pass -m860 to gas.

include/opcode/
	* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
	* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
	* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
	PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
gas/
	* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
	* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
	* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
 2015-07-03 10:57:14 +09:30
Sandra Loosemore
c8c8175b62 Opcodes and assembler support for Nios II R2 
2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
	    Cesar Philippidis  <cesar@codesourcery.com>

	gas/
	* config/tc-nios2.c (nios2_min_align): New.
	(nop): Replace with....
	(nop_r1, nop_r2, nop_r2_cdx, nop32, nop16): New.
	(nios2_align): Handle alignment on 2-byte boundaries when CDX
	instructions may be present.
	(s_nios2_align): Adjust reference to nop.
	(CDXBRANCH, IS_CDXBRANCH): New.
	(CDX_UBRANCH_SUBTYPE, CDX_CBRANCH_SUBTYPE): New.
	(nios2_relax_subtype_size): Handle 2-byte CDX branches.
	(nios2_relax_frag): Likewise.
	(md_convert_frag): Handle R2 encodings.
	(nios2_check_overflow): Check that low-order bits are zero
	before applying rightshift from howto.
	(nios2_check_overflow): Correct negative overflow calculation.
	(nios2_diagnose_overflow): Handle signed_immed12_overflow.  Issue
	generic overflow messages for miscellaneous instruction formats.
	(md_apply_fix): Recognize new R2 relocations.  For pc_relative
	relocations, store fixup in *valP.
	(nios2_reglist_mask, nios2_reglist_dir): New.
	(nios2_parse_reglist): New.
	(nios2_parse_base_register): New.
	(nios2_assemble_expression): Handle constant expressions designated
	by BFD_RELOC_NONE.
	(nios2_assemble_reg3): New.
	(nios2_assemble_arg_c): Handle R2 instruction formats.
	(nios2_assemble_arg_d): Likewise.
	(nios2_assemble_arg_s): Likewise.
	(nios2_assemble_arg_t): Likewise.
	(nios2_assemble_arg_D): New.
	(nios2_assemble_arg_S): New.
	(nios2_assemble_arg_T): New.
	(nios2_assemble_arg_i): Handle R2 instruction formats.
	(nios2_assemble_arg_I): New.
	(nios2_assemble_arg_u): Handle R2 instruction formats.
	(nios2_assemble_arg_U): New.
	(nios2_assemble_arg_V): New.
	(nios2_assemble_arg_W): New.
	(nios2_assemble_arg_X): New.
	(nios2_assemble_arg_Y): New.
	(nios2_assemble_arg_o): Handle R2 instruction formats.
	(nios2_assemble_arg_O): New.
	(nios2_assemble_arg_P): New.
	(nios2_assemble_arg_j): Handle R2 instruction formats.
	(nios2_assemble_arg_k): New.
	(nios2_assemble_arg_l): Handle R2 instruction formats.
	(nios2_assemble_arg_m): Likewise.
	(nios2_assemble_arg_M): New.
	(nios2_assemble_arg_N): New.
	(nios2_assemble_arg_e): New.
	(nios2_assemble_arg_f): New.
	(nios2_assemble_arg_g): New.
	(nios2_assemble_arg_h): New.
	(nios2_assemble_arg_R): New.
	(nios2_assemble_arg_B): New.
	(nios2_assemble_args): Handle new argument letters.
	(nios2_consume_arg): Likewise.
	(nios2_translate_pseudo_insn): Avoid dereferencing null pointer
	in error message.
	(nios2_ps_insn_info_structs): Add nop.n.
	(output_ubranch): Handle CDX branches.
	(output_cbranch): Likewise.
	(output_call): Handle R2 encodings.
	(output_movia): Likewise.
	(md_begin): Initialize nios2_min_align.
	(md_assemble): Align to nios2_min_align.  Adjust nios2_min_align
	if a 16-bit instruction is seen.
	(nios2_cons_align): Use appropriate nop pattern.

	include/opcode/
	* nios2.h (enum iw_format_type): Add R2 formats.
	(enum overflow_type): Add signed_immed12_overflow and
	enumeration_overflow for R2.
	(struct nios2_opcode): Document new argument letters for R2.
	(REG_3BIT, REG_LDWM, REG_POP): Define.
	(includes): Include nios2r2.h.
	(nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
	(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
	(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
	(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
	(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
	(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
	Declare.
	* nios2r2.h: New file.

	opcodes/
	* nios2-dis.c (nios2_extract_opcode): New.
	(nios2_disassembler_state): New.
	(nios2_find_opcode_hash): Use mach parameter to select correct
	disassembler state.
	(nios2_print_insn_arg): Extend to support new R2 argument letters
	and formats.
	(print_insn_nios2): Check for 16-bit instruction at end of memory.
	* nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
	(NIOS2_NUM_OPCODES): Rename to...
	(NIOS2_NUM_R1_OPCODES): This.
	(nios2_r2_opcodes): New.
	(NIOS2_NUM_R2_OPCODES): New.
	(nios2_num_r2_opcodes): New.
	(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
	(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
	(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
	(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
	(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):	New.
 2015-07-01 16:08:03 -07:00
Peter Bergner
11a0cf2ec0 Allow for optional operands with non-zero default values. 
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1.  It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case.  I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.

This fixes the rfebb issue.  I also fixed the mftb and mfcr instructions
so they use the same mechanism.  This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].

include/opcode/

	* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
	(ppc_optional_operand_value): New inline function.

opcodes/
	* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
	* ppc-opc.c (FXM4): Add non-zero optional value.
	(TBR): Likewise.
	(SXL): Likewise.
	(insert_fxm): Handle new default operand value.
	(extract_fxm): Likewise.
	(insert_tbr): Likewise.
	(extract_tbr): Likewise.

gas/
	* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
	Allow for optional operands without insert functions.

gas/testsuite/
	* gas/ppc/power8.d: Fixup rfebb test results.
	* gas/ppc/a2.s: Fix invalid mfcr test.
	* gas/ppc/a2.d: Likewise.
 2015-06-19 17:17:07 -05:00
Matthew Wahab
88f0ea342d [AArch64] Add support for ARMv8.1 command line option 2015-06-04 11:14:07 +01:00
Matthew Wahab
a5932920ef [ARM] Support for ARMv8.1 command line option 
2015-06-03  Matthew Wahab  <matthew.wahab@arm.com>

gas/
	* config/tc-arm.c (arm_archs): Add "armv8.1-a".
	* doc/c-arm.texi (ARM Options, -march): Add "armv8.1-a".
	* NEWS: Mention ARMv8.1 support.

include/opcode/
	* arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
	(ARM_ARCH_V8_1A): New.
	(ARM_ARCH_V8_1A_FP): New.
	(ARM_ARCH_V8_1A_SIMD): New.
	(ARM_ARCH_V8_1A_CRYPTOV1): New.
	(ARM_FEATURE_CORE): New.
 2015-06-03 10:03:50 +01:00