This patch updates GNU_PROPERTY_X86_XXX macros for gold:
1. GNU_PROPERTY_X86_UINT32_AND_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in all relocatable inputs:
#define GNU_PROPERTY_X86_UINT32_AND_LO 0xc0000002
#define GNU_PROPERTY_X86_UINT32_AND_HI 0xc0007fff
2. GNU_PROPERTY_X86_UINT32_OR_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in any relocatable inputs:
#define GNU_PROPERTY_X86_UINT32_OR_LO 0xc0008000
#define GNU_PROPERTY_X86_UINT32_OR_HI 0xc000ffff
3. GNU_PROPERTY_X86_UINT32_OR_AND_XXX: A 4-byte unsigned integer property.
A bit is set if it is set in any relocatable inputs and the property is
present in all relocatable inputs:
#define GNU_PROPERTY_X86_UINT32_OR_AND_LO 0xc0010000
#define GNU_PROPERTY_X86_UINT32_OR_AND_HI 0xc0017fff
4. GNU_PROPERTY_X86_FEATURE_2_NEEDED, GNU_PROPERTY_X86_FEATURE_2_USED
and GNU_PROPERTY_X86_FEATURE_2_XXX bits.
GNU_PROPERTY_X86_FEATURE_1_AND is unchanged. GNU_PROPERTY_X86_ISA_1_USED
and GNU_PROPERTY_X86_ISA_1_NEEDED are updated to better support targeted
processors since GNU_PROPERTY_X86_ISA_1_?86 aren't isn't very useful.
A new set of GNU_PROPERTY_X86_ISA_1_XXX bits are defined. The previous
GNU_PROPERTY_X86_ISA_1_XXX macros are deprecated and renamed to
GNU_PROPERTY_X86_COMPAT_ISA_1_XXX and GNU_PROPERTY_X86_COMPAT_2_ISA_1_XXX.
elfcpp/
* elfcpp.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_ISA_1_USED): This.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ...
(GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED): This.
(GNU_PROPERTY_X86_UINT32_AND_LO): New.
(GNU_PROPERTY_X86_UINT32_AND_HI): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_LO): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_HI): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_AND_LO): Likewise.
(GNU_PROPERTY_X86_UINT32_OR_AND_HI): Likewise.
(GNU_PROPERTY_X86_COMPAT_2_ISA_1_NEEDED): New.
(GNU_PROPERTY_X86_COMPAT_2_ISA_1_NEEDED): Likewise.
(GNU_PROPERTY_X86_FEATURE_1_AND): Updated to
(GNU_PROPERTY_X86_UINT32_AND_LO + 0).
(GNU_PROPERTY_X86_ISA_1_NEEDED): New. Defined to
GNU_PROPERTY_X86_UINT32_OR_LO + 2.
(GNU_PROPERTY_X86_FEATURE_2_NEEDED): New. Defined to
(GNU_PROPERTY_X86_UINT32_OR_LO + 1).
(GNU_PROPERTY_X86_ISA_1_USED): New. Defined to
GNU_PROPERTY_X86_UINT32_OR_AND_LO + 2.
(GNU_PROPERTY_X86_FEATURE_2_USED): New. Defined to
(GNU_PROPERTY_X86_UINT32_OR_AND_LO + 1).
gold/
* x86_64.cc (Target_x86_64::Target_x86_64): Initialize
feature_2_used_, feature_2_needed_ and object_feature_2_used_.
(Target_x86_64::feature_2_used_): New data member.
(Target_x86_64::feature_2_needed_): Likewise.
(Target_x86_64::object_isa_1_used_): Likewise.
(Target_x86_64::record_gnu_property): Support
GNU_PROPERTY_X86_COMPAT_ISA_1_USED,
GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED,
GNU_PROPERTY_X86_COMPAT_2_ISA_1_USED,
GNU_PROPERTY_X86_COMPAT_2_ISA_1_NEEDED,
GNU_PROPERTY_X86_FEATURE_2_USED and
GNU_PROPERTY_X86_FEATURE_2_NEEDED.
(Target_x86_64::merge_gnu_properties): Merge FEATURE_2_USED bits.
Initialize object_feature_2_used_.
(Target_x86_64::do_finalize_gnu_properties): Support
GNU_PROPERTY_X86_FEATURE_2_USED and
GNU_PROPERTY_X86_FEATURE_2_NEEDED.
* testsuite/gnu_property_a.S (GNU_PROPERTY_X86_ISA_1_USED): Set
to 0xc0010002.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Set to 0xc0008002.
* testsuite/gnu_property_b.S (GNU_PROPERTY_X86_ISA_1_USED): Set
to 0xc0010002.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Set to 0xc0008002.
* testsuite/gnu_property_c.S (GNU_PROPERTY_X86_ISA_1_USED): Set
to 0xc0010002.
(GNU_PROPERTY_X86_ISA_1_NEEDED): Set to 0xc0008002.
* testsuite/gnu_property_test.sh: Updated.
At least one C library (uclibc-ng) defines some of these only when
the compiler is GCC. We might as well test for all three cases and
handle any of them being missing.
Very similar code exists in libctf and split between elfcpp and gold:
fix both.
(Also sync up elfcpp with a change made to libctf swap.h a few months
ago: since there is no out-of-line definition of the bswap replacements,
they should be declared static inline, not just inline, to prevent the
linker generating out-of-line references to them.)
PR libctf/25120
libctf/
* configure.ac: Check for bswap_16, bswap_32, and bswap_64 decls.
* swap.h (bswap_16): Do not assume that presence of <byteswap.h>
means this is declared.
(bswap_32): Likewise.
(bswap_64): Likewise.
(bswap_identity_64): Remove, unused.
* configure: Regenerated.
* config.h.in: Likewise.
gold/
* configure.ac: Check for bswap_16, bswap_32, and bswap_64 decls.
* configure: Regenerated.
* config.h.in: Likewise.
elfcpp/
* elfcpp_swap.h (bswap_16): Do not assume that presence of
<byteswap.h> means this is declared. Make static inline, matching
recent change to libctf, since there is no non-inline definition
of these functions.
(bswap_32): Likewise.
(bswap_64): Likewise.
These relocations should have had REL in their names, to reflect the
fact that they are pc-relative. Fix that now by adding _PCREL.
I've added some back-compatibility code to support anyone using
.reloc with the old relocations.
include/
* elf/ppc64.h (elf_ppc64_reloc_type): Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
bfd/
* reloc.c: Rename
BFD_RELOC_PPC64_GOT_TLSGD34 to BFD_RELOC_PPC64_GOT_TLSGD_PCREL34,
BFD_RELOC_PPC64_GOT_TLSLD34 to BFD_RELOC_PPC64_GOT_TLSLD_PCREL34,
BFD_RELOC_PPC64_GOT_TPREL34 to BFD_RELOC_PPC64_GOT_TPREL_PCREL34,
BFD_RELOC_PPC64_GOT_DTPREL34 to BFD_RELOC_PPC64_GOT_DTPREL_PCREL34.
* elf64-ppc.c: Update throughout for reloc renaming.
(ppc64_elf_reloc_name_lookup): Handle old reloc names.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c: Update throughout for reloc renaming.
elfcpp/
* powerpc.h: Rename
R_PPC64_GOT_TLSGD34 to R_PPC64_GOT_TLSGD_PCREL34,
R_PPC64_GOT_TLSLD34 to R_PPC64_GOT_TLSLD_PCREL34,
R_PPC64_GOT_TPREL34 to R_PPC64_GOT_TPREL_PCREL34, and
R_PPC64_GOT_DTPREL34 to R_PPC64_GOT_DTPREL_PCREL34.
gold/
* powerpc.cc: Update throughout for reloc renaming.
Gold version of git commit c213164ad2.
elfcpp/
* powerpc.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::get_reference_flags): Set
flags for new relocations, and some missing older relocs.
(Target_powerpc::Scan::local): Handle new pcrel tls relocs.
Call set_has_static_tls for tprel relocs.
(Target_powerpc::Scan::global): Likewise.
(Target_powerpc::Relocate::relocate): Handle new pcrel tls relocs.
Calls from notoc functions via the PLT need different stubs. Even
calls to local functions requiring a valid toc pointer must go via a
stub. This patch provides the support in gold.
elfcpp/
* powerpc.h (R_PPC64_PLTSEQ_NOTOC, R_PPC64_PLTCALL_NOTOC): Define.
gold/
* powerpc.cc (Target_powerpc::maybe_skip_tls_get_addr_call): Handle
notoc calls.
(is_branch_reloc): Template on size. Return true for REL24_NOTOC.
Update all callers.
(max_branch_delta): Likewise.
(Target_powerpc::Branch_info::make_stub): Add a stub for notoc
calls to functions needing a valid toc pointer.
(Target_powerpc::do_relax): Layout stubs again if any need resize.
(add_12_11_12, addi_12_11, addis_12_11, ldx_12_11_12, ori_12_12_0),
(oris_12_12_0, sldi_12_12_32): Define.
(Stub_table::Plt_stub_ent): Add notoc_ and iter_ fields.
(Stub_table::Branch_stub_key, Branch_stub_key_hash): Rename from
Branch_stub_ent and Branch_stub_ent hash. Remove save_res_ from key.
(Stub_table::Branch_stub_ent): New struct.
(class Stub_table): Add need_resize and resizing vars.
(Stub_table::need_resize, branch_size): New accessors.
(Stub_table::set_resizing): New function.
(Stub_table::add_plt_call_entry): Handle notoc calls and resizing
on seeing such or a tocsave stubs after a normal stub using the
same sym.
(Stub_table::add_long_branch_entry): Similarly.
(Stub_table::find_long_branch_entry): Return a Branch_stub_ent*.
(Stub_table::define_stub_syms): Adjust
(Stub_table::build_tls_opt_head, build_tls_opt_tail): New functions.
(build_notoc_offset): New function.
(Stub_table::plt_call_size): Move out of line. Handle notoc calls.
(Stub_table::branch_stub_size): Similarly.
(Stub_table::do_write): Separate loop for ELFv2 stubs, handling
notoc calls. Simplify ELFv1 loop. Output notoc branch stubs.
Use build_tls_opt_head and build_tls_opt_tail.
(Target_powerpc::Scan::get_reference_flags): Handle REL24_NOTOC.
(Target_powerpc::Scan::reloc_needs_plt_for_ifunc): Likewise,
and PLTSEQ_NOTOC and PLTCALL_NOTOC.
(Target_powerpc::Scan::local, global, relocate): Likewise.
These relocs have been around for quite a while. It's past time gold
supported them.
elfcpp/
* powerpc.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::get_reference_flags): Handle
REL16_HIGH* relocs.
(Target_powerpc::Scan::local): Likewise.
(Target_powerpc::Scan::global): Likewise.
(Target_powerpc::Relocate::relocate): Likewise.
bfd/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch.
binutils/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values.
(arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch.
elfcpp/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* arm.h (Tag_MVE_arch): Define new enum value.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (mve_ext, mve_fp_ext): New features.
(armv8_1m_main_ext_table): Add new extensions.
(aeabi_set_public_attributes): Translate new features to new build attributes.
(arm_convert_symbolic_attribute): Add Tag_MVE_arch.
* doc/c-arm.texi: Document new extensions and new build attribute.
include/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf/arm.h (Tag_MVE_arch): Define new enum value.
* opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the first
instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF12.
The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the
immediate and we don't externally.
ChangeLog entries are as follows :
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF12): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BFL instructions which is one of the first instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF18.
The inconsistency between external R_ARM_THM_BF18 and internal
BFD_RELOC_ARM_THUMB_BF19 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF19): New
* libbfd.h: Regenerated.
* bfd-in2.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF18.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF19
and R_ARM_THM_BF18 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF19.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF18): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF19.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This adds infrastructure for the BF instructions which is one of the first instructions in Arm that have more than one relocations in them.
This is the third infrastructure patch that adds a new relocation R_ARM_THM_BF16.
The inconsistency between external R_ARM_THM_BF16 and internal
BFD_RELOC_ARM_THUMB_BF17 is because internally we count the static bit-0 of the immediate and we don't externally.
ChangeLog entries are as follows :
*** bfd/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF17): New enum.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* bfd-elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF16.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF17
and R_ARM_THM_BF16 together.
(get_value_helper): New reloc helper.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF16.
*** elfcpp/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF16): New relocation code.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF17.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
elfcpp/
PR gold/22914
* elfcpp.h (NT_GNU_PROPERTY_TYPE_0): New note type.
(GNU_PROPERTY_*): New Gnu property types.
* x86_64.h (GNU_PROPERTY_X86_FEATURE_1_IBT)
(GNU_PROPERTY_X86_FEATURE_1_SHSTK): New x86 feature bits.
gold/
PR gold/22914
* layout.cc (Layout::Layout): Initialize gnu_properties_.
(read_sized_value, write_sized_value): New functions.
(Layout::layout_gnu_property): New method.
(Layout::create_notes): Call create_gnu_properties_note.
(Layout::create_gnu_properties_note): New method.
* layout.h (Layout::layout_gnu_property): New method.
(Layout::create_gnu_properties_note): New method.
(Layout::Gnu_property, Layout::Gnu_properties): New types.
(Layout::gnu_properties_): New data member.
* object.cc (Sized_relobj_file::layout_gnu_property_section): New
method.
(Sized_relobj_file::do_layout): Handle .note.gnu.property sections.
* object.h (Sized_relobj_file::layout_gnu_property_section): New
method.
* target.h (Target::merge_gnu_property): New method.
(Target::do_merge_gnu_property): New virtual method.
* x86_64.cc (Target_x86_64::do_merge_gnu_property): New method.
* testsuite/Makefile.am (gnu_property_test): New test case.
* testsuite/Makefile.in: Regenerate.
* testsuite/gnu_property_a.S: New source file.
* testsuite/gnu_property_b.S: New source file.
* testsuite/gnu_property_c.S: New source file.
* testsuite/gnu_property_main.c: New source file.
* testsuite/gnu_property_test.sh: New test script.
In addition to the existing relocs we need two more to mark all
instructions in the call sequence, PLTCALL on the call itself (plus
the toc restore insn for ppc64), and PLTSEQ on others. All
relocations in a particular sequence have the same symbol.
Example ppc64 ELFv2 assembly:
.reloc .,R_PPC64_PLTSEQ,puts
std 2,24(1)
addis 12,2,puts@plt@ha # .reloc .,R_PPC64_PLT16_HA,puts
ld 12,puts@plt@l(12) # .reloc .,R_PPC64_PLT16_LO_DS,puts
.reloc .,R_PPC64_PLTSEQ,puts
mtctr 12
.reloc .,R_PPC64_PLTCALL,puts
bctrl
ld 2,24(1)
Example ppc32 -fPIC assembly:
addis 12,30,puts+32768@plt@ha # .reloc .,R_PPC_PLT16_HA,puts+0x8000
lwz 12,12,puts+32768@plt@l # .reloc .,R_PPC_PLT16_LO,puts+0x8000
.reloc .,R_PPC_PLTSEQ,puts+32768
mtctr 12
.reloc .,R_PPC_PLTCALL,puts+32768
bctrl
Marking sequences like this allows the linker to convert them to nops
and a direct call if the target symbol turns out to be local.
When the call is __tls_get_addr, each relocation shown above is paired
with an R_PPC*_TLSLD or R_PPC*_TLSGD reloc to additionally mark the
sequence for possible TLS optimization. The TLSLD or TLSGD relocs are
emitted first.
include/
* elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
* elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw): Add PLTSEQ and PLTCALL howtos.
(is_plt_seq_reloc): New function.
(ppc_elf_check_relocs): Handle PLTSEQ and PLTCALL relocs.
(ppc_elf_tls_optimize): Handle inline plt call sequence.
(ppc_elf_relax_section): Handle PLTCALL reloc.
(ppc_elf_relocate_section): Nop out inline plt call sequence when
resolving locally.
* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_PLTSEQ and
R_PPC64_PLTCALL entries. Comment R_PPC64_TOCSAVE.
(has_tls_get_addr_call): Correct comment.
(is_branch_reloc): Add PLTCALL.
(is_plt_seq_reloc): New function.
(ppc64_elf_check_relocs): Handle PLT16_LO_DS reloc. Set
has_tls_reloc for R_PPC64_TLSGD and R_PPC64_TLSLD. Create plt
entry for R_PPC64_PLTCALL.
(ppc64_elf_tls_optimize): Handle inline plt call sequence.
(ppc_type_of_stub): Handle PLTCALL reloc.
(toc_adjusting_stub_needed): Likewise.
(ppc64_elf_relocate_section): Set "can_plt_call" for PLTCALL
reloc insn. Nop out inline plt call sequence when resolving
locally. Handle __tls_get_addr inline plt call optimization.
elfcpp/
* powerpc.h (R_POWERPC_PLTSEQ, R_POWERPC_PLTCALL): Define.
gold/
* powerpc.cc (Target_powerpc::Track_tls::maybe_skip_tls_get_addr_call):
Handle inline plt sequence relocs.
(Stub_table::Plt_stub_key::Plt_stub_key): Likewise.
(Target_powerpc::Scan::reloc_needs_plt_for_ifunc): Likewise.
(Target_powerpc::Relocate::relocate): Likewise.
This implements the special __tls_get_addr_opt call stub for powerpc
gold that returns __thread variable addresses without actually making
a call to __tls_get_addr in most cases. Shared libraries that are
loaded at program load time (ie. dlopen is not used) have a known
layout for their __thread variables, and thus DTPMOD64/DPTREL64 pairs
describing those variables can be set up by ld.so for the
__tls_get_addr_opt call stub fast exit.
Ref https://sourceware.org/ml/libc-alpha/2015-03/msg00626.html
I really, really wish I'd used a differently versioned __tls_get_addr
symbol than the base symbol to indicate glibc support for the
optimized call, rather than having glibc export __tls_get_addr_opt. A
lot of the messing around here, flipping symbols from __tls_get_addr
to __tls_get_addr_opt, is caused by that decision. About the only
benefit is that a user can see at a glance that their disassembled
code is calling __tls_get_addr via the fancy call stub.. Anyway, we
need references to __tls_get_addr to seem like they were to
__tls_get_addr_opt, and in cases like the tsan interceptor, a
definition of __tls_get_addr to seem like one of __tls_get_addr_opt
as well. That's the reason for Symbol::clear_in_reg and
Symbol_table::clone, and why symbols are substituted in Scan::global
and other places dealing with dynamic linking.
elfcpp/
* elfcpp.h (DT_PPC_OPT): Define.
* powerpc.h (PPC_OPT_TLS): Define.
gold/
* options.h (tls_get_addr_optimize): New option.
* symtab.h (Symbol::clear_in_reg, clone): New functions.
(Sized_symbol::clone): New function.
(Symbol_table::clone): New function.
* resolve.cc (Symbol::clone, Sized_symbol::clone): New functions.
* powerpc.cc (Target_powerpc::has_tls_get_addr_opt_,
tls_get_addr_, tls_get_addr_opt_): New vars.
(Target_powerpc::tls_get_addr_opt, tls_get_addr,
is_tls_get_addr_opt, replace_tls_get_addr,
set_has_tls_get_addr_opt, stk_linker): New functions.
(Target_powerpc::Track_tls::maybe_skip_tls_get_addr_call): Add
target param. Update callers. Compare symbols rather than names.
(Target_powerpc::do_define_standard_symbols): Init tls_get_addr_
and tls_get_addr_opt_.
(Target_powerpc::Branch_info::mark_pltcall): Translate tls_get_addr
sym to tls_get_addr_opt.
(Target_powerpc::Branch_info::make_stub): Likewise.
(Stub_table::define_stub_syms): Likewise.
(Target_powerpc::Scan::global): Likewise.
(Target_powerpc::Relocate::relocate): Likewise.
(add_3_12_2, add_3_12_13, bctrl, beqlr, cmpdi_11_0, cmpwi_11_0,
ld_11_1, ld_11_3, ld_12_3, lwz_11_3, lwz_12_3, mr_0_3, mr_3_0,
mtlr_11, std_11_1): New constants.
(Stub_table::eh_frame_added_): Delete.
(Stub_table::tls_get_addr_opt_bctrl_, plt_fde_len_, plt_fde_): New vars.
(Stub_table::init_plt_fde): New functions.
(Stub_table::add_eh_frame, replace_eh_frame): Move definition out
of line. Init and use plt_fde_.
(Stub_table::plt_call_size): Return size for tls_get_addr stub.
Extract alignment code to..
(Stub_table::plt_call_align): ..this new function. Adjust all callers.
(Stub_table::add_plt_call_entry): Set has_tls_get_addr_opt and
tls_get_addr_opt_bctrl, and align after that.
(Stub_table::do_write): Write out tls_get_addr stub.
(Target_powerpc::do_finalize_sections): Emit DT_PPC_OPT
PPC_OPT_TLS/PPC64_OPT_TLS bit.
(Target_powerpc::Relocate::relocate): Don't check for or modify
nop following bl for tls_get_addr stub.
The 64-bit ELF compression header has a reserved field. It should be
cleared to avoid random bits in it.
elfcpp/
PR gold/21857
* elfcpp.h (Chdr_write): Add put_ch_reserved.
(Chdr_write<64, true>::put_ch_reserved): New.
(Chdr_write<64, false>::put_ch_reserved): Likewise.
gold/
PR gold/21857
* compressed_output.cc (Output_compressed_section::set_final_data_size):
Call put_ch_reserved to clear the reserved field for 64-bit ELF.
elfcpp/
* elfcpp.h (DT_PPC64_OPT): Define.
* powerpc.h (PPC64_OPT_TLS, PPC64_OPT_MULTI_TOC,
PPC64_OPT_LOCALENTRY): Define.
gold/
* options.h (General_options): Add plt_localentry.
* powerpc.cc (Target_powerpc::st_other): New function.
(Target_powerpc::plt_localentry0_, plt_localentry0_init_,
has_localentry0_): New vars.
(Target_powerpc::plt_localentry0, set_has_localentry0,
is_elfv2_localentry0): New functions.
(Target_powerpc::Branch_info::mark_pltcall): Don't set tocsave or
return true for localentry:0 calls.
(Stub_table::Plt_stub_ent::localentry0_): New var.
(Stub_table::add_plt_call_entry): Set localentry0_ and has_localentry0_.
Don't set r2save_ for localentry:0 calls.
(Output_data_glink::do_write): Save r2 in __glink_PLTresolve for elfv2.
(Target_powerpc::scan_relocs): Default plt_localentry0_.
(Target_powerpc::do_finalize_sections): Set DT_PPC64_OPT.
(Target_powerpc::Relocate::relocate): Don't require nop following
calls for localentry:0 plt calls, and don't change nop.
Includes DT_MIPS_RLD_MAP and DT_MIPS_RLD_MAP_REL dynamic tags and
__RLD_MAP symbol.
2016-06-20 Vladimir Radosavljevic <Vladimir.Radosavljevic@imgtec.com>
elfcpp/
* elfcpp.h (DT_MIPS_RLD_MAP_REL): New enum constant.
gold/
* mips.cc (Target_mips::Target_mips): Initialize rld_map_.
(Target_mips::rld_map_): New data member.
(Target_mips::do_finalize_sections): Add support for
DT_MIPS_RLD_MAP and DT_MIPS_RLD_MAP_REL dynamic tags,
.rld_map section, and __RLD_MAP symbol.
(Target_mips::do_dynamic_tag_custom_value): Add support for
DT_MIPS_RLD_MAP_REL dynamic tag.
* output.cc (Output_data_dynamic::get_entry_offset): New method
definition.
* output.h (Output_data_dynamic::get_entry_offset): New method
declaration.
elfcpp/
* mips.h (R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
R_MIPS_PC19_S2, R_MIPS_PCHI16, R_MIPS_PCLO16): New enums for
Mips32r6 and Mips64r6 relocations.
(r6_isa): New function.
gold/
* mips.cc (relocation_needs_la25_stub): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(hi16_reloc): Add support for R_MIPS_PCHI16 relocation.
(is_matching_lo16_reloc): Likewise.
(lo16_reloc): Add support for R_MIPS_PCLO16 relocation.
(Mips_output_data_plt::plt_entry_r6): New static data member for
R6 PLT entry.
(Target_mips::is_output_r6): New method.
(Target_mips::Mips_mach): Add new enum constants.
(Mips_relocate_functions::Status): Likewise.
(Mips_relocate_functions::pchi16_relocs): New static data member.
(Mips_relocate_functions::relpc21): New method.
(Mips_relocate_functions::relpc26): Likewise.
(Mips_relocate_functions::relpc18): Likewise.
(Mips_relocate_functions::relpc19): Likewise.
(Mips_relocate_functions::relpchi16): Likewise.
(Mips_relocate_functions::do_relpchi16): Likewise.
(Mips_relocate_functions::relpclo16): Likewise.
(Mips_output_data_plt::do_write): Add support for Mips r6 plt
entry.
(Target_mips::mips_32bit_flags): Add E_MIPS_ARCH_32R6 support.
(Target_mips::elf_mips_mach): Add E_MIPS_ARCH_32R6 and
E_MIPS_ARCH_64R6 support.
(Target_mips::update_abiflags_isa): Likewise.
(mips_get_size_for_reloc): Add support for relocs: R_MIPS_PCHI16,
R_MIPS_PCLO16, R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3 and
R_MIPS_PC19_S2.
(Target_mips::Scan::local): Add support for relocs: R_MIPS_PCHI16
and R_MIPS_PCLO16.
(Target_mips::Scan::global): Add support for relocs:
R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
(Target_mips::Relocate::relocate): Call functions for resolving
Mips32r6 and Mips64r6 relocations, and print error message for
STATUS_PCREL_UNALIGNED.
(Target_mips::Scan::get_reference_flags): Add support for relocs:
R_MIPS_PCHI16, R_MIPS_PCLO16, R_MIPS_PC21_S2, R_MIPS_PC26_S2,
R_MIPS_PC18_S3 and R_MIPS_PC19_S2.
(Target_mips::elf_mips_mach_name): Add E_MIPS_ARCH_32R6 and
E_MIPS_ARCH_64R6 support.
