Nick Clifton
84ea6cf2c5
Add MIPS V and MIPS 64 machine numbers
2000-12-02 00:55:22 +00:00
Nick Clifton
e7af610e14
Add MIPS32 as a seperate MIPS architecture
2000-12-01 21:35:38 +00:00
Nick Clifton
4372b67322
Improve MIPS32 support
2000-12-01 20:05:32 +00:00
Jakub Jelinek
19f7b01094
gas/
...
* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
instructions to loose any special insn->architecture mask.
* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
(sparc_md_end, sparc_arch_types, sparc_arch,
sparc_elf_final_processing): Handle v8plusb and v9b architectures.
(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
request v9b architecture if they are used).
bfd/
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
elf32_sparc_object_p, elf32_sparc_final_write_processing):
Support v8plusb.
* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
sparc64_elf_object_p): Support v9b.
* archures.c: Declare v8plusb and v9b machines.
* bfd-in2.h: Ditto.
* cpu-sparc.c: Ditto.
include/opcode/
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
Note that '3' is used for siam operand.
opcodes/
* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
(compute_arch_mask): Add v8plusb and v9b machines.
(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
* opcodes/sparc-opc.c: Support for Cheetah instruction set.
(prefetch_table): Add #invalidate.
2000-10-20 10:38:47 +00:00
Jim Wilson
139368c9f3
Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again.
...
gas/ChangeLog
* config/tc-ia64.c (dv_sem): Add "stop".
(specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now.
(specify_resource, case IA64_RS_PRr): New for regs 16 to 62.
(specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to
match above.
(mark_resources): Check IA64_RS_PRr.
gas/testsuite/ChangeLog
* gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/dv-imply.d: Regenerate.
* gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d,
gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l,
gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise.
include/opcode/ChangeLog
* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
opcodes/ChangeLog
* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
* ia64-asmtab.c: Regnerate.
2000-09-22 19:43:50 +00:00
Nick Clifton
156c2f8bf7
Add support for the MIPS32
2000-09-14 01:47:38 +00:00
Alan Modra
3c5ce02eb8
doco addition.
2000-09-05 05:22:24 +00:00
Jim Wilson
50b81f1903
Fix 3 DV bugs, and a few minor cleanups.
...
gas/
* config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle
postincrement modified registers. Handle IA64_OPND_R3_2 addl
source registers.
(note_register_values): Handle IA64_OPND_R3_2 operands.
gas/testsuite/
* gas/ia64/dv-raw-err.s: Add new tests for addl and postinc.
* gas/ia64/dv-raw-err.l: Likewise.
* gas/ia64/dv-waw-err.l: Update sed pattern.
* gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment.
* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
include/opcode/
* ia64.h (IA64_OPCODE_POSTINC): New.
opcodes/
* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
break, mov-immediate, nop.
* ia64-opc-f.c: Delete fpsub instructions.
* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
address operand. Rewrite using macros to avoid long lines.
* ia64-opc.h (POSTINC): Define.
* ia64-asmtab.c: Regenerate.
2000-08-16 23:20:15 +00:00
H.J. Lu
fc29466dba
2000-08-15 H.J. Lu <hjl@gnu.org>
...
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
IgnoreSize change.
2000-08-16 17:29:23 +00:00
Denis Chertykov
45ee1401ab
* avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.
...
Move related opcodes closer to each other.
Minor changes in comments, list undefined opcodes.
2000-08-06 14:09:14 +00:00
Dave Brolley
9d551405de
2000-07-26 Dave Brolley <brolley@redhat.com>
...
* cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
2000-07-26 22:44:42 +00:00
Hans-Peter Nilsson
c848861769
cris.h: New file.
2000-07-20 15:39:41 +00:00
Nick Clifton
65aa24b6e8
Applied Marek Michalkiewicz <marekm@linux.org.pl>'s patch to ehance the AVR port.
2000-06-27 01:45:30 +00:00
Nick Clifton
60bcf0fa8c
Applied Stephane Carrez <Stephane.Carrez@worldnet.fr> patches to add support
...
for m68hc11 and m68hc12 processors.
2000-06-19 01:22:44 +00:00
Denis Chertykov
60a2978a70
* avr.h: clr,lsl,rol, ... moved after add,adc, ...
2000-06-09 18:02:05 +00:00
Denis Chertykov
68ab2dd99e
* avr.h: New file with AVR opcodes.
2000-06-07 17:48:35 +00:00
Donald Lindsay
f0662e279c
Define the ALONE flag bit, for use in the opcode table.
2000-05-25 22:23:45 +00:00
Alan Modra
b722f2be22
Allow d suffix on iret
2000-05-23 00:36:39 +00:00
Alan Modra
f9e0cf0b83
Fix fild.
2000-05-17 00:47:51 +00:00
Frank Ch. Eigler
f660ee8b2e
* cgen/opcodes fix
...
* approved by nickc
[opcodes/ChangeLog]
2000-05-16 Frank Ch. Eigler <fche@redhat.com>
* fr30-desc.h: Partially regenerated to account for changed
CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
* m32r-desc.h: Ditto.
[include/opcode/ChangeLog]
2000-05-16 Frank Ch. Eigler <fche@redhat.com>
* cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that
it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set.
(CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds
CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
2000-05-16 19:28:07 +00:00
Alan Modra
558b0a60a8
Fix cpu_flags for sys{enter,exit} fx{save,restore}
2000-05-13 14:01:54 +00:00
Alan Modra
e413e4e996
`.arch cpu_type' pseudo for x86.
2000-05-13 09:26:23 +00:00
Timothy Wall
5c84d377b6
Support for tic54x target.
2000-05-06 17:14:34 +00:00
J.T. Conklin
966f959b21
* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
...
(PPC_OPERAND_VR): New operand flag for vector registers.
2000-05-03 22:19:45 +00:00
Jeff Law
c5d05dbb5e
* h8300.h (EOP): Add missing initializer.
2000-05-01 16:55:50 +00:00
Jeff Law
a7fba0e099
* hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode
...
forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements).
New operand types l,y,&,fe,fE,fx added to support above forms.
(pa_opcodes): Replaced usage of 'x' as source/target for
floating point double-word loads/stores with 'fx'.
Fr
2000-04-21 21:04:04 +00:00
Jim Wilson
800eeca487
IA-64 ELF support.
2000-04-21 20:22:24 +00:00
Nick Clifton
ba23e138c9
Fix value of SHORT_A1.
...
Move SHORT_AR to end of list of short instructions.
2000-03-27 20:17:02 +00:00
Alan Modra
d0b4722035
Mostly cosmetic. Fixes to comments. Don't start as_bad and as_warn
...
messages with capital. Don't malign Unixware, malign SysV386 instead.
2000-03-26 14:13:02 +00:00
Nick Clifton
866afedcb4
Apply patch for 100679
2000-03-02 23:01:40 +00:00
Alan Modra
cc5ca5ce51
Extend the i386 gas testsuite to do some tests for intel_syntax. Fix all
...
the errors exposed by this addition. These were intel mode
"fi... word ptr", "fi... dword ptr", "jmp Imm seg, Imm offset", "out dx,al".
The failure with intel "out dx,al" was also present in att "out al,dx".
Extend testsuite to catch this case too.
2000-02-25 11:41:12 +00:00
Nick Clifton
68e324a2b8
Rename 'flags' to 'signed_overflow_ok_p'
2000-02-24 23:57:23 +00:00
Andrew Haley
60f036a265
2000-02-24 Andrew Haley <aph@cygnus.com>
...
* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
(CGEN_CPU_TABLE): flags: new field.
Add prototypes for new functions.
2000-02-24 21:56:53 +00:00
Alan Modra
9b9b5cd47d
Forgot Changelog for last i386.h change.
2000-02-24 12:41:54 +00:00
Alan Modra
5b93d8bb51
Add IBM 370 support.
2000-02-23 13:52:23 +00:00
Andrew Haley
87f398dd6a
g2000-02-22 Andrew Haley <aph@cygnus.com>
...
* mips.h: (OPCODE_IS_MEMBER): Add comment.
2000-02-22 19:01:25 +00:00
Andrew Haley
9a1e79ca63
ChangeLog change only.
2000-02-22 16:59:39 +00:00
Andrew Haley
367c01aff9
1999-12-30 Andrew Haley <aph@cygnus.com>
...
* mips.h (OPCODE_IS_MEMBER): Add gp32 arg.
2000-02-22 14:39:20 +00:00
Alan Modra
add0c67765
Cosmetic changes to tc-i386.[ch] + extend x86 gas testsuite jmp and
...
call tests + tweak intel mode far call and jmp.
2000-01-15 12:06:03 +00:00
Alan Modra
3138f287b1
x86 indirect jump/call syntax fixes. Disassembly fix for lcall.
1999-12-27 16:10:31 +00:00
Jeff Law
ccecd07b7e
* mn10300.h: Add new operand types. Add new instruction formats.
1999-12-01 10:05:24 +00:00
Jeff Law
b37e19e99a
* hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb"
...
instruction.
1999-11-25 03:28:22 +00:00
Gavin Romig-Koch
5fce5ddfd3
For include/opcode:
...
* mips.h (INSN_ISA5): New.
For opcodes:
* mips-opc.c (I5): New.
(abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s
madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps,
pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
1999-11-18 19:53:48 +00:00
Gavin Romig-Koch
2bd7f1f332
For include/opcode:
...
* mips.h (OPCODE_IS_MEMBER): New.
For gas:
* config/tc-mips.c (macro_build): Use OPCODE_IS_MEMBER.
(mips_ip): Use OPCODE_IS_MEMBER.
For opcodes:
* mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
1999-11-01 19:29:55 +00:00
Nick Clifton
4df2b5c55e
Define SHORT_AR (fix for CR: 101340)
1999-10-29 09:49:04 +00:00
Michael Meissner
446a06c9b8
Add md expression support; Cleanup alpha warnings
1999-10-18 22:29:15 +00:00
Jeff Law
eca04c6a4a
* hppa.h (pa_opcodes): Add load and store cache control to
...
instructions. Add ordered access load and store.
* hppa.h (pa_opcode): Add new entries for addb and addib.
* hppa.h (pa_opcodes): Fix cmpb and cmpib entries.
* hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
1999-10-10 07:55:25 +00:00
Diego Novillo
c43185deeb
Added seven new instructions ld, ld2w, sac, sachi, slae, st and
...
st2w for d10v. Created new testsuite for d10v to verify new
instructions.
1999-10-07 06:17:04 +00:00
Jeff Law
390f858d11
* hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve"
...
and "be" using completer prefixes.
1999-09-23 14:29:10 +00:00
Jeff Law
8c47ebd96b
* hppa.h (pa_opcodes): Add initializers to silence compiler.
1999-09-23 13:14:33 +00:00