Commit Graph

13 Commits

Author SHA1 Message Date
Jan Beulich
b763d508db x86/Intel: correct AVX512 S/G disassembly
Commit 6ff00b5e12 ("x86/Intel: correct permitted operand sizes for
AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn
handling in line with AVX2's, but the disassembler side was forgotten.
This has the benefit of
- allowing to fold a number of table entries,
- rendering a few #define-s and enumerators unused.
2021-03-10 08:20:29 +01:00
Jan Beulich
85ba7507f6 x86: reuse further VEX entries for EVEX
When the VEX.L=1 decode matches that of both EVEX.L'L=1 and EVEX.L'L=2
(typically when all three are invalid) the (smaller) VEX table entry can
be reused by EVEX, instead of duplicating data. (Note that XM and XMM as
well as EXxmm_md and EXd are equivalent at least for the purposes here.)
2021-03-10 08:19:11 +01:00
Jan Beulich
066f82b96a x86: reuse VEX entries for EVEX vperm{q,pd}
By matching VEX decode order (L before W), some EVEX entries can refer
back to VEX ones instead of carrying duplicates.
2021-03-10 08:18:24 +01:00
Jan Beulich
fc681dd6a1 x86: re-arrange order of decode for various EVEX opcodes
The order of decodes influences the overall number of table entries.
Reduce table size quite a bit by first decoding few-alternatives
attributes common to all valid leaves.

This also adds a PREFIX_DATA 7531c61332 ("x86: simplify decode of
opcodes valid with (embedded) 66 prefix only") missed to apply to
vbroadcastf64x4.
2021-03-10 08:16:54 +01:00
Jan Beulich
7531c61332 x86: simplify decode of opcodes valid with (embedded) 66 prefix only
The only valid (embedded or explicit) prefix being the data size one
(which is a fairly common pattern), avoid going through prefix_table[].
Instead extend the "required prefix" logic to also handle PREFIX_DATA
alone in a table entry, now used to identify this case. This requires
moving the (adjusted) ->prefix_requirement logic ahead of the printing
of stray prefixes, as the latter needs to observe the new setting of
PREFIX_DATA in used_prefixes.

Also add PREFIX_OPCODE on related entries when previously there was
mistakenly no decode step through prefix_table[].
2020-07-14 10:33:40 +02:00
Jan Beulich
89e65d17e3 x86: drop Vex128 and Vex256
These are only used when VEX.L or EVEX.L'L have already been decoded,
and hence the "normal" length dependent name determination is quite
fine. Adjust a few enumerators to make clear that vex_len_table[] has
been consulted; be consistent and do so for all *f128 and *i128 insns
in one go.
2020-07-14 10:31:49 +02:00
Jan Beulich
492a76aab5 x86: replace %LW by %DQ
This makes more visible what the two alternatives will be that result
from this macro.
2020-07-14 10:30:26 +02:00
Jan Beulich
bc152a17ff x86: most VBROADCAST{F,I}{32,64}x* only accept memory operands
VBROADCAST{F,I}32x2 are the only exceptions here.
2020-07-06 13:43:34 +02:00
Jan Beulich
c82a99a085 x86: adjust/correct V*{F,I}{32x8,64x4}
For all of these only the 512-bit forms are valid, so drop 256-bit ones
from the integer insert/extract variants.

Also replace EXxmmq by the more natural (here) EXymm.
2020-07-06 13:43:05 +02:00
Jan Beulich
3a57774c7b x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'L
Just like (where they exist) their AVX counterparts do for VEX.L. For
all of them the 128-bit forms are invalid.
2020-07-06 13:41:58 +02:00
Jan Beulich
e74d9fa9cf x86: AVX512 extract/insert insns need to honor EVEX.L'L
Just like their AVX counterparts do for VEX.L.

At this occasion also make EVEX.W have the same effect as VEX.W on the
printing of VPINSR{B,W}'s operands, bringing them also in sync with
VPEXTR{B,W}.
2020-07-06 13:41:27 +02:00
H.J. Lu
e395f487b3 i386: Check vector length for scatter/gather prefetch instructions
Since not all vector lengths are supported by scatter/gather prefetch
instructions, decode them only with supported vector lengths.

gas/

	PR binutils/24719
	* testsuite/gas/i386/disassem.s: Add test for vgatherpf0dps
	with invalid vector length.
	* testsuite/gas/i386/x86-64-disassem.s: Likewise.
	* testsuite/gas/i386/disassem.d: Updated.
	* testsuite/gas/i386/x86-64-disassem.d: Likewise.

opcodes/

	PR binutils/24719
	* i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
	EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
	EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
	EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
	EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
	EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
	EVEX_LEN_0F38C7_R_6_P_2_W_1.
	* i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
	PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
	PREFIX_EVEX_0F38C6_REG_6 entries.
	* i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
	EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
	EVEX_W_0F38C7_R_6_P_2 entries.
	* i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
	EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
	EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
	EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
	EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
	EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
	EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
2019-06-27 13:39:32 -07:00
H.J. Lu
ad692897c1 i386: Break i386-dis-evex.h into small files
Break i386-dis-evex.h into small files such that each file is included
just once.

	* i386-dis-evex.h: Break into ...
	* i386-dis-evex-len.h: New file.
	* i386-dis-evex-mod.h: Likewise.
	* i386-dis-evex-prefix.h: Likewise.
	* i386-dis-evex-reg.h: Likewise.
	* i386-dis-evex-w.h: Likewise.
	* i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
	i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
	i386-dis-evex-mod.h.
2019-06-21 13:18:41 -07:00