This adds another test for file numbers given in .file directives,
checking that the value can be represented as an unsigned int and that
a memory allocation expression doesn't overflow. I removed a test
added recently since an earlier test (num < 1) already covers the
(num < 0) case.
* dwarf2dbg.c: Whitespace fixes.
(get_filenum): Don't strdup "file". Adjust error message.
(dwarf2_directive_filename): Use an unsigned type for "num".
Catch truncation of file number and overflow of get_filenum
XRESIZEVEC multiplication. Delete dead code.
git commit 3076e59490 caused
tic54x-coff +FAIL: c54x subsym assignment/use
PR 24538
* config/tc-tic54x.c (tic54x_start_line_hook): Do skip end of line
chars in setting endp.
PR 24538
gas * macro.c (get_any_string): Increase size of buffer used to hold
decimal value of expression result.
* dw2gencfi.c (get_debugseg_name): Handle an empty name.
* dwarf2dbg.c (get_filenum): Catch integer wraparound when
extending allocate file array.
(dwarf2_directive_filename): Add extra checks of the computed file
number.
* config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into
warning hash table.
(s_arm_eabi_attribute): Check for obj_elf_vendor_attribute
returning -1.
* config/tc-i386.c (i386_output_nops): Catch an attempt to
generate nops of negative lengths.
* as.h (MAX_LITTLENUMS): Move definition to here from...
* config/atof-ieee.c: ...here.
* config/tc-aarch64.c: ...here.
* config/tc-arc.c: ...here.
* config/tc-arm.c: ...here.
* config/tc-epiphany.c: ...here.
* config/tc-i386.c: ...here.
* config/tc-ia64.c: ...here. (And correct the value).
* config/tc-m32c.c: ...here.
* config/tc-m32r.c: ...here.
* config/tc-metag.c: ...here.
* config/tc-microblaze.c: ...here.
* config/tc-nds32.c: ...here.
* config/tc-or1k.c: ...here.
* config/tc-score.c: ...here.
* config/tc-score7.c: ...here.
* config/tc-tic4x.c: ...here.
* config/tc-tilegx.c: ...here.
* config/tc-tilepro.c: ...here.
* config/tc-visium.c: ...here.
* config/tc-sh.c (md_assemble): Add check for an instruction with
no opcodes.
* config/tc-mips.c (mips_lookup_insn): Add check for very short
instruction name.
* config/tc-tic54x.c: Use unsigned chars to access is_end_of_line
array.
(tic54x_start_line_hook): Check for an empty line.
(next_line_shows_parallel): Do not walk off the end of the string.
(tic54x_macro_start): Check for too much macro nesting.
(tic54x_start_label): Add label_start parameter. Use this
parameter to check the first character of the label.
* config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass
line_start variable to tic54x_start_label.
PR 24538
opcodes * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
end of the table prematurely.
Release 6 of the MIPS architecture does not have an ADDI instruction.
ADD/SUB instructions with immediate operands can be expanded to load
and immediate value and then perform the operation.
gas/
* config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>:
Add expansions for MIPS r6.
* testsuite/gas/mips/add.s: Enable tests for R6.
* testsuite/gas/mips/daddi.s: Annotate to test DADD for R6.
* testsuite/gas/mips/mipsr6@add.d: Likewise.
* gas/testsuite/gas/mips/mipsr6@dadd.d: New test.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
opcodes/
* mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
macros for R6.
opcodes/
* ppc-dis.c (skip_optional_operands): Change return type and returns.
(print_insn_powerpc) <skip_optional>: Change type.
Call skip_optional_operands if we have not skipped any operands.
gas/
* testsuite/gas/ppc/476.d: Update expected output.
* testsuite/gas/ppc/power6.d: Likewise.
My testcase matched against a file format of elf64-littleaarch64 in the
objdump output. This was unnecessarily restrictive and causes testcase
failures on aarch64_be.
Here we remove that restriction.
Committed as obvious.
Testing done on aarch64_be-none-elf gas to see the failure goes away.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/sve2.d: Remove file format restriction.
Add tests that SVE2 instructions are encoded as they should be, and
tests that invalid instructions have their problems reported.
Also check that each sve2 cryptographic extension is required to use the
corresponding cryptographic instructions.
Finally, test to ensure that sve2 instructions using mnemonics that
exist in sve1 still need the sve2 feature to be used.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: New test.
* testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test.
* testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.l: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.s: Test new instructions.
* testsuite/gas/aarch64/sve1-extended-sve2.s: New test.
* testsuite/gas/aarch64/sve2.d: Test new instructions.
* testsuite/gas/aarch64/sve2.s: Test new instructions.
New operand describes a shift-left immediate encoded in bits
22:20-19:18-16 where UInt(bits) - esize == shift.
This operand is useful for instructions like sshllb.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHLIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
operand.
This includes defining a new single bit field SVE_i2h at position 20.
SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded
in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm4_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
(fields): Handle SVE_i2h field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
Include a new iclass to extract the variant from the most significant 3
bits of this operand.
Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.
The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
operand.
(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-asm.c (aarch64_ins_sve_shrimm):
(aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass decode.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHRIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
operand.
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses
in a Zn register, offset by an Xm register.
This is used with scatter/gather SVE2 instructions.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
(parse_address_main): Account for new addressing mode [Zn.S, Xm].
(parse_operands): Handle new SVE_ADDR_ZX operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_ADDR_ZX.
(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between
z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm3_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
(fields): Handle SVE_i3l and SVE_i3h2 fields.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
fields.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate
operand encoded at bit position 10.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_IMM_ROT3.
(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
(fields): Handle SVE_rot3 field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
Make them work for tile, by using ".quad 0" as the simulated
instruction and doubling size of aligns. The larger aligns tripped
over riscv alignment handling, fixed by adding -mno-relax there.
Also disable link-relax for avr, pru and xtensa, allowing these
targets to pass these tests. With link-time relaxation enabled,
these targets emit alignment relocations rather than aligning at
assembly time. This means the assembler doesn't see a change in PC
when it is expected over an alignment frag and thus view numbers are
calculated incorrectly.
* testsuite/gas/elf/dwarf2-1.s,
* testsuite/gas/elf/dwarf2-2.s,
* testsuite/gas/elf/dwarf2-5.s,
* testsuite/gas/elf/dwarf2-7.s,
* testsuite/gas/elf/dwarf2-8.s,
* testsuite/gas/elf/dwarf2-9.s,
* testsuite/gas/elf/dwarf2-10.s,
* testsuite/gas/elf/dwarf2-11.s,
* testsuite/gas/elf/dwarf2-12.s,
* testsuite/gas/elf/dwarf2-13.s,
* testsuite/gas/elf/dwarf2-14.s,
* testsuite/gas/elf/dwarf2-15.s,
* testsuite/gas/elf/dwarf2-16.s,
* testsuite/gas/elf/dwarf2-17.s,
* testsuite/gas/elf/dwarf2-18.s,
* testsuite/gas/elf/dwarf2-19.s: Double size of align and simulated
instructions.
* testsuite/gas/elf/dwarf2-1.d,
* testsuite/gas/elf/dwarf2-2.d,
* testsuite/gas/elf/dwarf2-5.d,
* testsuite/gas/elf/dwarf2-7.d,
* testsuite/gas/elf/dwarf2-8.d,
* testsuite/gas/elf/dwarf2-9.d,
* testsuite/gas/elf/dwarf2-10.d,
* testsuite/gas/elf/dwarf2-11.d,
* testsuite/gas/elf/dwarf2-12.d,
* testsuite/gas/elf/dwarf2-13.d,
* testsuite/gas/elf/dwarf2-14.d,
* testsuite/gas/elf/dwarf2-15.d,
* testsuite/gas/elf/dwarf2-16.d,
* testsuite/gas/elf/dwarf2-17.d,
* testsuite/gas/elf/dwarf2-18.d,
* testsuite/gas/elf/dwarf2-19.d: Use xfail rather than notarget.
Remove avr, pru, tile, xtensa from xfails. Update expected output.
* testsuite/gas/elf/elf.exp: Sort targets.
(dump_opts): Pass {as -mno-relax} for riscv, {as -mno-link-relax}
for avr and pru, and {as --no-link-relax} for xtensa to dwarf tests.
* testsuite/gas/elf/section2.e-miwmmxt: Delete unused file.
md_begin happens after md_parse_option.
* config/tc-xtensa.c (opt_linkrelax): New variable.
(md_parse_option): Set it here.
(md_begin): Copy opt_linkrelax to linkrelax.
Expressions that compute view numbers that aren't simplified early
enough to a constant end up being selected for representation as
complex relocations, enabled on mep-* targets.
It would be possible to recognize such expressions, that can resolve
to constants, but this problem was hit before, in preexisting tests,
so xfail the new hits similarly.
The new hits were caused by yesterday's patch to dwarf2dbg.c: views in
the beginning of subsections are now computed later, based on the
final views or previous subsections in the same section.
for gas/ChangeLog
* testsuite/gas/elf/dwarf2-18.d: Xfail mep-*.
* testsuite/gas/elf/dwarf2-19.d: Likewise.
Since I was looking at this I decided to fix the formatting, and
used an old C switch statements trick to factor out common code.
* symbols.c (use_complex_relocs_for): Formatting. Factor out
X_add_symbol tests.
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1]. These instructions are optional within
the EVA ASE. Their presence is indicated by the XNP bit in the
Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 230-231, pp. 357-360.
gas/
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
include/
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
GOT and PLT relocs shouldn't have their symbols replaced with a
section symbol plus added. Nor should the HIGHA TLS relocations,
which failed to be caught by the range test in ppc_fix_adjustable.
bfd/
* reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA),
(BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA):
Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry.
gas/
* config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT
relocs, and VLE sdarel relocs.
* testsuite/gas/ppc/power4.d: Adjust.
Location views at borders between subsegments/subsections in the same
segment/section are computed as if each new subsegment/subsection
started with a forced view reset to zero, but the line number program
does not introduce resets that are not explicitly requested, so if a
subsegment ends at the same address another starts, the line number
program will have a continuity of views at the border address, whereas
the initial view number label in the latter subsegment will be
miscomputed as zero.
This patch delays the assignment of view expressions at subsegment
heads to the time of chaining the frags of subsegments into a single
segment, so that they are set based on the view at the end of the
previous subsegment in the same segment.
The line number program created for the test program had an
unnecessary DW_LNS_advance_pc at the end. This patch also arranges
for us not to emit it.
for gas/ChangeLog
* dwarf2dbg.c (set_or_check_view): Skip heads when assigning
views of prior locs.
(dwarf2_gen_line_info_1): Skip heads.
(size_inc_line_addr, emit_inc_line_addr): Drop
DW_LNS_advance_pc for zero addr delta.
(dwarf2_finish): Assign views for heads of segments.
* testsuite/gas/elf/dwarf2-19.d: New.
* testsuite/gas/elf/dwarf2-19.s: New.
* testsuite/gas/elf/elf.exp: Test it.
m32c_md_end attempted to pad out a code section with nops, but this
was just plain wrong in many ways:
- The padding didn't happen at all if the last section emitted wasn't
a code section.
- The padding went to the wrong place if subsections were used, and
the last subseg used wasn't the highest numbered subseg.
- Padding wasn't added to all code sections.
- If the last section was empty, it was padded to 4 bytes.
- The padding didn't go to a 4-byte alignment boundary, instead it
effectively made the last instruction 4 bytes in size.
- The padding didn't take into account that code sections may have
contents other than machine instructions.
So, rip it out and handle nop padding properly, also fixing .align
.balign/.p2align in the middle of code.
gas/
* config/tc-m32c.c (insn_size): Delete static var.
(md_begin): Don't set it.
(m32c_md_end): Delete.
(md_assemble): Add insn_size auto var.
* config/tc-m32c.h (md_end): Don't define.
(m32c_md_end): Delete.
(NOP_OPCODE, HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): Define.
* testsuite/gas/all/align.d: Remove m32c from notarget list.
* testsuite/gas/all/incbin.d: Likewise.
* testsuite/gas/elf/dwarf2-11.d: Likewise.
* testsuite/gas/macros/semi.d: Likewise.
* testsuite/gas/all/gas.exp (do_comment): Similarly.
ld/
* testsuite/ld-scripts/fill.d: Don't xfail m32c
* testsuite/ld-scripts/fill16.d: Likewise.
The .code16gcc directive to support 16-bit mode with 32-bit address.
For IRET without a suffix, generate 16-bit IRET with a warning to
return from an interrupt handler in 16-bit mode.
PR gas/24485
* config/tc-i386.c (process_suffix): Issue a warning to IRET
without a suffix for .code16gcc.
* testsuite/gas/i386/jump16.s: Add tests for iretX.
* testsuite/gas/i386/jump16.d: Updated.
* testsuite/gas/i386/jump16.e: New file.
This patch enables the new Transactional Memory Extension added recently
as part of Arm's new architecture technologies.
We introduce a new optional extension "tme" to enable this. The following
instructions are part of the extension:
* tstart <Xt>
* ttest <Xt>
* tcommit
* tcancel #<imm>
The ISA for the above can be found here:
https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order
*** gas/ChangeLog ***
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add case for
AARCH64_OPND_TME_UIMM16.
(aarch64_features): Add "tme".
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/tme-invalid.d: New test.
* testsuite/gas/aarch64/tme-invalid.l: New test.
* testsuite/gas/aarch64/tme-invalid.s: New test.
* testsuite/gas/aarch64/tme.d: New test.
* testsuite/gas/aarch64/tme.s: New test.
*** include/ChangeLog ***
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_TME): New.
(enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
*** opcodes/ChangeLog ***
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
AARCH64_OPND_TME_UIMM16.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_IMM_NIL): New.
(TME): New.
(_TME_INSN): New.
(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions
that were omitted from the initial spec. These instructions
are optional in implementations but not associated with any
ASE or pseudo-ASE. Their presence is indicated by the XNP bit
in the Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 228-229, pp. 354-357.
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 289-290 and pp. 458-460.
gas/
* config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB,
M_SCDP_AB>: New cases and expansions for paired instructions.
* testsuite/gas/mips/llpscp-32.s: New test source.
* testsuite/gas/mips/llpscp-64.s: Likewise.
* testsuite/gas/mips/llpscp-32.d: New test.
* testsuite/gas/mips/llpscp-64.d: Likewise.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/r6.s: Add new instructions to test source.
* testsuite/gas/mips/r6-64.s: Likewise.
* testsuite/gas/mips/r6-64-n32.d: Check new instructions.
* testsuite/gas/mips/r6-64-n64.d: Likewise.
* testsuite/gas/mips/r6-n32.d: Likewise.
* testsuite/gas/mips/r6-n64.d: Likwwise.
* testsuite/gas/mips/r6.d: Likewise.
include/
* opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
(M_SCWP_AB, M_SCDP_AB): Likewise.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
The .code16gcc directive supports 16bit mode with 32-bit address. Since
IRET (opcode 0xcf) in 16bit mode returns from an interrupt in 16bit mode,
we shouldn't add 0x66 prefix for IRET.
PR gas/24485
* config/tc-i386.c (process_suffix): Don't add DATA_PREFIX_OPCODE
to IRET for .code16gcc.
* testsuite/gas/i386/jump16.s: Add IRET tests.
* testsuite/gas/i386/jump16.d: Updated.
Targets such as xtensa incur a much higher overhead to resolve
location view numbers than e.g. x86, because the expressions used to
compute view numbers cannot be resolved soon enough.
Each view number is computed by incrementing the previous view, if
they are both at the same address, or by resetting it to zero
otherwise. If PV is the previous view number, PL is its location, and
NL is the location of the next view, its number is computed by
evaluating NV = !(NL > PL) * (PV + 1).
set_or_check_view uses resolve_expression to decide whether portions
of this expression can be simplified to constants. The (NL > PL)
subexpression is one that can often be resolved to a constant,
breaking chains of view number computations at instructions of nonzero
length, but not after alignment that might be unnecessary.
Alas, when nearly every frag ends with a relaxable instruction,
frag_offset_fixed_p will correctly fail to determine a known offset
between two unresolved addresses in neighboring frags, so the
unresolved symbolic operation will be constructed and used in the
computation of most view numbers. This results in very deep
expressions.
As view numbers get referenced in location view lists, each operand in
the list goes through symbol_clone_if_forward_ref, which recurses on
every subexpression. If each view number were to be referenced, this
would exhibit O(n^2) behavior, where n is the depth of the view number
expressions, i.e., the length of view number sequences without an
early resolution that cuts the expression short.
This patch enables address compares used by view numbering to be
resolved even when exact offsets are not known, using new logic to
determine when the location either remained the same or changed for
sure, even with the possibility of relaxation. This enables most view
number expressions to be resolved with a small, reasonable depth.
PR gas/24444
* frags.c (frag_gtoffset_p): New.
* frags.h (frag_gtoffset_p): Declare it.
* expr.c (resolve_expression): Use it.
In most cases we don't want expression symbols, such as that created
for an expression like "symbol + (1f - .)", resolved down to a
constant. Instead we'd like to leave the expression as "symbol +
constant" once the "1f - ." part has been resolved, and let the
backend decide whether "symbol" can be reduced further.
However, that doesn't work when trying to resolve .loc view symbols
early. We get expression symbols left as an O_symbol expression
pointing at an absolute symbol, and marked as sy_flags.sy_resolved.
That wouldn't really be a problem, but when one of those expression
symbols is used in further .loc view expressions, its value is taken
as zero.
This patch fixes the symbol value mistake, and stops creation of
O_symbol expression symbols pointing to absolute symbols. Either of
these fixes would cure the .loc view usage.
PR 24444
* symbols.c (resolve_symbol_value): When handling symbols
marked as sy_flags.resolved, return correct value for the
case of expression symbols left as an O_symbol expression.
Merge O_symbol code handling undefined and common symbols with
code handling special cases of expression symbols. Use
seg_left to test for undefined and common symbols. Don't
leave an O_symbol expression when X_add_symbol resolves to
the absolute_section. Init final_val later.
* testsuite/gas/mmix/basep-7.d: Adjust expected output.
PR 24464
* config/tc-rx.h (md_relax_frag): Pass the max_iterations variable
to the relaxation function.
* config/tc-rx.c (rx_relax_frag): Add new parameter - the maximum
number of iterations. Make sure that our internal iteration limit
does not exceed this external iteration limit.
gas * config/tc-msp430.c (msp430_make_init_symbols): Define
__crt0_run_{preinit,init,fini}_array symbols if
.{preinit,init,fini}_array sections exist.
* testsuite/gas/msp430/fini-array.d: New test.
* testsuite/gas/msp430/init-array.d: New test.
* testsuite/gas/msp430/preinit-array.d: New test.
* testsuite/gas/msp430/fini-array.s: New test source.
* testsuite/gas/msp430/init-array.s: New test source.
* testsuite/gas/msp430/preinit-array.s: New test source.
* testsuite/gas/msp430/msp430.exp: Add new tests to driver.
* config/tc-msp430.c (msp430_make_init_symbols): Define __crt0_init_bss
symbol when .lower.bss or .either.bss sections exist.
Define __crt0_movedata when .lower.data or .either.data sections exist.
* testsuite/gas/msp430/either-data-bss-sym.d: New test.
* testsuite/gas/msp430/low-data-bss-sym.d: New test.
* testsuite/gas/msp430/either-data-bss-sym.s: New test source.
* testsuite/gas/msp430/low-data-bss-sym.s: New test source.
* testsuite/gas/msp430/msp430.exp: Run new tests.
Enable large code model when running -mdata-region={upper,either}
tests.
gas * config/tc-msp430.c (options): New OPTION_UNKNOWN_INTR_NOPS,
OPTION_NO_UNKNOWN_INTR_NOPS and do_unknown_interrupt_nops.
(md_parse_option): Handle OPTION_UNKNOWN_INTR_NOPS and
OPTION_NO_UNKNOWN_INTR_NOPS by setting do_unknown_interrupt_nops
accordingly.
(md_show_usage): Likewise.
(md_shortopts): Add "mu" for OPTION_UNKNOWN_INTR_NOPS and
"mU" for OPTION_NO_UNKNOWN_INTR_NOPS.
(md_longopts): Likewise.
(warn_eint_nop): Update comment.
(warn_unsure_interrupt): Don't warn if prev_insn_is_nop or
prev_insn_is_dint or we are assembling for 430 ISA.
(msp430_operands): Only call warn_unsure_interrupt if
do_unknown_interrupt_nops == TRUE.
* testsuite/gas/msp430/nop-unknown-intr.s: New test source file.
* testsuite/gas/msp430/nop-unknown-intr-430.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430x.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430x-ignore.d: New test.
* testsuite/gas/msp430/nop-unknown-intr-430.l: Warning output for new
test.
* testsuite/gas/msp430/nop-unknown-intr-430x.l: Likewise.
* testsuite/gas/msp430/msp430.exp: Add new tests to driver.
Some of these tests were excluded for ns32k-netbsd, exclude for all
ns32k instead.
binutils/
* testsuite/binutils-all/copy-2.d: Don't run for ns32k-*-*.
* testsuite/binutils-all/copy-3.d: Likewise.
gas/
* testsuite/gas/all/gas.exp: Remove ns32k xfails.
* testsuite/gas/all/weakref1u.d: Don't run for ns32k-*-*.
ld/
* testsuite/ld-scripts/pr20302.d: Don't run for ns32k-*-*.
* testsuite/ld-scripts/section-match-1.d: Likewise.
* testsuite/ld-undefined/require-defined.exp: Likewise.
These are only used by dlx and ns32k.
* write.h: Don't include bit_fix.h.
(struct fix): Rearrange some fields. Delete fx_im_disp and
fx_bit_fixP. Use bitfields for fx_size and fx_pcrel_adjust.
* write.c (fix_new_internal): Don't init fx_im_disp and fx_bit_fixP.
(fixup_segment): Don't exclude overflow checks on fx_bit_fixP.
(print_fixup): Don't print im_disp.
* config/tc-cris.c (md_apply_fix): Remove tests of fx_bit_fixP
and fx_im_disp.
* config/tc-dlx.c (md_apply_fix): Remove wrong debug code. Set
fx_no_overflow when fx_bit_fixP.
* config/tc-dlx.h: Include bit_fix.h.
(TC_FIX_TYPE, tc_fix_data, TC_INIT_FIX_DATA): Define.
* config/tc-ns32k.c (fix_new_ns32k, fix_new_ns32k_exp): Set
fx_no_overflow when bit_fixP.
* config/tc-ns32k.h (TC_FIX_TYPE): Add fx_bit_fixP and fx_im_disp.
(fix_im_disp, fix_bit_fixP): Adjust to suit.
(TC_INIT_FIX_DATA, TC_FIX_DATA_PRINT): Likewise.
GNU as' Arm backend assumes each mnemonic has a single entry in the instruction table but VLDR (system register) and VSTR (system register) are different instructions than VLDR and VSTR. It is thus necessary to add some form of demultiplexing in the parser. It starts by creating a new operand type OP_VLDR which indicate that the operand is either the existing OP_RVSD operand or a system register. The function parse_operands () then tries these two cases in order, calling the new parse_sys_vldr_vstr for the second case.
Since the encoding function is specified in the instruction table entry, it also need to have some sort of demultiplexing. This is done in do_vldr_vstr which either calls the existing do_neon_ldr_str () or calls the new do_t_vldr_vstr_sysreg ().
A new internal relocation is needed as well since the offset has a shorter range than in other Thumb coprocessor instructions. Disassembly also requires special care since VSTR (system register) reuse the STC encoding with the coprocessor number 15. Armv8.1-M Mainline ARM manual states that coprocessor 8, 14 and 15 are reserved for floating-point and MVE instructions a feature bit check is added if the coprocessor number is one of this value and we are trying to match a coprocessor instruction (eg. STC) to forbid the match.
ChangeLog entries are as follows:
*** bfd/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* reloc.c (BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM): New internal
relocation.
* bfd-in2.h: Regenerate.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_sys_vldr_vstr): New function.
(OP_VLDR): New enum operand_parse_code enumerator.
(parse_operands): Add logic for OP_VLDR.
(do_t_vldr_vstr_sysreg): New function.
(do_vldr_vstr): Likewise.
(insns): Guard VLDR and VSTR by arm_ext_v4t for Thumb mode.
(md_apply_fix): Add bound check for VLDR and VSTR co-processor offset.
Add masking logic for BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM relocation.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add examples of bad
uses of VLDR and VSTR.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error messages for
above bad uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add examples of VLDR and
VSTR valid uses.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add disassembly for the
above examples.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
specifier. Add entries for VLDR and VSTR of system registers.
(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
coprocessor instructions on Armv8.1-M Mainline targets. Add handling
of %J and %K format specifier.
Like for CLRM, this patch aims to share as much logic with the similar looking VLDM/VSTM. This is achieved by adding 2 new enumerator values in enum reg_list_els for the single-precision and double-precision variants of VSCCLRM and extending parse_vfp_reg_list () to deal with these types.
These behave like the existing REGLIST_VFP_S and REGLIST_VFP_D types with extra logic to expect VPR as the last element in the register list.
The function is algo augmented with a new partial_match parameter to indicate if any register other than VPR had already been parsed in the register list so as to not try parsing the second variant if that's the case and return the right error message.
The rest of the patch is the usual encoding function, new disassembler table entries and format specifier and parsing, encoding and disassembling tests.
It is worth mentioning that the new entry in the disassembler table was added in the coprocessor-related table despite VSCCLRM always being available even in FPU-less configurations. The main reason for this is that VSCCLRM also match VLDMIA entry and must thus be tried first but coprocessor entries are tried before T32 entries. It also makes sense because it is in the same encoding space as coprocessor and VFP instructions and is thus the natural place for someone to look for this instruction.
Note: Both variants of VSCCLRM support D16-D31 registers but Armv8.1-M Mainline overall does not. I have thus decided not to implement support for these registers in order to keep the code simpler. It can always be added later if needed.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_typed_reg_parse): Fix typo in comment.
(enum reg_list_els): New REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
enumerators.
(parse_vfp_reg_list): Add new partial_match parameter. Set
*partial_match to TRUE if at least one element in the register list has
matched. Add support for REGLIST_VFP_S_VPR and REGLIST_VFP_D_VPR
register lists which expect VPR as last element in the list.
(s_arm_unwind_save_vfp_armv6): Adapt call to parse_vfp_reg_list to new
prototype.
(s_arm_unwind_save_vfp): Likewise.
(enum operand_parse_code): New OP_VRSDVLST enumerator.
(parse_operands): Adapt call to parse_vfp_reg_list to new prototype.
Handle new OP_VRSDVLST case.
(do_t_vscclrm): New function.
(insns): New entry for VSCCLRM instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Add invalid VSCCLRM
instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Add error expectations
for above instructions.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Add tests for VSCCLRM
instruction.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Add expected disassembly
for above instructions.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
Add new entries for VSCCLRM instruction.
(print_insn_coprocessor): Handle new %C format control code.
Given the similarity between LDM/STM and CLRM register lists, most of the changes in this patch aim at sharing code between those two sets of instruction. Sharing is achieved both in parsing and encoding of those instructions.
In terms of parsing, parse_reg_list () is extended to take a type that describe what type of instruction is being parsed. The reg_list_els used for parse_vfp_reg_list () is reused for the type and that function is added an assert for the new REGLIST_CLRM and REGLIST_RN enumerators.
parse_reg_list () is then taught to accept APSR and reject SP and PC when parsing for a CLRM instruction. At last, caller of parse_reg_list () is updated accordingly and logic is added for the new OP_CLRMLST operand.
Encoding-wise, encode_thumb2_ldmstm () is reused to encode the variable bits of CLRM and is thus renamed encode_thumb2_multi (). A new do_io parameter is added to distinguish between LDM/STM and CLRM which guard all the LDM/STM specific code of the function.
Finally objdump is told how to disassemble CLRM, again reusing the logic to print the LDM/STM register list (format specifier 'm'). Tests are also added in the form of negative tests to check parsing and encoding/disassembling tests.
ChangeLog entries are as follows:
*** gas/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (enum reg_list_els): Define earlier and add
REGLIST_RN and REGLIST_CLRM enumerators.
(parse_reg_list): Add etype parameter to distinguish between regular
core register list and CLRM register list. Add logic to
recognize CLRM register list.
(parse_vfp_reg_list): Assert type is not for core register list.
(s_arm_unwind_save_core): Update call to parse_reg_list to new
prototype.
(enum operand_parse_code): Declare OP_CLRMLST enumerator.
(parse_operands): Update call to parse_reg_list to new prototype. Add
logic for OP_CLRMLST.
(encode_thumb2_ldmstm): Rename into ...
(encode_thumb2_multi): This. Add do_io parameter. Add logic to
encode CLRM and guard LDM/STM only code by do_io.
(do_t_ldmstm): Adapt to use encode_thumb2_multi.
(do_t_push_pop): Likewise.
(do_t_clrm): New function.
(insns): Define CLRM.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.d: New file.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.l: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main-bad.s: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.d: Likewise.
* testsuite/gas/arm/archv8m_1m-cmse-main.s: Likewise.
*** opcodes/ChangeLog ***
2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
CLRM.
(print_insn_thumb32): Add logic to print %n CLRM register list.
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds support to the Scalar low overhead loop instructions:
LE
WLS
DLS
We also add a new assembler resolvable relocation bfd_reloc_code_real enum for the 12-bit branch offset used in these instructions.
ChangeLog entries are as follows:
*** bfd/ChnageLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_LOOP12): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
*** gas/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (operand_parse_code): Add OP_LR and OP_oLR
for the LR operand and optional LR operand.
(parse_operands): Add switch cases for OP_LR and OP_oLR for
both type checking and value checking.
(encode_thumb32_addr_mode): New entries for DLS, WLS and LE.
(v8_1_loop_reloc): New helper function for handling labels
for the low overhead loop instructions.
(do_t_loloop): New function to encode DLS, WLS and LE.
(insns): New entries for WLS, DLS and LE.
(md_pcrel_from_section): New switch case
for BFD_RELOC_ARM_THUMB_LOOP12.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-tloop.s: New.
* testsuite/gas/arm/armv8_1-m-tloop.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.s: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.d: New.
* testsuite/gas/arm/armv8_1-m-tloop-bad.l: New.
*** opcodes/ChangeLog ***
2019-04-12 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %P
and %Q patterns.
s patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils.
This patch adds the BFCSEL instruction. It also adds a local relocation with a new bfd_reloc_code_real enum.
ChangeLog entries are as follows:
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_THUMB_PCREL_BFCSEL): New relocation.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
*** gas/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (T16_32_TAB): New entriy for bfcsel.
(do_t_v8_1_branch): New switch case for bfcsel.
(toU): Define.
(insns): New instruction for bfcsel.
(md_pcrel_from_section): New switch case
for BFD_RELOC_THUMB_PCREL_BFCSEL.
(md_appdy_fix): Likewise
(tc_gen_reloc): Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: New.
* testsuite/gas/arm/armv8_1-m-bfcsel.s: New.
*** ld/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* testsuite/ld-arm/bfcsel.s: New.
* testsuite/ld-arm/bfcsel.d: New.
* testsuite/ld-arm/arm-elf.exp: Add above test.
*** opcodes/ChangeLog ***
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
(print_insn_thumb32): Edit the switch case for %Z.
This patch is part of a series of patches to add support for Armv8.1-M Mainline
instructions to binutils.
This adds infrastructure for the BFCSEL instructions which is one of the first
instructions in Arm that have more than one relocations in them.
This adds a new relocation R_ARM_THM_BF12.
The inconsistency between external R_ARM_THM_BF12 and internal
BFD_RELOC_ARM_THUMB_BF13 is because internally we count the static bit-0 of the
immediate and we don't externally.
ChangeLog entries are as follows :
ChangeLog entries are as follows :
*** bfd/ChnageLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* reloc.c (BFD_RELOC_ARM_THUMB_BF13): New.
* bfd-in2.h: Regenerated.
* libbfd.h: Regenerated.
* elf32-arm.c (elf32_arm_howto_table_1): New entry for R_ARM_THM_BF13.
(elf32_arm_reloc_map elf32_arm_reloc_map): Map BFD_RELOC_ARM_THUMB_BF13
and R_ARM_THM_BF12 together.
(elf32_arm_final_link_relocate): New switch case for R_ARM_THM_BF13.
*** elfcpp/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm.h (R_ARM_THM_BF12): New relocation code.
*** gas/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (md_pcrel_from_section): New switch case for
BFD_RELOC_ARM_THUMB_BF13.
(md_appdy_fix): Likewise.
(tc_gen_reloc): Likewise.
*** include/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
*** opcodes/ChangeLog ***
2019-04-04 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
