Add arches CK804, CK805 and CK800. CK800 is an special arch which
support all instructions for CSKYV2. Refine the cpu tables to
simplify adding a new cpu.
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (struct csky_cpu_info): Add new members
isa_flag, features and ver.
(struct csky_cpu_feature): New.
(struct csky_cpu_version): New.
(CSKY_FEATURE_MAX): Define.
(CSKY_CPU_REVERISON_MAX): Define.
(FEATURE_DSP_EXT, FEATURE_DSP, FEATURE_MMU, FEATURE_VDSP,
FEATURE_FLOAT, FEATURE_TRUST, FEATURE_JAVA, FEATURE_SHIELD):
Define, each standard one collection of instructions.
(CSKY_FEATURES_DEF_NULL, CSKY_FEATURES_DEF_e,
CSKY_FEATURES_DEF_t, CSKY_FEATURES_DEF_f, CSKY_FEATURES_DEF_v,
CSKY_FEATURES_DEF_ef, CSKY_FEATURES_DEF_jt,
CSKY_FEATURES_DEF_efht, CSKY_FEATURES_DEF_efv,
CSKY_FEATURES_DEF_eft, CSKY_FEATURES_DEF_d,
CSKY_FEATURES_DEF_df, CSKY_FEATURES_DEF_ft,
CSKY_FEATURES_DEF_tv, CSKY_FEATURES_DEF_fv,
CSKY_FEATURES_DEF_dft, CSKY_FEATURES_DEF_dfv,
CSKY_FEATURES_DEF_ftv, CSKY_FEATURES_DEF_eftv): Define,
the features combination used by cpu.
(CSKY_CPU_REVERISON_r0p0, CSKY_CPU_REVERISON_r1p0,
CSKY_CPU_REVERISON_r2p0, CSKY_CPU_REVERISON_r3p0,
CSKY_CPU_REVERISON_RESERVED, CSKY_CPU_REVERISON_R3):
Define, version information used by cpu.
(csky_cpus): Refine, and add CK804, CK805 and CK800.
(parse_cpu): Refine.
(parse_arch): Refine.
(md_show_usage): Refine.
(md_begin): Refine.
include/
* opcode/csky.h (CSKY_ARCH_804): Define.
(CSKY_ARCH_805): Define.
(CSKY_ARCH_800): Define.
We don't support power10 on ppc32, mainly because some instructions
have 34-bit fields for which we don't have relocations on ppc32.
If you try to assemble typical code, you'll see errors saying
"reloc ... not supported by object file format". Also, on 32-bit
hosts with binutils configured without a 64-bit bfd, you'll see errors
saying "bignum invalid" when using large offsets. But let's not kill
output of prefix insns entirely on 32-bit hosts.
* config/tc-ppc.c (md_assemble): Emit prefix insn by parts when
valueT is smaller than 64 bits.
The option corresponds to GCC to control the float calling conversion,
and the value will be stored in .csky.attributes section.
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (float_abi): New.
(md_longopts): Add mfloat-abi.
(struct sky_option_value_table): New.
(csky_float_abis): New, the possible values for -mfloat-abi.
(parse_float_abi): New funtion.
(md_show_usage): Show help information for -mfloat-abi.
(set_csky_attribute): Store float-abi value.
Link-time relaxations of branches are common for MSP430, given that GCC
can generate pessimal branch instructions, and the
-mcode-region=either/-mdata-region=either options to shuffle sections
can further change the type of branch instruction required.
These relaxations can result in invalid code when .uleb128
directives, used in the .gcc_except_table section, are used to calculate
the distance between two labels. A value for the .uleb128 directive is
calculated at assembly-time, and can't be updated at link-time, even if
relaxation causes the distance between the labels to change.
This patch adds relocations for subtract expressions in .uleb128
directives, to allow the linker to re-calculate the value of these
expressions after relaxation has been performed.
bfd/ChangeLog:
* bfd-in2.h (bfd_reloc_code_real): Add
BFD_RELOC_MSP430_{SET,SUB}_ULEB128.
* elf32-msp430.c (msp430_elf_ignore_reloc): New.
(elf_msp430_howto_table): Add R_MSP430{,X}_GNU_{SET,SUB}_ULEB128.
(msp430_reloc_map): Add R_MSP430_GNU_{SET,SUB}_ULEB128.
(msp430x_reloc_map): Add R_MSP430X_GNU_{SET,SUB}_ULEB128.
(write_uleb128): New.
(msp430_final_link_relocate): Handle R_MSP430{,X}_GNU_{SET,SUB}_ULEB128.
* libbfd.c (_bfd_write_unsigned_leb128): New.
* libbfd.h (_bfd_write_unsigned_leb128): New prototype.
Add BFD_RELOC_MSP430_{SET,SUB}_ULEB128.
* reloc.c: Document BFD_RELOC_MSP430_{SET,SUB}_ULEB128.
binutils/ChangeLog:
* readelf.c (target_specific_reloc_handling): Handle
R_MSP430{,X}_GNU_{SET,SUB}_ULEB128.
gas/ChangeLog:
* config/tc-msp430.c (msp430_insert_uleb128_fixes): New.
(msp430_md_end): Call msp430_insert_uleb128_fixes.
include/ChangeLog:
* elf/msp430.h (elf_msp430_reloc_type): Add
R_MSP430_GNU_{SET,SUB}_ULEB128.
(elf_msp430x_reloc_type): Add R_MSP430X_GNU_{SET,SUB}_ULEB128.
ld/ChangeLog:
* testsuite/ld-msp430-elf/msp430-elf.exp: Run new tests.
* testsuite/ld-msp430-elf/uleb128.s: New test.
* testsuite/ld-msp430-elf/uleb128_430.d: New test.
* testsuite/ld-msp430-elf/uleb128_430x.d: New test.
This adds support for the Arm Cortex-R82 CPU in AArch64 GAS. For more
information about this processor, see [0].
[0] : https://developer.arm.com/ip-products/processors/cortex-r/cortex-r82
gas/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add Cortex-R82.
* doc/c-aarch64.texi: Document -mcpu=cortex-r82.
This patch adds support for the system registers introduced in Armv8-R
AArch64.
gas/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to
validation function.
(parse_sys_ins_reg): Likewise.
(print_operands): Pass CPU features to aarch64_print_operand().
* testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test.
* testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output.
* testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input.
* testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test.
* testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output.
* testsuite/gas/aarch64/v8-r-sysregs.d: New test.
* testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests.
include/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (aarch64_sys_ins_reg_supported_p): Also take
system register name in order to simplify validation for v8-R.
(aarch64_print_operand): Also take CPU feature set, as disassembly for
system registers now depends on arch variant.
opcodes/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* aarch64-dis.c (print_operands): Pass CPU features to
aarch64_print_operand().
* aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
preferred disassembly of system registers.
(SR_RNG): Refactor to use new SR_FEAT2 macro.
(SR_FEAT2): New.
(SR_V8_1_A): New.
(SR_V8_4_A): New.
(SR_V8_A): New.
(SR_V8_R): New.
(SR_EXPAND_ELx): New.
(SR_EXPAND_EL12): New.
(aarch64_sys_regs): Specify which registers are only on
A-profile, add R-profile system registers.
(ENC_BARLAR): New.
(PRBARn_ELx): New.
(PRLARn_ELx): New.
(aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
Armv8-R AArch64.
This patch adds the basic infrastructure needed to support Armv8-R in
AArch64 binutils: new command-line flags, new feature bits, a new BFD
architecture, and support for differentiating between architecture
variants in the disassembler.
The new command-line options added by this patch are -march=armv8-r in
GAS and -m aarch64:armv8-r in objdump.
The disassembler support is necessary since Armv8-R AArch64 introduces a
system register (VSCTLR_EL2) which shares an encoding with a different
system register (TTBR0_EL2) in Armv8-A. This also allows us to use the
correct preferred disassembly for the new DFB alias introduced in
Armv8-R.
bfd/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* archures.c (bfd_mach_aarch64_8R): New.
* bfd-in2.h: Regenerate.
* cpu-aarch64.c (bfd_aarch64_arch_v8_r): New.
(bfd_aarch64_arch_ilp32): Update tail pointer.
gas/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (aarch64_archs): Add armv8-r.
* doc/c-aarch64.texi: Document -march=armv8-r.
include/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_A): New.
(AARCH64_FEATURE_V8_R): New.
(AARCH64_ARCH_V8): Include new A-profile feature bit.
(AARCH64_ARCH_V8_R): New.
opcodes/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* aarch64-dis.c (arch_variant): New.
(determine_disassembling_preference): Disassemble according to
arch variant.
(select_aarch64_variant): New.
(print_insn_aarch64): Set feature set.
If bfd_vma is 32 bits, gcc complains about shift counts exceeding
width of the type.
* config/tc-pdp11.c (md_number_to_chars): Condition nbytes=8 code
on BFD64.
Move divul and divsl to CSKYV2_ISA_3E3R3 instruction set, which is
enabled by ck803r3, and it's still a part of enhance DSP instruction
set.
gas/
* config/tc-csky.c (csky_cpus): Add ck803r3.
(CSKY_ISA_803R3): Define.
(CSKY_ISA_803R2): Refine, use CSKY_ISA_803R1.
include/
* opcode/csky.h (CSKYV2_ISA_3E3R3): Define.
opcodes/
* csky-opc.h (csky_v2_opcodes): Move divul and divsl
to CSKYV2_ISA_3E3R3 instruction set.
PR 26420
PR 26421
PR 26425
PR 26427
* config/tc-arm.c (struct arm_it): Make size, size_req, cond and
uncond_value unsigned.
(parse_vfp_reg_list): Make setmask unsigned, vpr_str_len size_t.
(parse_big_immediate): Cast generic_bignum elements to unsigned.
(encode_thumb32_immediate): Shift left 0xffU.
(double_to_single): Make sign unsigned. Tidy.
(move_or_literal_pool): Cast LITTLE_NUM elements to uint64_t or
valueT.
(vfp_or_neon_is_neon): Adjust inst.uncond_value expression.
(md_assemble): Likewise.
(handle_pred_state): Make cond unsigned.
(thumb32_negate_data_op): Make variables unsigned.
(md_apply_fix): Make value and newval unsigned, adjust uses.
This also fixes the packing of the nibble buffer, which contains
rubbish in the top 4 bits of each element.
PR 26510
* config/tc-z8k.c (buffer): Use unsigned char.
(apply_fix): Use unsigned char* pointers.
(build_bytes): Likewise and mask nibbles when packing.
Always use unsigned constants in expressions generating masks. The
following trys mightily to avoid UB (but hits it anyway with bits=32
and 0x7fffffff << 1), and worse, for 32-bit int, 64-bit long, bits=32
doesn't generate 0xffffffff.
max = ((((1 << (bits - 1)) - 1) << 1) | 1);
results in -1, or max = 0xffffffffffffffff.
This patch fixes that problem, a possible shift exponent of -1U,
removes some dead code, and makes general tidies.
PR26437
PR26438
* config/tc-cr16.c: Include limits.h, formatting.
(CR16_PRINT): Wrap params in parentheses. Remove parens from uses
throughout file.
(getconstant): Handle zero nbits.
(print_operand): Simplify handling of index regs.
(check_range): Use int32_t variables. Correct range checks.
This patch adds support for xBPF, another ISA targetting the BPF
virtual architecture. For now, the primary difference between eBPF
and xBPF is that xBPF supports indirect calls through the
'call %reg' form of the call instruction.
bfd/
* archures.c (bfd_mach_xbpf): Define.
* bfd-in2.h: Regenerate.
* cpu-bpf.c (bfd_xbpf_arch) New.
(bfd_bpf_arch) Update next in list field to point to xbpf arch.
cpu/
* bpf.cpu (arch bpf): Add xbpf mach and isas.
(define-xbpf-isa) New pmacro.
(all-isas) Add xbpfle,xbpfbe.
(endian-isas): New pmacro.
(mach xbpf): New.
(model xbpf-def): Likewise.
(h-gpr): Add xbpf mach.
(f-dstle, f-srcle, dstle, srcle): Add xbpfle isa.
(f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa.
(define-alu-insn-un): Use new endian-isas pmacro.
(define-alu-insn-bin, define-alu-insn-mov): Likewise.
(define-endian-insn, define-lddw): Likewise.
(dlind, dxli, dxsi, dsti): Likewise.
(define-cond-jump-insn, define-call-insn): Likewise.
(define-atomic-insns): Likewise.
gas/
* config/tc-bpf.c: Add option -mxbpf to select xbpf isa.
* testsuite/gas/bpf/indcall-1.d: New file.
* testsuite/gas/bpf/indcall-1.s: Likewise.
* testsuite/gas/bpf/indcall-bad-1.l: Likewise.
* testsuite/gas/bpf/indcall-bad-1.s: Likewise.
* testsuite/gas/bpf/bpf.exp: Run new tests.
opcodes/
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-opc.h: Likewise.
* disassemble.c (disassemble_init_for_target): Set bits for xBPF
ISA when appropriate.
Some versions of gcc with -Werror=format-overflow complain about using
a perfectly good 7 char buffer for "r%dr%d" when the int is between 0
and 64, apparently not seeing the value range.
note: __builtin___sprintf_chk output between 5 and 24 bytes into a destination of size 7
* config/tc-arc.c (declare_register_set): Avoid false positive
format-overflow warning.
* config/tc-epiphany.c (md_assemble): Likewise.
* config/tc-mips.c (md_begin): Likewise.
* config/tc-mmix.c (mmix_md_begin): Likewise.
* config/tc-nds32.c (nds32_elf_append_relax_relocs): Avoid false
positive "may be used uninitialized" warning.
A number of the tic54x tests were failing, and I thought it worth
investigating since the target makes use of a lot of hash tables, and
we've just changed gas hash tables. It turns out none of the gas
failures were due to hashing.
* config/tc-tic54x.c (stag_add_field_symbols): Don't free "name"
in case where it isn't copied.
* config/tc-tic54x.h (LOCAL_LABELS_FB): Undef.
* testsuite/gas/tic54x/field.d: Dump section contents and symbols
rather than disassembling.
* testsuite/gas/tic54x/set.d: Adjust for newer disassembly.
Get rid of sy_ prefix, and some unused fields.
* symbols.c (struct symbol_flags): Rename sy_volatile to volatil,
and remove sy_ from other field names. Update throughout.
(struct symbol): Remove sy_ from field names. Delete unused
TARGET_SYMBOL_FIELDS. Update throughout file. Move after..
(struct local_symbol): ..here. Remove lsy_ from field names.
Delete unused TC_LOCAL_SYMFIELD_TYPE. Update throughout file.
(local_symbol_resolved_p, local_symbol_mark_resolved): Delete.
Expand uses throughout file.
(local_symbol_get_frag, local_symbol_set_frag): Likewise.
(symbol_new): Move symbol_table_frozen test to..
(symbol_append): ..here, and..
(symbol_insert): ..here.
(resolve_symbol_value, symbol_relc_make_expr): White space fixes.
(HANDLE_XADD_OPT1, HANDLE_XADD_OPT2): Likewise.
* config/obj-coff.h (RESOLVE_SYMBOL_REDEFINITION): Update.
gas/
* config/tc-csky.c (csky_insn_info): Add member last_isize.
(md_assemble): Assign value to csky_insn.last_isize.
* testsuite/gas/csky/enhance_dsp.d: Test bloop's two operands form.
* testsuite/gas/csky/enhance_dsp.s: Likewise.
opcodes/
* csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
This patch fixes an internal error in GAS when defining a section using
a symbol that has already been named but not defined. For a minimal
reproducer, try the following input:
a=b
.sect a
The problem is that obj_elf_change_section() happily reuses the symbol
"a" created by equals() without clearing the sy_value field: prior to
this patch, it just set bsym. This caused a problem when attempting to
resolve the section symbol, since resolve_symbol_value() ended up
resolving the symbol as if it were the original symbol created by
equals(), which ends up leaving the section symbol in the undefined
section instead of in section a, hence the call to abort() in
S_SET_SEGMENT().
gas/ChangeLog:
* config/obj-elf.c (obj_elf_change_section): When repurposing an
existing symbol, ensure that we set sy_value as per other (fresh)
section symbols.
* testsuite/gas/elf/elf.exp: Add new test.
* testsuite/gas/elf/section-symbol-redef.d: New test.
* testsuite/gas/elf/section-symbol-redef.s: Input for test.
* config/tc-arm.c (do_neon_cvt_1): Parse vcvtne as vcvt-ne for
NS_FD shape when MVE is present
* testsuite/gas/arm/mve-vcvtne-it-bad.d: New test.
* testsuite/gas/arm/mve-vcvtne-it-bad.l: New test.
* testsuite/gas/arm/mve-vcvtne-it-bad.s: New test.
* testsuite/gas/arm/mve-vcvtne-it.d: New test.
* testsuite/gas/arm/mve-vcvtne-it.s: New test.
This patch fixes an assertion failure on long system register operands
in the AArch64 backend. See the new testcase for an input which
reproduces the issue.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sys_reg): Don't assert when parsing
a long system register.
(parse_sys_ins_reg): Likewise.
(sysreg_hash_insert): New.
(md_begin): Use sysreg_hash_insert() to ensure all system
registers are no longer than the maximum length at startup.
* testsuite/gas/aarch64/invalid-sysreg-assert.d: New test.
* testsuite/gas/aarch64/invalid-sysreg-assert.l: Error output.
* testsuite/gas/aarch64/invalid-sysreg-assert.s: Input.
include/ChangeLog:
* opcode/aarch64.h (AARCH64_MAX_SYSREG_NAME_LEN): New.
The MSP430 GAS option "-md" is supposed to indicate that the CRT startup
code should copy data from ROM to RAM at startup. However, this option
has no effect; GAS handles the related behaviour automatically by
looking for the presence of certain symbols in the input file.
gas/ChangeLog:
* config/tc-msp430.c (OPTION_MOVE_DATA): Remove.
(md_parse_option): Remove case for OPTION_MOVE_DATA.
(md_longopts): Remove "md" entry.
(md_show_usage): Likewise.
Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use
disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}.
Note: Since there is no disp32 on 0(%bp), use disp16 instead.
PR gas/26305
* config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on
(%bp)/(%ebp)/(%rbp) for {disp32}.
* doc/c-i386.texi: Update {disp32} documentation.
* testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests.
* testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests.
* testsuite/gas/i386/pseudos.d: Updated.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
Ever since commit 4d7206a284 ("Rework MIPS macro relaxation, fix string
merging bug"), <https://sourceware.org/ml/binutils/2004-01/msg00248.html>,
`prev_reloc_op_frag' has only been set and never used. Remove it then.
gas/
* config/tc-mips.c (prev_reloc_op_frag): Remove variable.
(my_getSmallExpression): Adjust accordingly.
PR gas/4572
When / is a comment character, its use as binary "divide" operator needs
escaping by a backslash. Besides the scrubber needing to support this
(addressed in an earlier change), there are also a few provisions needed
in target specific operator handling.
As the spec calls for % and * to also be escaped because of being
"overloaded", also recognize these, despite the overloading there not
really preventing their use as operators in most (%) or all (*) cases,
given the way how the rest of the assembler works.
To bring source and testsuite in line, also drop the TE_I386AIX part of
the respective conditional, as i?86-*-aix* support had been removed a
while ago.
Various provisions exist for insns to be placed in the absolute section,
yet actually trying to do so didn't work. While data emission (of non-
zero values) is not allowed by generic code, I think this functionality
is useful for the programmer to be able to determine the size of insns.
Therefore, rather than turning the silnet failure into a verbose one,
make things mostly work; the one class of insns not supported (yet) are
branches (JMP and Jcc) with dynamically determined displacement widths.
In this one case, an error now gets reported instead of silently
ignoring the code.
Also avoid recording ISA / feature usage for insns emitted to the
absolute section.
When encoding a 32-bit offset, there is no need to sign-extend it to 64
bits since only the lower 32 bits are used.
* config/tc-i386.c (offset_in_range): Remove 32-bit sign
extension.
Extract extended states from operand types in instruction template. Set
xstate_zmm for master register move.
* config/tc-i386.c (_i386_insn): Remove has_regmmx, has_regxmm,
has_regymm, has_regzmm and has_regtmm. Add xstate.
(md_assemble): Set i.xstate from operand types in instruction
template.
(build_modrm_byte): Updated.
(output_insn): Check i.xstate.
* testsuite/gas/i386/i386.exp: Run property-6 and
x86-64-property-6.
* testsuite/gas/i386/property-6.d: New file.
* testsuite/gas/i386/property-6.s: Updated.
* testsuite/gas/i386/x86-64-property-6.d: Likewise.
Since VEX/EVEX vector instructions will always update the full YMM/ZMM
registers, set YMM/ZMM features for VEX/EVEX vector instructions.
* config/tc-i386.c (output_insn): Set YMM/ZMM features for
VEX/EVEX vector instructions.
* testsuite/gas/i386/property-4.d: New file.
* testsuite/gas/i386/property-4.s: Likewise.
* testsuite/gas/i386/property-5.d: Likewise.
* testsuite/gas/i386/property-5.s: Likewise.
* testsuite/gas/i386/x86-64-property-4.d: Likewise.
* testsuite/gas/i386/x86-64-property-5.d: Likewise.
We check register-only source operand to decide if two source operands of
VEX encoded instructions should be swapped. But source operands in AMX
instructions with two source operands swapped are all register-only
operand. Add SwapSources to indicate two source operands should be
swapped.
gas/
* config/tc-i386.c (build_modrm_byte): Check vexswapsources to
swap two source operands.
opcodes/
* i386-gen.c (opcode_modifiers): Add VexSwapSources.
* i386-opc.h (VexSwapSources): New.
(i386_opcode_modifier): Add vexswapsources.
* i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
with two source operands swapped.
* i386-tbl.h: Regenerated.
This patch fixes a segfault which occurs when the AArch64 backend parses
a symbol operand that begins with a register name and ends with a
unicode byte (byte value > 127).
For example, the following input causes the crash:
x0é: udf x0é
gas/ChangeLog:
2020-07-02 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (reg_name_p): Fix cast so that we don't
segfault on negative chars.
* testsuite/gas/aarch64/reglike-label-unicode-segv.d: New test.
* testsuite/gas/aarch64/reglike-label-unicode-segv.s: Input.
The xc16x md_apply_fix code is just so broken that in my opinion the
target should never have been accepted, and from a quick look at
commit logs for the target it appears that no one has ever contributed
fixes for anything. This target has just been a 14 year burden on
global binutils and cgen maintainers. That's not how free software is
supposed to work.
bfd/
* config.bfd: Obsolete xc16x.
gas/
* config/tc-xc16x.c (md_apply_fix): Add FIXME.
The unprivileged CSR should be controlled by other specific specs rather
than the privileged spec. For example, the debug CSR should be controlled
by the debug spec, and the float CSR should be controlled by the float
spec. User may use assembler options to choose what the debug and other
specs they want, or may encode the versions of specs into the architecture
string directly. Since we haven't decided which one is better, we set the
defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE
in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec
versions for them. However, these PRIV_SPEC_CLASS_NONE will be changed
to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future.
gas/
* config/tc-riscv.c (riscv_csr_class_check): Removed. Move the
checking into riscv_csr_address.
(riscv_csr_version_check): Likewise.
(riscv_csr_address): New function. Return the suitable CSR address
after checking the ISA dependency and versions. Issue warnings if
we find any conflict and -mcsr-check is set. CSR_CLASS_F and
CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
priv spec versions for them.
(reg_csr_lookup_internal): Call riscv_csr_address to find the
suitable CSR address.
* testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the
priv spec warnings here. These warnings are added by accident.
Remove them and only focus on the ISA dependency warnings.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
than the privileged ones.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR.
* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
include/
* opcode/riscv-opc.h: Support the unprivileged CSR. The versions
of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now.
* opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG.
opcodes/
* riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
unprivileged CSR can also be initialized.
Finally; sorry for the delay. There were a few false starts, where I
misinterpreted the error-messages and the comment that Alan added:
it's not the fix size that's too large (and the frag too small), it's
stating the wrong size of what will be "fixed up" - that of the actual
target value, not the size of the field that needs to be adjusted.
Comments added for clarity.
Test-suite committed separately.
gas:
PR gas/25331
* config/tc-mmix.c (md_assemble) <fixup for
BFD_RELOC_MMIX_BASE_PLUS_OFFSET>: This fixup affects 1 byte, not 8.
Also, set its fx_no_overflow.
(md_convert_frag) <case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO)>:
Similarly this fixup affects 4 bytes, not 8 and needs its
fx_no_overflow set.
* config/tc-mmix.h (TC_FX_SIZE_SLACK): Don't define.
To support Intel AMX instructions with 8-bit immediate opcode extension,
but without operands:
tilerelease, 0, 0x49, 0xc0, 1, CpuAMX_TILE|Cpu64, Vex|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
process ImmExt without operands.
* config/tc-i386.c (md_assemble): Process ImmExt without
operands.
Rename VecSIB to SIB to support Intel Advanced Matrix Extensions which
introduces instructions with a mandatory SIB byte which isn't a vector
SIB (VSIB).
gas/
* config/tc-i386.c (check_VecOperands): Replace vecsib with sib.
Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128,
VECSIB256 and VECSIB512, respectively.
(build_modrm_byte): Replace vecsib with sib.
opcodes/
* i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
(VecSIB128): Renamed to ...
(VECSIB128): This.
(VecSIB256): Renamed to ...
(VECSIB256): This.
(VecSIB512): Renamed to ...
(VECSIB512): This.
(VecSIB): Renamed to ...
(SIB): This.
(i386_opcode_modifier): Replace vecsib with sib.
* i386-opc.tbl (VexSIB128): New.
(VecSIB256): Likewise.
(VecSIB512): Likewise.
Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VexSIB128, VecSIB256
and VecSIB512, respectively.
This patch adds GNU attribute support to m68k and utilises it to tag the
floating-point calling convention used (hard-float or soft-float). It enables
the linker to ensure linked objects use a consistent floating-point ABI and
allows tools like GDB to infer the ABI used from the ELF file. It is based on
similar work done for PowerPC.
bfd/
* elf32-m68k.c (m68k_elf_merge_obj_attributes): New function.
(elf32_m68k_merge_private_bfd_data): Merge GNU attributes.
binutils/
* readelf.c (display_m68k_gnu_attribute): New function.
(process_arch_specific): Call display_m68k_gnu_attribute for EM_68K.
gas/
* config/tc-m68k.c (m68k_elf_gnu_attribute): New function.
(md_pseudo_table): Handle "gnu_attribute".
* doc/as.texi: Document GNU attribute for M68K.
include/
* elf/m68k.h: Add enum for GNU object attribute with floating point
tag name and values.
ld/
* testsuite/ld-m68k/attr-gnu-4-0.s: New file.
* testsuite/ld-m68k/attr-gnu-4-1.s: Likewise.
* testsuite/ld-m68k/attr-gnu-4-2.s: Likewise.
* testsuite/ld-m68k/attr-gnu-4-00.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-01.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-02.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-10.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-11.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-12.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-20.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-21.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-22.d: Likewise.
* testsuite/ld-m68k/m68k.exp: Run the new tests.
With abuses of ImmExt gone, all templates using it have operands. Move
its main invocation into process_operands(), matching its secondary one
for the SSE2AVX case.
Use of an explicit data size or REX.W prefix is sufficient indication of
the intended operation when operand size can't be derived from suffix or
register operands. Avoid the ambiguity warning and make in particular
immediate handling (sizing) cope with explicitly specified prefixes.
Extending/reusing the noreg16 test made me notice a few cases of
unintentional 32-bit addressing, which gets corrected at the same time.
Just like for the data size prefix (see commit 7a8655d2bb ["x86: don't
abort() upon DATA16 prefix on (E)VEX encoded insn"]), any form of REX
prefix is invalid with VEX/XOP/EVEX.
Legacy encoded insns do so, and their automatic conversion to AVX ones
ought to produce functionally identical code. Therefore explicit REX
prefixes cannot simply be ignored. This is in particular relevant
because at least PCMPESTR{I,M}'s 64-bit forms couldn't be expressed in
older gas by other than using a REX64 prefix.
