Commit Graph

10180 Commits

Author SHA1 Message Date
Tsukasa OI
7379729c7d RISC-V: Reorganize testcases for CFI directives
This commit reorganizes and adds some CSRs to csr-dw-regnums.[sd] to
make it test the same CSRs as csr.s.

gas/ChangeLog:

	* testsuite/gas/riscv/csr-dw-regnums.s: Reorganize and add
	defined CSRs tested in csr.s.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
2022-02-23 14:45:34 +08:00
Alan Modra
19f7966ede gas local label and dollar label handling
Much of the gas source and older BFD source use "long" for function
parameters and variables, when other types would be more appropriate.
This patch fixes one of those cases.  Dollar labels and numeric local
labels do not need large numbers.  Small positive itegers are usually
all that is required.  Due to allowing longs, it was possible for
fb_label_name and dollar_label_name to overflow their buffers.

	* symbols.c: Delete unnecessary forward declarations.
	(dollar_labels, dollar_label_instances): Use unsigned int.
	(dollar_label_defined, dollar_label_instance): Likewise.
	(define_dollar_label): Likewise.
	(fb_low_counter, fb_labels, fb_label_instances): Likewise.
	(fb_label_instance_inc, fb_label_instance): Likewise.
	(fb_label_count, fb_label_max): Make them size_t.
	(dollar_label_name, fb_label_name): Rewrite using sprintf.
	* symbols.h (dollar_label_defined): Update prototype.
	(define_dollar_label, dollar_label_name): Likewise.
	(fb_label_instance_inc, fb_label_name): Likewise.
	* config/bfin-lex.l (yylex): Remove unnecessary casts.
	* expr.c (integer_constant): Likewise.
	* read.c (read_a_source_file): Limit numeric label range to int.
2022-02-16 22:05:24 +10:30
Alan Modra
969f6a63c0 ubsan: s_app_line integer overflow
There are quite a few ubsan warnings in gas.  This one disappears with
a code tidy.

	* read.c (s_app_line): Rename 'l' to 'linenum'.  Avoid ubsan
	warning.
2022-02-16 22:05:24 +10:30
Alan Modra
d12b8d620c asan : use of uninitialized value in buffer_and_nest
* macro.c (buffer_and_nest): Don't read past end of string buffer.
2022-02-16 19:15:40 +10:30
Richard Sandiford
b4b0dcfd03 gas/doc: Fix "a true results" typo 2022-02-11 15:08:46 +00:00
Nick Clifton
2f49159cfb Updated French translation for the gas sub-directory. 2022-01-28 12:16:03 +00:00
Mike Frysinger
9a84a44d5d gas: drop old cygnus install hack
This was needed when gas was using the automake cygnus option, but
this was removed years ago by Simon in d0ac1c4488
("Bump to autoconf 2.69 and automake 1.15.1").  So delete it here.
The info pages are already & still installed by default w/out it.
2022-01-24 19:58:33 -05:00
Nick Clifton
5fe73d4624 Update Bulgarian, French, Romaniam and Ukranian translation for some of the sub-directories 2022-01-24 14:22:49 +00:00
H.J. Lu
ad69b6b861 Regenerate Makefile.in files with automake 1.15.1
Regenerate Makefile.in files with the unmodified automake 1.15.1 to
remove

runstatedir = @runstatedir@

bfd/

	* Makefile.in: Regenerate.

binutils/

	* Makefile.in: Regenerate.

gas/

	* Makefile.in: Regenerate.

gold/

	* Makefile.in: Regenerate.
	* testsuite/Makefile.in: Likewise.

gprof/

	* Makefile.in: Regenerate.

ld/

	* Makefile.in: Regenerate.

opcodes/

	* Makefile.in: Regenerate.
2022-01-23 06:59:20 -08:00
H.J. Lu
31b0378d53 Regenerate configure files with autoconf 2.69
Regenerate configure files with the unmodified autoconf 2.69 to remove

  --runstatedir=DIR       modifiable per-process data [LOCALSTATEDIR/run]

bfd/

	* configure: Regenerate.

binutils/

	* configure: Regenerate.

gas/

	* configure: Regenerate.

gold/

	* configure: Regenerate.

gprof/

	* configure: Regenerate.

ld/

	* configure: Regenerate.

opcodes/

	* configure: Regenerate.
2022-01-23 05:27:01 -08:00
Nick Clifton
f908e960c5 Change version number to 2.38.50 and regenerate files 2022-01-22 12:39:28 +00:00
Nick Clifton
a74e1cb344 Add markers for 2.38 branch 2022-01-22 12:08:55 +00:00
Lifang Xia
cb2562f553 RISC-V: create new frag after alignment.
PR 28793:

The alignment may be removed in linker. We need to create new frag after
alignment to prevent the assembler from computing static offsets.

gas/
	* config/tc-riscv.c (riscv_frag_align_code): Create new frag.
2022-01-22 17:20:18 +08:00
Mike Frysinger
ec7194506d drop old unused stamp-h.in file
This was needed by ancient versions of automake, but that hasn't been
the case since at least automake-1.5, so punt this from the tree.
2022-01-21 03:11:47 -05:00
Nick Clifton
6c037fdbf0 Update the config.guess and config.sub files from the master repository and regenerate files. 2022-01-17 16:21:22 +00:00
Sergey Belyashov
1adce770ea Fix Z80 assembly failure.
PR 28762
	* app.c (do_scrub_chars): Correct handling when the symbol is not 'af'.
2022-01-17 13:00:17 +00:00
Alan Modra
1ffce3f87d Re: gas: add visibility support using GNU syntax on XCOFF
tc-ppc.c: In function 'ppc_comm':
tc-ppc.c:4560:40: error: 'visibility' may be used uninitialized in this function [-Werror=maybe-uninitialized]

With that fixed we hit lots of segfaults in the ld testsuite.

	PR 22085
bfd/
	* xcofflink.c (xcoff_link_input_bfd): Don't segfault on NULL
	sym_hash.
gas/
	* config/tc-ppc.c (ppc_comm): Init visibility.
2022-01-13 16:50:15 +10:30
Clément Chigot
09d4578fd9 gas: add visibility support using GNU syntax on XCOFF
In order to ease port of GNU assembly code and especially ld testsuite,
this patch allows XCOFF to accept the usual GNU syntax for visibility.

PR 22085

gas/ChangeLog:

	* config/tc-ppc.c (ppc_GNU_visibility): New function.
	* testsuite/gas/ppc/aix.exp: Add new tests.
	* testsuite/gas/ppc/xcoff-visibility-2-32.d: New test.
	* testsuite/gas/ppc/xcoff-visibility-2-64.d: New test.
	* testsuite/gas/ppc/xcoff-visibility-2.s: New test.
2022-01-12 09:08:17 +01:00
Clément Chigot
add588a8ef gas: add visibility support for XCOFF
XCOFF assembly defines the visibility using an additional argument
on several pseudo-ops: .globl, .weak, .extern and .comm.
This implies that .globl and .weak syntax is different than the
usual GNU syntax. But we want to provide compatibility with AIX
assembler, especially because GCC is generating the visibility
using this XCOFF syntax.

PR 22085

bfd/ChangeLog:

        * coffcode.h (coff_write_object_contents): Change XCOFF header
        vstamp field to 2.
        * coffgen.c (coff_print_symbol): Increase the size for n_type.

gas/ChangeLog:

        * config/tc-ppc.c (ppc_xcoff_get_visibility): New function.
        (ppc_globl): New function.
        (ppc_weak): New function.
        (ppc_comm): Add visibility field support.
        (ppc_extern): Likewise.
        * testsuite/gas/all/cofftag.d: Adjust to new n_type size
        providing by objdump.
        * testsuite/gas/ppc/test1xcoff32.d: Likewise.
        * testsuite/gas/ppc/aix.exp: Add new tests.
        * testsuite/gas/ppc/xcoff-visibility-1-32.d: New test.
        * testsuite/gas/ppc/xcoff-visibility-1-64.d: New test.
        * testsuite/gas/ppc/xcoff-visibility-1.s: New test.

include/ChangeLog:

        * coff/internal.h (SYM_V_INTERNAL, SYM_V_HIDDEN,
        SYM_V_PROTECTED, SYM_V_EXPORTED, SYM_V_MASK): New defines.
        * coff/xcoff.h (struct xcoff_link_hash_entry): Add visibility
        field.

ld/ChangeLog:

        * testsuite/ld-pe/pr19803.d: Adjust to new n_type size
        providing by objdump.
2022-01-12 09:08:11 +01:00
Hans-Peter Nilsson
c4f5871457 objdump, readelf: Emit "CU:" format only when wide output is requested
As pre-approved by Alan in
https://sourceware.org/pipermail/binutils/2021-September/118019.html
and I believe people have run into getting testsuite failures for
test-environments with "long" directory names, at least once more
since that time.  Enough.  I grepped the gas, binutils and ld
testsuites for "CU:" to catch target-specific occurrences, but I
noticed none.  I chose to remove "CU:" on the objdump tests instead of
changing options to get the wide format, so as to keep the name of the
test consistent with actual options; but added it to the readelf
options for the gas test as I believe the "CU:" format is preferable.

Tested for cris-elf and native x86_64-pc-linux-gnu.

binutils:
	* dwarf.c (display_debug_lines_decoded): Don't check the
	string length of the directory, instead emit the "CU: dir/name"
	format only if wide output is requested.
	* testsuite/binutils-all/dw5.W, testsuite/binutils-all/objdump.WL:
	Adjust accordingly.

gas:
	* testsuite/gas/elf/dwarf-5-loc0.d: Add -W to readelf options.
2022-01-12 05:51:25 +01:00
Jan Beulich
d02f2788c3 gas/doc: mention quoted symbol names 2022-01-11 15:43:34 +01:00
Clément Chigot
3c5038247c XCOFF: add support for TLS relocations on hidden symbols
This patch adds support for TLS relocation targeting C_HIDEXT symbols.
In gas, TLS relocations, except R_TLSM and R_TLMSL, must keep the value
of their target symbol.
In ld, it simply ensures that internal TLS symbols are added to the
linker hash table for xcoff_reloc_type_tls.

It also improves the tests made by both.

bfd/ChangeLog:

	* coff-rs6000.c (xcoff_howto_table): Fix name of R_TLSML.
	(xcoff_reloc_type_tls): Replace the error when h is NULL by
	an assert.
	(xcoff_complain_overflow_unsigned_func): Adjust comments.
	* coff64-rs6000.c (xcoff64_howto_table): Fix name of R_TLSML.
	* xcofflink.c (xcoff_link_add_symbols_to_hash_table): New
	function.
	(xcoff_link_add_symbols): Add C_HIDEXT TLS symbols to the linker
	hash table.

gas/ChangeLog:

	* config/tc-ppc.c (md_apply_fix): Enable support for TLS
	relocation over internal symbols.
	* testsuite/gas/ppc/aix.exp: Replace xcoff-tlms by xcoff-tls.
	* testsuite/gas/ppc/xcoff-tlsm-32.d: Removed.
	* testsuite/gas/ppc/xcoff-tlsm-64.d: Removed.
	* testsuite/gas/ppc/xcoff-tlsm.s: Removed.
	* testsuite/gas/ppc/xcoff-tls-32.d: New test.
	* testsuite/gas/ppc/xcoff-tls-64.d: New test.
	* testsuite/gas/ppc/xcoff-tls.s: New test.

ld/ChangeLog:

	* testsuite/ld-powerpc/aix52.exp: Improve aix-tls-reloc test.
	* testsuite/ld-powerpc/aix-tls-reloc.s: Likewise.
	* testsuite/ld-powerpc/aix-tls-reloc-32.d: Removed.
	* testsuite/ld-powerpc/aix-tls-reloc-64.d: Removed.
	* testsuite/ld-powerpc/aix-tls-reloc-32.dd: New test.
	* testsuite/ld-powerpc/aix-tls-reloc-32.dt: New test.
	* testsuite/ld-powerpc/aix-tls-reloc-64.dd: New test.
	* testsuite/ld-powerpc/aix-tls-reloc-64.dt: New test.
2022-01-10 09:14:57 +01:00
Philipp Tomsich
9fba072133 RISC-V: update docs to reflect privileged spec v1.9 has been dropped
After commit d8af286fff ("RISC-V: Drop the privileged spec v1.9
support.") has removed support for privileged spec v1.9, this removes
it from the documentation.

References: d8af286fff ("RISC-V: Drop the privileged spec v1.9 support.")

gas/ChangeLog:

	* configure: Regenerate.
	* configure.ac: Remove reference to priv spec 1.9.
	* po/fr.po: Same.
	* po/ru.po: Same.
	* po/uk.po: Same.
2022-01-07 23:41:25 +01:00
Philipp Tomsich
86d39e66f5 RISC-V: update docs for -mpriv-spec/--with-priv-spec for 1.12
While support for the privileged spec was added in a63375ac33
("RISC-V: Hypervisor ext: support Privileged Spec 1.12"), the
documentation has not been updated.  Add 1.12 to the relevant
documentation.

References: a63375ac33 ("RISC-V: Hypervisor ext: support Privileged Spec 1.12")

gas/ChangeLog:

	* config/tc-riscv.c: Add 1.12 to the usage message.
	* configure: Regenerate.
	* configure.ac: Add 1.12 to the help/usage message.
	* po/fr.po: Same.
	* po/ru.po: Same.
	* po/uk.po: Same.
2022-01-07 23:40:30 +01:00
Nelson Chu
aed44286ef RISC-V: Updated the default ISA spec to 20191213.
Update the default ISA spec from 2.2 to 20191213 will change the default
version of i from 2.0 to 2.1.  Since zicsr and zifencei are separated
from i 2.1, users need to add them in the architecture string if they need
fence.i and csr instructions.  Besides, we also allow old ISA spec can
recognize zicsr and zifencei, but we won't output them since they are
already included in the i extension when i's version is less than 2.1.

bfd/
	* elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can
	recognize zicsr and zifencei.
gas/
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213.
	* testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1.
	* testsuite/gas/riscv/option-arch-03.s: Likewise.
ld/
	* testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Added zifencei
	into Tag_RISCV_arch since it is added implied when i's version is
	larger than 2.1.
2022-01-07 18:48:29 +08:00
Richard Sandiford
27297937e0 aarch64: Add support for new SME instructions
This patch adds support for three new SME instructions: ADDSPL,
ADDSVL and RDSVL.  They behave like ADDPL, ADDVL and RDVL, but read
the streaming vector length instead of the current vector length.

opcodes/
	* aarch64-tbl.h (aarch64_opcode_table): Add ADDSPL, ADDSVL and RDSVL.
	* aarch64-dis-2.c: Regenerate.

gas/
	* testsuite/gas/aarch64/sme.s, testsuite/gas/aarch64/sme.d: Add tests
	for ADDSPL, ADDSVL and RDSVL.
2022-01-06 16:22:54 +00:00
Jan Beulich
ffb864501e x86: drop NoAVX insn attribute
To avoid issues like that addressed by 6e3e5c9e41 ("x86: extend SSE
check to PCLMULQDQ, AES, and GFNI insns"), base the check on opcode
attributes and operand types.
2022-01-06 14:19:56 +01:00
Jan Beulich
1ef3994a37 x86-64: restrict PC32 -> PLT32 conversion
Neither non-64-bit code nor uses with a non-zero offset from a symbol
should be converted to PLT32, as an eventual PLT entry would not express
what was requested.
2022-01-06 14:17:40 +01:00
Alan Modra
1037150181 Adjust quoted-sym-names test
Some targets restrict symbol addresses in .text to instruction
boundaries.

	* testsuite/gas/all/quoted-sym-names.s: Define syms in .data.
	* testsuite/gas/all/quoted-sym-names.d: Adjust to suit.
2022-01-05 20:04:28 +10:30
Jan Beulich
125ff8197d x86/Intel: correct VFPCLASSP{S,D} handling when displacement is present
fits_in_disp8() can be called before ambiguous operands get resolved
or rejected (in process_suffix()), which requires that i.memshift be
non-negative to avoid an internal error. This case wasn't covered by
6c0946d0d2 ("x86: correct VFPCLASSP{S,D} operand size handling").
2022-01-04 10:05:53 +01:00
Jan Beulich
5ed4d49d10 gas: rework handling of backslashes in quoted symbol names
Strange effects can result from the present handling, e.g.:

.if 1
"backslash\\":
.endif

yields first (correctly) "missing closing `"'" but then also "invalid
character '\' in mnemonic" and further "end of file inside conditional".
Symbols names ending in \ are in principle not expressable with that
scheme.

Instead of recording whether a backslash was seen, inspect the
subsequent character right away. Only accept \\ (meaning a single
backslash in the resulting symbol name) and \" (meaning an embedded
double quote in the resulting symbol name) for now, warning about any
other combination.

While perhaps not necessary immediately, also permit concatenated
strings to form a symbol name. This may become useful if going forward
we would want to support \<octal> or \x<hex> sequences, where closing
and re-opening quotes can be useful to delimit such sequences.

The ELF "Multibyte symbol names" test gets switched away from using
.set, as that would now also mean excluding nios2 and pru. By using
.equiv instead, even the existing #notarget can be dropped. (For h8300
the .section directive additionally needs attributes specified, to avoid
a target specific warning.)
2022-01-04 10:05:17 +01:00
Alan Modra
a2c5833233 Update year range in copyright notice of binutils files
The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.

The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
2022-01-02 12:04:28 +10:30
Alan Modra
b685de86cc ubsan: next_char_of_string signed integer overflow
Squash another totally useless fuzz report that I should have ignored.

	* read.c (next_char_of_string): Avoid integer overflow.
2022-01-01 14:22:13 +10:30
Alan Modra
487b0ff02d ubsan: signed integer multiply overflow
9223371018427387904 * 2 cannot be represented in type 'long', yes, but
we don't care.

	* expr.c (expr): Avoid signed overflow.
2022-01-01 14:22:11 +10:30
Alan Modra
443aa5f05e gas reloc sorting
In some cases, eg. riscv_pre_output_hook, gas generates out-of-order
relocations.  Various places in the linker assume relocs are sorted
by increasing r_offset, which is normally the case.  Provide
GAS_SORT_RELOCS to handle unsorted relocs.

bfd/
	PR 28709
	* elf32-nds32.c (nds32_insertion_sort): Make static.
	* elf32-nds32.h (nds32_insertion_sort): Delete declaration.
gas/
	PR 28709
	* write.c (write_relocs): Implement reloc sorting by r_offset
	when GAS_SORT_RELOCS.
	* config/tc-nds32.c (compar_relent, nds32_set_section_relocs): Delete.
	* config/tc-nds32.h (nds32_set_section_relocs): Don't declare.
	(SET_SECTION_RELOCS): Don't define.
	(GAS_SORT_RELOCS): Define.
	* config/tc-riscv.h (GAS_SORT_RELOCS): Define.
2021-12-28 23:00:01 +10:30
Nelson Chu
b6a08665ff RISC-V: Rewrite the csr testcases.
Maskray (Fangrui Song) had suggested me before that we should combine
multiple testcases into one file as possible as we can.  So that we can
more easily understand what these test cases are testing, and easier to
maintain.  Therefore, this patch rewrites all csr testcases, to make them
more clean.

gas/
	* testsuite/gas/riscv/csr-fail-nonexistent.d: Renamed from
	priv-reg-fail-nonexistent testcase.
	* testsuite/gas/riscv/csr-fail-nonexistent.: Likewise.
	* testsuite/gas/riscv/csr-fail-nonexistent.s: Likewise.
	* testsuite/gas/riscv/csr-insns-pseudo-noalias.d: Renamed from
	priv-reg-pseudo testcase.
	* testsuite/gas/riscv/csr-insns-pseudo.d: Likewise.
	* testsuite/gas/riscv/csr-insns-pseudo.s: Likewise.
	* testsuite/gas/riscv/csr-insns-read-only.d: Renamed from
	priv-reg-fail-read-only-02 testcase.
	* testsuite/gas/riscv/csr-insns-read-only.l: Likewise.
	* testsuite/gas/riscv/csr-insns-read-only.s: Likewise.
	* testsuite/gas/riscv/h-ext-32.d: Moved hypervisor csrs to csr.s.
	* testsuite/gas/riscv/h-ext-32.s: Likewise.
	* testsuite/gas/riscv/h-ext-64.d: Likewise.
	* testsuite/gas/riscv/h-ext-64.s: Likewise.
	* testsuite/gas/riscv/csr.s: Renamed from priv-reg.s, and then
	added the hypervisor csrs.
	* testsuite/gas/riscv/csr-version-1p9p1.d: The csr testcase when
	the privileged spec is 1.9.1.  Also tested all invalid csr warnings
	when -mcsr-check is enabled.
	* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p10.d: Likewise, but the
	privileged spec is 1.10..
	* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise, but the
	privileged spec is 1.11.
	* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise, but the
	privileged spec is 1.12.
	* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
	* testsuite/gas/riscv/priv-reg*: Removed or Renamed.
2021-12-24 16:08:25 +08:00
Vineet Gupta
a63375ac33 RISC-V: Hypervisor ext: support Privileged Spec 1.12
This is the Hypervisor Extension 1.0

 - Hypervisor Memory-Management Instructions
   HFENCE.VVMA, HFENCE.GVMA,

 - Hypervisor Virtual Machine Load and Store Instructions
   HLV.B, HLV.BU,          HSV.B,
   HLV.H, HLV.HU, HLVX.HU, HSB.H,
   HLV.W, HLV.WU, HLVX.WU, HSV.W,
   HLV.D,                  HSV.D

 - Hypervisor CSRs (some new, some address changed)
   hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip,
   htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah,
   vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp,

Note that following were added already as part of svinval extension
support:
   HINVAL.GVMA, HINVAL.VVMA

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Nelson Chu <nelson.chu@sifive.com>

bfd/
	* cpu-riscv.c (riscv_priv_specs): Added entry for 1.12.
	* cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12.
gas/
	* config/tc-riscv.c (abort_version): Updated comment.
	(validate_riscv_insn): Annotate switch-break.
	* testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor.
	* testsuite/gas/riscv/h-ext-32.s: Likewise.
	* testsuite/gas/riscv/h-ext-64.d: Likewise.
	* testsuite/gas/riscv/h-ext-64.s: Likewise.
include/
	* opcode/riscv-opc.h: Added encodings for hypervisor csrs and
	instrcutions.
opcodes/
	* riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.
2021-12-24 15:17:52 +08:00
Vineet Gupta
5c3ffbc4dd RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implementation/tests
This makes way for a clean 1.12 based Hypervisor Ext support.

There are no known implementors of 1.9.1 H-ext. (Per Jim, kendryte k210
is based on priv spec 1.9.1, but it seems unlikely that they implemented
H-ext).

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Nelson Chu <nelson.chu@sifive.com>

gas/
	* testsuite/gas/riscv/csr-dw-regnums.d: Drop the hypervisor csrs
	defined in the privileged spec 1.9.1.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg.s: Likewise.
include/
	* opcode/riscv-opc.h: Drop the hypervisor csrs defined in the
	privileged spec 1.9.1.
2021-12-24 15:17:45 +08:00
jiawei
85adb21d04 RISC-V: Update Scalar Crypto testcases.
Add opcodes in testcases to make sure every instruction generate
right opcode after disassemble.

gas/ChangeLog:

        * testsuite/gas/riscv/k-ext-64.d: Add opcode detect.
        * testsuite/gas/riscv/k-ext.d: Ditto.
        * testsuite/gas/riscv/zbkb-32.d: Ditto.
        * testsuite/gas/riscv/zbkb-64.d: Ditto.
        * testsuite/gas/riscv/zbkc-32.d: Ditto.
        * testsuite/gas/riscv/zbkc-64.d: Ditto.
        * testsuite/gas/riscv/zbkx-32.d: Ditto.
        * testsuite/gas/riscv/zbkx-64.d: Ditto.
        * testsuite/gas/riscv/zknd-32.d: Ditto.
        * testsuite/gas/riscv/zknd-64.d: Ditto.
        * testsuite/gas/riscv/zkne-32.d: Ditto.
        * testsuite/gas/riscv/zkne-64.d: Ditto.
        * testsuite/gas/riscv/zknh-32.d: Ditto.
        * testsuite/gas/riscv/zknh-64.d: Ditto.
        * testsuite/gas/riscv/zksed-32.d: Ditto.
        * testsuite/gas/riscv/zksed-64.d: Ditto.
        * testsuite/gas/riscv/zksh-32.d: Ditto.
        * testsuite/gas/riscv/zksh-64.d: Ditto.
2021-12-22 18:12:17 +08:00
Jan Beulich
47f4115a1b x86: -mfence-as-lock-add=yes doesn't work for 16-bit mode
Rather than trying to fix this (which would require making an assumption
on the upper half of %esp being zero), simply issue an error. While at
it, since the generated code is in conflict with -momit-lock-prefix=yes,
issue an error in that case as well.
2021-12-21 09:31:04 +01:00
Jan Beulich
ca988435c6 gas/ELF: avoid below-base ref in obj_elf_parse_section_letters()
We would better be prepared for 'm' being the first character of the
incoming string.
2021-12-21 09:30:03 +01:00
Vladimir Mezentsev
9833dd9767 x86: Terminate mnemonicendp in swap_operand()
Tested on x86_64-pc-linux-gnu.

opcodes/ChangeLog:
2021-12-17 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>

	* i386-dis.c (swap_operand): Terminate mnemonicendp.

gas/ChangeLog:
2021-12-17 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>

	* testsuite/gas/i386/opts-intel.d: Updated expected disassembly.
	* testsuite/gas/i386/opts.d: Likewise.
	* testsuite/gas/i386/sse2avx-opts-intel.d: Likewise.
	* testsuite/gas/i386/sse2avx-opts.d: Likewise.
	* testsuite/gas/i386/x86-64-opts-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-opts.d: Likewise.
	* testsuite/gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-sse2avx-opts.d: Likewise.
2021-12-17 17:01:44 -08:00
Nick Clifton
f3be70df1b Fix AVR assembler so that it creates relocs that will work with linker relaxation.
PR 28686
gas	* config/tc-avr.h (tc_fix_adjustable): Define.
	* config/tc-avr.c (avr_fix_adjustable): New function.
	* testsuite/gas/all/gas.exp: Skip tests that need adjustable fixups.
	* testsuite/gas/elf/elf.exp: Likewise.
	* testsuite/gas/avr/diffreloc_withrelax.d: Adjust expected output.
	* testsuite/gas/avr/pc-relative-reloc.d: Adjust expected output.

ld	* testsuite/ld-avr/avr-prop-7.d: Adjust expected output.
	* testsuite/ld-avr/avr-prop-8.d: Likewise.
	* testsuite/ld-avr/pr13402.d: Likewise.
2021-12-16 16:40:57 +00:00
Richard Sandiford
a2b1ea81ba arm: Add support for Armv9.1-A to Armv9.3-A
This patch adds AArch32 support for -march=armv9.[123]-a.
The behaviour of the new options can be expressed using a
combination of existing feature flags and tables.

The cpu_arch_ver entries for ARM_ARCH_V9_2A and ARM_ARCH_V9_3A
are technically redundant but it seemed less surprising to include
them anyway.

include/
	* opcode/arm.h (ARM_ARCH_V9_1A, ARM_ARCH_V9_2A): New macros.
	(ARM_ARCH_V9_3A): Likewise.

gas/
	* doc/c-arm.texi: Add armv9.1-a, armv9.2-a and armv9.3-a.
	* config/tc-arm.c (armv91a_ext_table, armv92a_ext_table): New macros.
	(armv93a_ext_table): Likewise.
	(arm_archs): Add armv9.1-a, armv9.2-a and armv9.3-a.
	(cpu_arch_ver): Add ARM_ARCH_V9_1A, ARM_ARCH_V9_2A and ARM_ARCH_V9_3A.
	* NEWS: Mention the above.
	* testsuite/gas/arm/attr-march-armv9_1-a.d: New test.
	* testsuite/gas/arm/attr-march-armv9_2-a.d: Likewise.
	* testsuite/gas/arm/attr-march-armv9_3-a.d: Likewise.
	* testsuite/gas/arm/bfloat16-armv9.1-a.d: Likewise.
	* testsuite/gas/arm/bfloat16-armv9.2-a.d: Likewise.
	* testsuite/gas/arm/bfloat16-armv9.3-a.d: Likewise.
	* testsuite/gas/arm/i8mm-armv9.1-a.d: Likewise.
	* testsuite/gas/arm/i8mm-armv9.2-a.d: Likewise.
	* testsuite/gas/arm/i8mm-armv9.3-a.d: Likewise.
2021-12-16 09:32:00 +00:00
Richard Sandiford
b3e4d9326f arm: Add support for Armv8.7-A and Armv8.8-A
This patch adds AArch32 support for -march=armv8.[78]-a.
The behaviour of the new options can be expressed using a
combination of existing feature flags and tables.

The cpu_arch_ver entries are technically redundant but
it seemed less surprising to include them anyway.

include/
	* opcode/arm.h (ARM_ARCH_V8_7A, ARM_ARCH_V8_8A): New macros.

gas/
	* doc/c-arm.texi: Add armv8.7-a and armv8.8-a.
	* config/tc-arm.c (armv87a_ext_table, armv88a_ext_table): New macros.
	(arm_archs): Add armv8.7-a and armv8.8-a.
	(cpu_arch_ver): Add ARM_ARCH_V8_7A and ARM_ARCH_V8_8A.
	* NEWS: Mention the above.
	* testsuite/gas/arm/attr-march-armv8_7-a.d: New test.
	* testsuite/gas/arm/attr-march-armv8_8-a.d: Likewise.
	* testsuite/gas/arm/bfloat16-armv8.7-a.d: Likewise.
	* testsuite/gas/arm/bfloat16-armv8.8-a.d: Likewise.
	* testsuite/gas/arm/i8mm-armv8.7-a.d: Likewise.
	* testsuite/gas/arm/i8mm-armv8.8-a.d: Likewise.
2021-12-16 09:32:00 +00:00
Richard Sandiford
3518022233 aarch64: Add support for Armv9.1-A to Armv9.3-A
This patch adds AArch64 support for -march=armv9.[123]-a.
The behaviour of the new options can be expressed using a
combination of existing feature flags, so we don't need to
eat into the vanishing number of spare AARCH64_FEATURE_* bits.
Hoewver, it was more convenient to separate out the |s of
feature flags so that Armv9.1-A could reuse the set for
Armv8.6-A, and so on.

include/
	* opcode/aarch64.h (AARCH64_ARCH_V8_FEATURES): New macro,
	split out from...
	(AARCH64_ARCH_V8): ...here.
	(AARCH64_ARCH_V8_1_FEATURES): New macro, split out from...
	(AARCH64_ARCH_V8_1): ...here.
	(AARCH64_ARCH_V8_2_FEATURES): New macro, split out from...
	(AARCH64_ARCH_V8_2): ...here.
	(AARCH64_ARCH_V8_3_FEATURES): New macro, split out from...
	(AARCH64_ARCH_V8_3): ...here.
	(AARCH64_ARCH_V8_4_FEATURES): New macro, split out from...
	(AARCH64_ARCH_V8_4): ...here.
	(AARCH64_ARCH_V8_5_FEATURES): New macro, split out from...
	(AARCH64_ARCH_V8_5): ...here.
	(AARCH64_ARCH_V8_6_FEATURES): New macro, split out from...
	(AARCH64_ARCH_V8_6): ...here.
	(AARCH64_ARCH_V8_7_FEATURES): New macro, split out from...
	(AARCH64_ARCH_V8_7): ...here.
	(AARCH64_ARCH_V8_8_FEATURES): New macro, split out from...
	(AARCH64_ARCH_V8_8): ...here.
	(AARCH64_ARCH_V9_FEATURES): New macro, split out from...
	(AARCH64_ARCH_V9): ...here.
	(AARCH64_ARCH_V9_1_FEATURES, AARCH64_ARCH_V9_1): New macros.
	(AARCH64_ARCH_V9_2_FEATURES, AARCH64_ARCH_V9_2): New macros.
	(AARCH64_ARCH_V9_3_FEATURES, AARCH64_ARCH_V9_3): New macros.

gas/
	* doc/c-aarch64.texi: Add armv9.1-a, armv9-2-a and armv9.3-a.
	* config/tc-aarch64.c (aarch64_archs): Likewise.
	* NEWS: Mention the above.
	* testsuite/gas/aarch64/armv9_invalid.d,
	testsuite/gas/aarch64/armv9_invalid.s,
	testsuite/gas/aarch64/armv9_invalid.l: New test.
	* testsuite/gas/aarch64/armv9_1.d,
	testsuite/gas/aarch64/armv9_1.s: Likewise.
	* testsuite/gas/aarch64/armv9_1_invalid.d,
	testsuite/gas/aarch64/armv9_1_invalid.s,
	testsuite/gas/aarch64/armv9_1_invalid.l: Likewise.
	* testsuite/gas/aarch64/armv9_2.d,
	testsuite/gas/aarch64/armv9_2.s: Likewise.
	* testsuite/gas/aarch64/armv9_2_invalid.d,
	testsuite/gas/aarch64/armv9_2_invalid.s,
	testsuite/gas/aarch64/armv9_2_invalid.l: Likewise.
	* testsuite/gas/aarch64/armv9_3.d,
	testsuite/gas/aarch64/armv9_3.s: Likewise.
2021-12-16 09:32:00 +00:00
Nelson Chu
23ff54c27d RISC-V: Support svinval extension with frozen version 1.0.
According to the privileged spec, there are five new instructions for
svinval extension.  Two of them (HINVAL.VVMA and HINVAL.GVMA) need to
enable the hypervisor extension.  But there is no implementation of
hypervisor extension in mainline for now, so let's consider the related
issues later.

                31..25  24..20 19..15 14..12 11...7 6..2  1..0
sinval.vma      0001011 rs2    rs1    000    00000  11100 11
sfence.w.inval  0001100 00000  00000  000    00000  11100 11
sfence.inval.ir 0001100 00001  00000  000    00000  11100 11
hinval.vvma     0010011 rs2    rs1    000    00000  11100 11
hinval.gvma     0110011 rs2    rs1    000    00000  11100 11

This patch is cherry-picked from the riscv integration branch since the
svinval extension is frozen for now.  Besides, we fix the funct7 encodings
of hinval.vvma and hinval.gvma, from 0x0011011 and 0x0111011 to 0x0010011
and 0x0110011.

bfd/
	* elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval.
	(riscv_multi_subset_supports): Handle INSN_CLASS_SVINVAL.
gas/
	* testsuite/gas/riscv/svinval.d: New testcase.
	* testsuite/gas/riscv/svinval.s: Likewise.
include/
	* opcode/riscv-opc.h: Added encodings for svinval.
	* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SVINVAL.
opcodes/
	* riscv-opc.c (riscv_opcodes): Added svinval instructions.
2021-12-16 16:04:53 +08:00
Alan Modra
a078dd9ce8 loongarch64 build failure on 32-bit host
gas/config/tc-loongarch.c: In function ‘loongarch_args_parser_can_match_arg_helper’:
gas/config/tc-loongarch.c:661:13: error: cast from pointer to integer of different size [-Werror=pointer
-to-int-cast]
  661 |       imm = (offsetT) str_hash_find (r_htab, arg);
      |             ^

Cast it to the correct size int, relying on normal integer promotions
if offsetT is larger than a pointer.

	* config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper):
	Cast return from str_hash_find to intptr_t, not offsetT.
2021-12-15 09:20:59 +10:30
Nelson Chu
de3a913df6 RISC-V: Clarify the behavior of .option arch directive.
* To be consistent with -march option, removed the "=" operator when
user want to reset the whole architecture string.  So the formats are,

.option arch, +<extension><version>, ...
.option arch, -<extension>
.option arch, <ISA string>

* Don't allow to add or remove the base extensions in the .option arch
directive.  Instead, users should reset the whole architecture string
while they want to change the base extension.

* The operator "+" won't update the version of extension, if the
extension is already in the subset list.

bfd/
	* elfxx-riscv.c (riscv_add_subset): Don't update the version
	if the extension is already in the subset list.
	(riscv_update_subset): To be consistent with -march option,
	removed the "=" operator when user want to reset the whole
	architecture string.  Besides, Don't allow to add or remove
	the base extensions in the .option arch directive.
gas/
	* testsuite/gas/riscv/option-arch-01.s: Updated since we cannot
	add or remove the base extensions in the .option arch directive.
	* testsuite/gas/riscv/option-arch-02.s: Likewise.
	* testsuite/gas/riscv/option-arch-fail.l: Likewise.
	* testsuite/gas/riscv/option-arch-fail.s: Likewise.
	* testsuite/gas/riscv/option-arch-01a.d: Set -misa-spec=2.2.
	* testsuite/gas/riscv/option-arch-01b.d: Likewise.
	* testsuite/gas/riscv/option-arch-02.d: Updated since the .option
	arch, + won't change the version of extension, if the extension is
	already in the subset list.
	* testsuite/gas/riscv/option-arch-03.s: Removed the "=" operator
	when resetting the whole architecture string.
2021-12-09 15:55:04 +08:00
Richard Sandiford
36cb9e7e17 aarch64: Update gas/NEWS for recent changes
gas/
	* NEWS: Mention support for Armv8.8-A and for new system registers.
2021-12-02 15:00:57 +00:00