By the look of it, git commit 39ff0b8123 broke 32-bit host
--enable-targets=all binutils builds.
/usr/local/bin/ld: ../opcodes/.libs/libopcodes.a(riscv-dis.o): in function `parse_riscv_dis_option':
/home/alan/src/binutils-gdb/opcodes/riscv-dis.c:102: undefined reference to `riscv_get_priv_spec_class'
collect2: error: ld returned 1 exit status
Makefile:925: recipe for target 'objdump' failed
The problem is that elfxx-riscv.c is not built for a 32-bit host
without --enable-64-bit-bfd or unless RISCV is given specifically as a
target. No such trimming of 64-bit only targets is done in opcodes.
One solution is to move these support functions to cpu-riscv.c, which
runs into "error: implicit declaration of function ‘xmalloc’". Now,
xmalloc is not supposed to be used in libbfd or libopcodes - it's rude
to crash out of an application that calls libbfd or libopcodes
functions without giving it a chance to deal with out-of-memory
itself. So I removed the xmalloc and instead used a fixed size
buffer. If you are worried about adding 36 bytes for the buffer to
the riscv_get_priv_spec_class_from_numbers stack frame size, then you
have no idea of the likely xmalloc + malloc stack frame size! Trying
to reduce memory usage is commendable, but in this instance
riscv_estimate_digit and malloc for a temp buffer uses a lot more
memory than a fixed max-size buffer.
* elfxx-riscv.c (struct priv_spec_t, priv_specs),
(riscv_get_priv_spec_class, riscv_get_priv_spec_class_from_numbers),
(riscv_get_priv_spec_name): Move to..
* cpu-riscv.c: ..here.
(riscv_get_priv_spec_class_from_numbers): Don't xmalloc temp buffer.
Use %u to print unsigned numbers.
The following GDB behaviour was observed:
(gdb) x/1i 0x0001014a
0x1014a <main+8>: jal 0x10132 <foo>
(gdb) show architecture
The target architecture is set automatically (currently riscv:rv32)
(gdb) set architecture riscv:rv32
The target architecture is assumed to be riscv:rv32
(gdb) x/1i 0x0001014a
0x1014a <main+8>: 0x37e5
(gdb)
Notice that initially we can disassemble the instruction (it's a
compressed jal instruction), but after setting the architecture we can
no longer disassemble the instruction.
This is particularly puzzling as GDB initially thought the
architecture was 'riscv:rv32', but when we force the architecture to
be that, the disassembly stops working.
This issue was introduced with this commit:
commit c35d018b1a
Date: Mon Jan 27 15:19:30 2020 -0800
RISC-V: Fix gdbserver problem with handling arch strings.
In this commit we try to make riscv_scan handle cases where we see
architecture strings like 'riscv:rv32imc' (for example). Normally
this wouldn't match as bfd_default_scan requires an exact match, so we
extended riscv_scan to ignore trailing characters.
Unfortunately the default riscv arch is called 'riscv', is 64-bit,
and has its mach type set to 0, which I think is intended to pair with
code is riscv-dis.c:riscv_disassemble_insn that tries to guess if we
are 32 or 64 bit.
What happens then is that 'riscv:rv32' is first tested against 'riscv'
using bfd_default_scan, this doesn't match, we then compare this to
'riscv', but allowing trailing characters to be ignored, this matches,
and our 'riscv:rv32' matches against the default (64-bit)
architecture.
The solution I propose is to prevent the default architecture from
taking part in this "ignore trailing characters" extra match case,
only the more specific 'riscv:rv32' and 'riscv:rv64' get this extra
matching.
bfd/ChangeLog:
* cpu-riscv.c (riscv_scan): Don't allow shorter matches using the
default architecture.
Maciej reported a problem found by his RISC-V gdbserver port.
warning: while parsing target description (at line 4): Target description specified unknown architecture "riscv:rv64id"
warning: Could not load XML target description; ignoring
We only have two arches defined, riscv:rv32 and riscv:rv64. Both bfd and
gdb are creating arch strings that have extension letters added to the base
architecture. The bfd_default_scan function requires an exact match, so
these strings fail to map to a bfd_arch. I think we should ignore the
extension letters in a RISC-V specific scan function.
bfd/
* cpu-riscv.c (riscv_scan): New.
(N): Change bfd_default_scan to riscv_scan.
Change-Id: I096476705e1da5cb8934c5005b1eed2a8989f7a7
