For R_LARCH_TLS_{LE_HI20_R,LE_ADD_R,LD_PC_HI20,GD_PC_HI20, DESC_PC_HI20}
relocations, start a new frag to get correct eh_frame Call Frame Information
FDE DW_CFA_advance_loc info.
Gcc may generate "\t.align\t%d,54525952,4\n" before commit
b20c7ee066cb7d952fa193972e8bc6362c6e4063. To write 54525952 (NOP) to object
file, we call s_align_ptwo (-4). It result in alignment padding must be a
multiple of 4 if .align has second parameter.
Use default s_align_ptwo for .align.
There are two issues causing 11 test failures:
1. The TLS desc tests are matching the entire disassemble of a linked
executable. But if ld is configured --enable-default-hash-style=gnu
(note that most modern distros use this option), the layout of the
linked executables will be different and the immediate operands in
the linked executables will also be different. So we add
"--hash-style=both" for these tests to cancel the effect of
--enable-default-hash-style=gnu, like [x86_64 mark-plt tests].
2. By default objdump disassemble uses [pseudo-instructions] so "addi.w"
is outputed as "li.w", causing mismatches in TLS relaxation tests.
We can turn off the pseudo-instruction usage in objdump using "-M
no-aliases" to fix them.
[x86_64 mark-plt tests]: 16666ccc91
[pseudo-instructions]: 17f9439038
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
This matches the dependencies in the architecture, in LLVM, and even in the
original Binutils commit message that mistakenly included it only in armv9.4-a.
Before running our tests, we made a fake installation into ./tmpdir.
This installation changes libopcodes.la in the build area.
Gas testing may fail if gas and gprofng tests are run in parallel.
I create a script to run gprofng. Inside this script, LD_LIBRARY_PATH,
GPROFNG_SYSCONFDIR are set.
putenv_libcollector_ld_misc() first uses $GPROFNG_PRELOAD_LIBDIRS to create
directories for SP_COLLECTOR_LIBRARY_PATH ($SP_COLLECTOR_LIBRARY_PATH is used
to set up LD_PRELOAD).
gprofng/ChangeLog
2024-01-19 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
PR gprofng/31252
PR gprofng/30808
* src/envsets.cc (putenv_libcollector_ld_misc): Use
$GPROFNG_PRELOAD_LIBDIRS first to build SP_COLLECTOR_LIBRARY_PATH.
* testsuite/config/default.exp: Create a script to run gprofng.
* testsuite/lib/display-lib.exp: Fix typo.
Append "#pass" to APX tests for targets which pad text sections with NOPs.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Append
"#pass".
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: Likewise.
(cherry picked from commit f530d5f1ba)
VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As
long as the immediate has the top 4 bits clear, they are equivalent to
the earlier VEX-encoded insns, and hence can be used to permit use of
eGPR-s in the memory operand. Since this is the normal way of using
these insns, also alter the resulting diagnostic to complain about the
immediate, not the eGPR use.
When there's a suitably disambiguating register operand, suffixes are
generally omitted (unless in suffix-always mode). All NDD insns have a
suitable register operand, so they shouldn't have suffixes by default.
This corrects a counting problem, where prior to relocate_section relr
encoded relative relocs were allowed when it was known they were on
even boundaries, but relocate_section can only put relative relocs
(non-relr) on eight byte boundaries.
PR 30824
* elf64-ppc.c (RELR_ALIGN): Define, use throughout.
(maybe_relr): New function, use throughout.
(cherry picked from commit f91074ebd8)
Pass --hash-style=both to ld for -z mark-plt tests to support linker
configured with --enable-default-hash-style=gnu.
* testsuite/ld-x86-64/mark-plt-1b-x32.d: Pass --hash-style=both
to ld.
* testsuite/ld-x86-64/mark-plt-1b.d: Likewise.
* testsuite/ld-x86-64/mark-plt-1d-x32.d: Likewise.
* testsuite/ld-x86-64/mark-plt-1d.d: Likewise.
(cherry picked from commit 16666ccc91)
Since SCFI isn't supported on x32:
Fatal error: SCFI is not supported for this ABI
skip SCFI tests for x32 targets.
PR gas/31245
* testsuite/gas/scfi/x86_64/scfi-x86-64.exp: Skip for x32
targets.
(cherry picked from commit 7bd344dd0e)
Along with the relevant unit-tests, this adds the following rcpc3
instructions:
STL1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAP1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAPUR <Bt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Ht>, [<Xn|SP>{, #<simm>}]
LDAPUR <St>, [<Xn|SP>{, #<simm>}]
LDAPUR <Dt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Qt>, [<Xn|SP>{, #<simm>}]
STLUR <Bt>, [<Xn|SP>{, #<simm>}]
STLUR <Ht>, [<Xn|SP>{, #<simm>}]
STLUR <St>, [<Xn|SP>{, #<simm>}]
STLUR <Dt>, [<Xn|SP>{, #<simm>}]
STLUR <Qt>, [<Xn|SP>{, #<simm>}]
with `#<simm>' taking on a signed 8-bit integer value in the range
[-256,255] and `index' the values 0 or 1.
Co-authored-by: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Given the introduction of the new address operand types for rcpc3
instructions, this patch adds the necessary logic to teach
`general_constraint_met_p` how to proper handle these.
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
- AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
- AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
Beyond the need to encode any registers involved in data transfer and
the address base register for load/stores, it is necessary to specify
the data register addressing mode and whether the address register is
to be pre/post-indexed, whereby loads may be post-indexed and stores
pre-indexed with write-back.
The use of a single bit to specify both the indexing mode and indexing
value requires a novel function be written to accommodate this for
address operand insertion in assembly and another for extraction in
disassembly, along with the definition of two insn fields for use with
these instructions.
This therefore defines the following functions:
- aarch64_ins_rcpc3_addr_opt_offset
- aarch64_ins_rcpc3_addr_offset
- aarch64_ext_rcpc3_addr_opt_offset
- aarch64_ext_rcpc3_addr_offset
It extends the `do_special_{encoding|decoding}' functions and defines
two rcpc3 instruction fields:
- FLD_opc2
- FLD_rcpc3_size
The allowed immediate offsets in integer rcpc3 load store instructions
are not encoded explicitly in the instruction itself, being rather
implicitly equivalent to the amount of data loaded/stored by the
instruction.
This leads to the requirement that this quantity be calculated based on
the number of registers involved in the transfer, either as data
source or destination registers and their respective qualifiers.
This is done via `calc_ldst_datasize (const aarch64_opnd_info *opnds)'
implemented here, using a cumulative sum of qualifier sizes preceding
the address operand in the OPNDS operand list argument.
Indicating the presence of the Armv8.2-a feature adding further
support for the Release Consistency Model, the `+rcpc3' architectural
extension flag is added to the list of possible `-march' options in
Binutils, together with the necessary macro for encoding rcpc3
instructions.
This fixes the ld "Handle no DWARF information" testcase. Which
currently fails on riscv because a local label name is assumed
to be the current function name.
bfd/ChangeLog:
* elfnn-riscv.c (riscv_maybe_function_sym): Also check
_bfd_elf_is_local_label_name.
There are some tlbi operations that don't have a corresponding tlbip operation,
but we were incorrectly using the same list for both. Add the missing tlbi
*nxs operations, and use the F_REG_128 flag to filter tlbi operations that
don't have a tlbip analogue. For increased clarity, I have also used a macro
to reduce duplication between the 'nxs' and non-'nxs' variants, and added a
test to verify that no invalid combinations are accepted.
Additionally, fix two missing checks for AARCH64_OPND_SYSREG_TLBIP that were
preventing disassembly of tlbip instructions.
Hi,
This patch add support for SVE2.1 instructions ld1q,
ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 instruction faddqv,
fmaxnmqv, fmaxqv, fminnmqv and fminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 instruction dupq, eorqv and extq.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
