While investigating an unrelated issue in remote.c I noticed that the
bound checking for 'g' packets was bogus:
The previous code would only check that the first byte of the register
was within bounds before passing the buffer to regcache_raw_supply.
If it turned out that the register in the 'g' packet was incomplete
then regcache_raw_supply would proceed to memcpy out-of-bounds.
Since the buffer is allocated with alloca it's relatively unlikely to
crash (you just end up dumping gdb's stack into the cache) but it's
still a bit messy.
I changed this logic to check for truncated registers and raise an
error if one is encountered. Hopefully it should make debugging
remote stubs a bit easier.
gdb/ChangeLog:
2016-11-08 Lionel Flandrin <lionel@svkt.org>
* remote.c (process_g_packet): Detect truncated registers in 'g'
packets and raise an error.
Since Bad_Opcode and FGRPd9_2 were the same in i386-dis.c, all
Bad_Opcode entries in float_reg were displaced as FGRPd9_2. This
patch adds an entry for Bad_Opcode in fgrps to avoid treating it
as FGRPd9_2.
gas/
PR binutils/20775
* testsuite/gas/i386/i386.exp: Run fpu-bad.
* testsuite/gas/i386/fpu-bad.d: New file.
* testsuite/gas/i386/fpu-bad.s: Likewise.
opcodes/
PR binutils/20775
* i386-dis.c (FGRPd9_2): Replace 0 with 1.
(FGRPd9_4): Replace 1 with 2.
(FGRPd9_5): Replace 2 with 3.
(FGRPd9_6): Replace 3 with 4.
(FGRPd9_7): Replace 4 with 5.
(FGRPda_5): Replace 5 with 6.
(FGRPdb_4): Replace 6 with 7.
(FGRPde_3): Replace 7 with 8.
(FGRPdf_4): Replace 8 with 9.
(fgrps): Add an entry for Bad_Opcode.
PR ld/20784
* emultempl/elf32.em (search_needed): Fix infinite loop when
unable to process a token. Add support for curly braced enclosed
tokens.
* ld.texinfo (--rpath-link): Document supprot for $ORIGIN and
$LIB.
When we match against an address type operand within an instruction it
is important that we match exactly the right address type operand early
on, during the opcode selection phase. If we wait until the operand
insertion phase to check that we have the correct address operand, then
it is too late to select an alternative opcode. This becomes important
only when we have multiple opcodes with the same mnemonic, and operand
lists that differ only in the type of the address operands.
This commit fixes this issue, and adds some example instructions that
require this issue to be fixed (the instructions are identical except
for the address type operand).
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Use insert function to
validate matching address type operands.
* testsuite/gas/arc/nps400-10.d: New file.
* testsuite/gas/arc/nps400-10.s: New file.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_operands): Add F_DI14.
(arc_flag_classes): Add C_DI14.
* arc-nps400-tbl.h: Add new exc instructions.
I've been using dwarf-mode.el again recently and I found it mildly
annoying that the mode doesn't set default-directory. Setting it
means that operations in the dwarf-browsing buffer default to the
directory holding the object file being investigated.
This bumps the version number as well so that updating it via the
package manager works properly.
2016-11-04 Tom Tromey <tom@tromey.com>
* dwarf-mode.el (dwarf-browse): Set default-directory. Bump
version number.
Since the bpp instruction has been added the 16 bit wide pc relative
relocs might occur at offset 2 as well at offset 4 in an instruction.
With this patch the different adjustment is passed from
md_gather_operand to md_apply_fix via fx_pcrel_adjust field in the fix
data structure.
No regressions on s390x.
gas/ChangeLog:
2016-11-04 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (md_gather_operands): Set fx_pcrel_adjust.
(md_apply_fix): Use/Set fx_pcrel_adjust.
* testsuite/gas/s390/zarch-zEC12.d: Add bpp reloc test pattern.
* testsuite/gas/s390/zarch-zEC12.s: Add bpp reloc test.
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (cortex-m33): Declare new processor.
* doc/c-arm.texi (-mcpu ARM command line option): Document new
Cortex-M33 processor.
* NEWS: Mention ARM Cortex-M33 support.
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (cortex-m23): Declare new processor.
* doc/c-arm.texi (-mcpu ARM command line option): Document new
Cortex-M23 processor.
* NEWS: Mention ARM Cortex-M23 support.
* emultempl/elf32.em (search_needed): Remove use of getauxval and
inclusion of <sys/auxv.h>. Replace support for $PLATFORM with a
warning message.
* configure.ac (AC_CHECK_FUNCS): Remove getauxval.
* configure: Regenerate.
* config.in: Regenerate.
Currently the EXCLUDE_FILE linker script construct can only be used
within the input section list, and applied only to the section pattern
immediately following the EXCLUDE_FILE. For example:
*.o (EXCLUDE_FILE (a.o) .text .rodata)
In this case all sections matching '.text' are included from all files
matching '*.o' but not from the file 'a.o'. All sections matching
'.rodata' are also included from all files matching '*.o' (incluing from
'a.o').
If the user wants to restrict the inclusion of section '.rodata' so that
this too is not taken from the file 'a.o' then the above example must be
extended like this:
*.o (EXCLUDE_FILE (a.o) .text EXCLUDE_FILE (a.o) .rodata)
However, due to the internal grammar of the linker script language the
snippet 'EXCLUDE_FILE (a.o) .text' is parsed by a pattern called
'wildcard_spec'. The same 'wildcard_spec' pattern is also used to parse
the input file name snippet '*.o' in the above examples. As a result of
this pattern reuse within the linker script grammar then the following
is also a valid linker script construct:
EXCLUDE_FILE (a.o) *.o (.text .rodata)
However, though the linker accepts this without complaint the
EXCLUDE_FILE part is silently ignored and has no effect.
This commit takes this last example and makes it a useful, valid,
construct. The last example now means to include sections '.text' and
'.rodata' from all files matching '*.o' except for the file 'a.o'.
If the list of input sections is long, and the user knows that the file
exclusion applies across the list then the second form might be a
clearer alternative to replicating the EXCLUDE_FILE construct.
I've added a set of tests for EXCLUDE_FILE to the linker, including
tests for the new functionality.
ld/ChangeLog:
* ldlang.h (struct lang_wild_statement_struct): Add
exclude_name_list field.
* ldlang.c (walk_wild_file_in_exclude_list): New function.
(walk_wild_consider_section): Use new
walk_wild_file_in_exclude_list function.
(walk_wild_file): Add call to walk_wild_file_in_exclude_list.
(print_wild_statement): Print new exclude_name_list field.
(lang_add_wild): Initialise new exclude_name_list field.
* testsuite/ld-scripts/exclude-file-1.d: New file.
* testsuite/ld-scripts/exclude-file-1.map: New file.
* testsuite/ld-scripts/exclude-file-1.t: New file.
* testsuite/ld-scripts/exclude-file-2.d: New file.
* testsuite/ld-scripts/exclude-file-2.map: New file.
* testsuite/ld-scripts/exclude-file-2.t: New file.
* testsuite/ld-scripts/exclude-file-3.d: New file.
* testsuite/ld-scripts/exclude-file-3.map: New file.
* testsuite/ld-scripts/exclude-file-3.t: New file.
* testsuite/ld-scripts/exclude-file-4.d: New file.
* testsuite/ld-scripts/exclude-file-4.map: New file.
* testsuite/ld-scripts/exclude-file-4.t: New file.
* testsuite/ld-scripts/exclude-file-a.s: New file.
* testsuite/ld-scripts/exclude-file-b.s: New file.
* testsuite/ld-scripts/exclude-file.exp: New file.
* ld.texinfo (Input Section Basics): Update description of
EXCLUDE_FILE to cover the new features.
* NEWS: Mention new EXCLUDE_FILE usage.
When creating object files during testing, base the name of the object
file on the name of the source file, rather than using dump0.o,
dump1.o, etc. There's a few places where we have multiple source
files with the same name but in different directories, in these cases,
even after this change, we still add a numerical suffix to make the
object file names unique. So if we have 'foo/src.s' and 'bar/src.s',
we will create object files 'src.o' and 'src1.o'.
Update the few tests that hard code the object file name into the
expected test results.
ld/ChangeLog:
* testsuite/lib/ld-lib.exp (run_dump_test): Use object file names
based on the original source file name.
* testsuite/ld-discard/extern.d: Update object file names.
* testsuite/ld-discard/start.d: Likewise.
* testsuite/ld-discard/static.d: Likewise.
* testsuite/ld-elf/orphan-8.map: Likewise.
Add the xc16x-elf target to the list of targets that do not support
the -shared option. Being missing from this list was causing the
linker to add '-z norelro' to the link line of many tests, which in
turn caused these tests to fail.
ld/ChangeLog:
* testsuite/lib/ld-lib.exp (check_shared_lib_support): Add
xc16x-*-elf to the list of targets that don't support -shared.
Rename file_NAME_list to section_NAME_list in the linker's grammar
file. This rename reflects how the pattern is now being used, and makes
the grammar easier to understand.
There should be no functional change after this commit.
ld/ChangeLog:
* ldgram.y: Rename file_NAME_list to section_NAME_list
throughout.
2016-10-28 Manish Goregaokar <manish@mozilla.com>
gdb/ChangeLog:
* rust-lang.c (rust_union_is_untagged): Add function to
check if a union is an untagged unioni
(rust_val_print): Handle printing of untagged union values
(rust_print_type): Handle printing of untagged union types
(rust_evaluate_subexp): Handle evaluating field
access on untagged unions
2016-10-27 Manish Goregaokar <manish@mozilla.com>
gdb/ChangeLog:
* rust-lang.c (rust_get_disr_info): Treat univariant enums
without discriminants as encoded enums with a real field
* rust-lang.c (rust_evaluate_subexp): Handle field access
on encoded struct-like enums
gdb/testsuite/ChangeLog:
* simple.rs: Add test for univariant enums without discriminants
and for encoded struct-like enums
* simple.exp: Add test expectations
The long immediate operand chosen for one of the ldbit tests is
equivalent to a small negative value that would fit inside an s9
operand, leading to the assembler to choose an unexpected (but
legitimate) encoding of the instruction on 32-bit systems, and
therefore causing the test to fail. This commit fixes the test by
changing the offending limm value so that it can no longer be
interpreted as an s9 operand.
gas/ChangeLog:
* testsuite/gas/arc/nps400-6.s: Change ldbit tests so that
limm operands are out of the range of an s9, in order to fix
the test.
* testsuite/gas/arc/nps400-6.d: Updated to match new expected
output.
The current handling for arc instructions longer than 32-bits is all
handled as a special case in both the assembler and disassembler.
The problem with this approach is that it leads to code duplication,
selecting a long instruction is exactly the same process as selecting a
short instruction, except over more bits, in both cases we select based
on bit comparison, and initial operand insertion and extraction.
This commit unifies both the long and short instruction worlds,
converting the core opcodes library from being largely 32-bit focused,
to being largely 64-bit focused.
The changes are, on the whole, not too much. There's obviously a lot of
type changes but otherwise the bulk of the code just works. Most of the
actual functional changes are to code that previously handled the longer
48 or 64 bit instructions. The insert/extract handlers for these have
now been brought into line with the short instruction insert/extract
handlers.
All of the special case handling code that was previously added has now
been removed again. Overall, this commit reduces the amount of code in
the arc assembler and disassembler.
gas/ChangeLog:
* config/tc-arc.c (struct arc_insn): Change type of insn field.
(md_number_to_chars_midend): Support 6- and 8-byte values.
(emit_insn0): Update debug output.
(find_opcode_match): Likewise.
(build_fake_opcode_hash_entry): Delete.
(find_special_case_long_opcode): Delete.
(find_special_case): Remove long format special case handling.
(insert_operand): Change instruction type and update debug print
format.
(assemble_insn): Change instruction type, update debug print
formats, and remove unneeded assert.
include/ChangeLog:
* opcode/arc.h (struct arc_opcode): Change type of opcode and mask
fields.
(struct arc_long_opcode): Delete.
(struct arc_operand): Change types for insert and extract
handlers.
opcodes/ChangeLog:
* arc-dis.c (struct arc_operand_iterator): Remove all fields
relating to long instruction processing, add new limm field.
(OPCODE): Rename to...
(OPCODE_32BIT_INSN): ...this.
(OPCODE_AC): Delete.
(skip_this_opcode): Handle different instruction lengths, update
macro name.
(special_flag_p): Update parameter type.
(find_format_from_table): Update for more instruction lengths.
(find_format_long_instructions): Delete.
(find_format): Update for more instruction lengths.
(arc_insn_length): Likewise.
(extract_operand_value): Update for more instruction lengths.
(operand_iterator_next): Remove code relating to long
instructions.
(arc_opcode_to_insn_type): New function.
(print_insn_arc):Update for more instructions lengths.
* arc-ext.c (extInstruction_t): Change argument type.
* arc-ext.h (extInstruction_t): Change argument type.
* arc-fxi.h: Change type unsigned to unsigned long long
extensively throughout.
* arc-nps400-tbl.h: Add long instructions taken from
arc_long_opcodes table in arc-opc.c.
* arc-opc.c: Update parameter types on insert/extract handlers.
(arc_long_opcodes): Delete.
(arc_num_long_opcodes): Delete.
(arc_opcode_len): Update for more instruction lengths.
highbyte and lowbyte actually refer to the low byte and the high
byte respectively, but are used consistently in this swapped
order. This commit swaps them round so that highbyte refers to the
high byte and lowbyte refers to the low byte.
There should be no functional change after this commit.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
In preparation to moving to a world where arc instructions can be 2, 4,
6, or 8 bytes long, make some macros 64-bit safe.
There should be no functional change after this commit.
include/ChangeLog:
* opcode/arc.h: Make macros 64-bit safe.
In preparation for moving to a world where arc instructions can be 2, 4,
6, or 8 bytes in length, replace the ARC_SHORT macro (which is either
true of false) with an arc_opcode_len function that returns a length in
bytes.
There should be no functional change after this commit.
gas/ChangeLog:
* config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with
arc_opcode_len.
include/ChangeLog:
* opcode/arc.h (arc_opcode_len): Declare.
(ARC_SHORT): Delete.
opcodes/ChangeLog:
* arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
with arc_opcode_len.
(find_format_long_instructions): Likewise.
* arc-opc.c (arc_opcode_len): New function.
When assembling an instruction replace the short_insn boolean flag with
an integer field for holding the instruction length. This is in
preparation for moving to a world where instructions can be 2, 4, 6, or
8 bytes in length.
gas/ChangeLog:
* config/tc-arc.c (struct arc_insn): Replace short_insn flag with
len field.
(apply_fixups): Update to use len field.
(emit_insn0): Simplify code, making use of len field.
(md_convert_frag): Update to use len field.
(assemble_insn): Update to use len field.
A few masks were incorrect, there were opcode bits that lives outside of
the instruction mask, the effected instructions are decode1, zncv, and
efabgt.
Previously these instructions would assemble and disassemble correctly,
and a correctly encoded binary should behave no differently. The only
difference would be seen in a few incorrectly encoded binaries,
previously these would have decoded to the above instructions, while now
they will not.
opcodes/ChangeLog:
* arc-nps400-tbl.h: Fix some instruction masks.
This adds an option for the Qualcomm falkor core, the corresponding
gcc patch is here:
https://gcc.gnu.org/ml/gcc-patches/2016-11/msg00262.html
This was tested with aarch64 and armhf builds and make check and also
by building and running SPEC2006.
* config/tc-aarch64.c (aarch64_cpus): Add falkor.
* config/tc-arm.c (arm_cpus): Likewise.
* doc/c-aarch64.texi: Likewise.
* doc/c-arm.texi: Likewise.
As we require c++11, GDB fails to build if bison is not new enough.
I see the following error on the system (fedora 19) that bison is
2.6.4,
g++ -std=gnu++11 .... \
-c -o ada-exp.o -MT ada-exp.o -MMD -MP -MF .deps/ada-exp.Tpo 'if test -f ada-exp.c; then echo ada-exp.c; else echo ../../binutils-gdb/gdb/ada-exp.c; fi`
In file included from ../../binutils-gdb/gdb/ada-exp.y:731:0:
ada-lex.c:113:0: error: "YY_NULL" redefined [-Werror]
#define YY_NULL 0
^
ada-exp.c:158:0: note: this is the location of the previous definition
# define YY_NULL nullptr
^
cc1plus: all warnings being treated as errors
make: *** [ada-exp.o] Error 1
Both ada-exp.c and ada-lex.c has macro YY_NULL, like this,
$ cat 1.c
# ifndef YY_NULL
# if defined __cplusplus && 201103L <= __cplusplus
# define YY_NULL nullptr
# else
# define YY_NULL 0
# endif
# endif
#define YY_NULL 0
as we can see, YY_NULL is defined differently (nullptr vs 0)
$ g++ -std=c++11 -Wall 1.c -c
1.c:9:0: warning: "YY_NULL" redefined
#define YY_NULL 0
^
1.c:3:0: note: this is the location of the previous definition
# define YY_NULL nullptr
^
$ g++ -Wall 1.c -c
bison renames YY_NULL to YY_NULLPTR in 2013 Nov,
https://lists.gnu.org/archive/html/bison-patches/2013-11/msg00002.html
and bison released later than 2013 Nov have this patch. Bison 3.0.2,
released on 2013 Dec, is OK.
The fix is to replace YY_NULL with YY_NULLPTR via sed. With old bison,
YY_NULL becomes YY_NULLPTR; with new bison, YY_NULLPTR becomes
YY_NULLPTRPTR,
gdb:
2016-11-03 Yao Qi <yao.qi@linaro.org>
* Makefile.in (.y.c): Replace YY_NULL with YY_NULLPTR.
The REG_82 entry in x86 disassembler is for opcode 0x83, not opcode
0x82.
* i386-dis.c (REG_82): Renamed to ...
(REG_83): This.
(dis386): Updated.
(reg_table): Likewise.
