2002-12-31 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (validate_mips_insn, mips_ip): Recognize
the "+D" operand, which will be used only by the disassembler.
[ gas/testsuite/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0sel-names-mips32.d: New test.
* gas/mips/cp0sel-names-mips32r2.d: New test.
* gas/mips/cp0sel-names-mips64.d: New test.
* gas/mips/cp0sel-names-numeric.d: New test.
* gas/mips/cp0sel-names-sb1.d: New test.
* gas/mips/cp0sel-names.s: New test source file.
* gas/mips/mips.exp: Run new tests.
[ include/opcode/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* mips.h: Note that the "+D" operand type name is now used.
[ opcodes/ChangeLog ]
2002-12-31 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0sel_name): New structure.
(mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
(mips_cp0sel_names_sb1): New arrays.
(mips_arch_choice): New structure members "cp0sel_names" and
"cp0sel_names_len".
(mips_arch_choices): Add references to new cp0sel_names arrays
as appropriate, and make all existing entries reference
appropriate mips_XXX_names_numeric arrays rather than simply
using NULL.
(mips_cp0sel_names, mips_cp0sel_names_len): New variables.
(lookup_mips_cp0sel_name): New function.
(set_default_mips_dis_options): Set mips_cp0sel_names and
mips_cp0sel_names_len as appropriate. Remove now-unnecessary
checks for NULL register name arrays.
(parse_mips_dis_option): Likewise.
(print_insn_arg): Handle "+D" operand type.
* mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
names symbolically.
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/elf_arch_mips1.d: New test.
* gas/mips/elf_arch_mips2.d: New test.
* gas/mips/elf_arch_mips3.d: New test.
* gas/mips/elf_arch_mips4.d: New test.
* gas/mips/elf_arch_mips5.d: New test.
* gas/mips/elf_arch_mips32.d: New test.
* gas/mips/elf_arch_mips32r2.d: New test.
* gas/mips/elf_arch_mips64.d: New test.
* gas/mips/empty.s: New test source file.
* gas/mips/mips.exp: Run new tests.
* gas/mips/elf_ase_mips16.d: Change to use empty.s
* gas/mips/elf_ase_mips16.s: Remove.
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
* archures.c (bfd_mach_mipsisa32r2): New define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsisa32r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa32r2.
* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
(_bfd_mips_elf_final_write_processing): Add
bfd_mach_mipsisa32r2 case.
(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
binaries marked as using MIPS32 Release 2.
[ binutils/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
changes in MIPS -M options.
[ gas/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
CPU variants.
* configure: Regenerate.
* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
(macro_build): Handle "K" operand.
(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
CPU_HAS_DROR and CPU_HAS_ROR are currently used.
(mips_ip): New variable "lastpos", and implement "+A", "+B",
and "+C" operands for MIPS32 Release 2 ins/ext instructions.
Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
(validate_mips_insn): Implement "+" as a way to extend the
allowed operands, and implement "K", "+A", "+B", and "+C"
operands.
(OPTION_MIPS32R2): New define.
(md_longopts): Add entry for OPTION_MIPS32R2.
(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
(md_parse_option): Handle OPTION_MIPS32R2.
(s_mipsset): Reimplement handling of ".set mipsN" options
and add support for ".set mips32r2".
(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
(md_show_usage): Document "-mips32r2" option.
* doc/as.texinfo: Document "-mips32r2" option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32r2.d: New test.
* gas/mips/hwr-names-mips32r2.d: New test.
* gas/mips/hwr-names-numeric.d: New test.
* gas/mips/hwr-names.s: New test source file.
* gas/mips/mips32r2.d: New test.
* gas/mips/mips32r2.s: New test source file.
* gas/mips/mips32r2-ill.l: New test.
* gas/mips/mips32r2-ill.s: New test source file.
* gas/mips/mips.exp: Add mips32r2 architecture data array
entry. Run new tests mentioned above.
[ include/elf/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_32R2): New define.
[ include/opcode/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document "+" as the start of two-character operand
type names, and add new "K", "+A", "+B", and "+C" operand types.
(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
defines.
[ opcodes/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
(mips_hwr_names_mips3264r2): New arrays.
(mips_arch_choice): New "hwr_names" member.
(mips_arch_choices): Adjust for structure change, and add a new
entry for "mips32r2" ISA.
(mips_hwr_names): New variable.
(set_default_mips_dis_options): Set mips_hwr_names.
(parse_mips_dis_option): New "hwr-names" option which sets
mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
(print_insn_arg): Change return type to "int"
and use that to indicate number of characters consumed.
Add support for "+" operand extension character, "+A", "+B",
"+C", and "K" operands.
(print_insn_mips): Adjust for changes to print_insn_arg.
(print_mips_disassembler_options): Adjust for "hwr-names"
addition and "reg-names" change.
* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
forms of "sll". Add new MIPS32 Release 2 instructions: ehb,
di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
Note that hardware rotate instructions (ror, rorv) can be
used on MIPS32 Release 2, and add the official mnemonics
for them (rotr, rotrv) and the similar "rotl" mnemonic for
left-rotate.
* gas/mips/mips.exp: Define the notion of an "architecture data
array," add comments indicating how to add a new architecture and
suggestions for adding new tests. Populate the architecture data
array with many known architectures and convert many tests to
be run for multiple architectures.
(mips_arches): New global array.
(mips_arch_create, mips_arch_list_all, mips_arch_data)
(mips_arch_displayname, mips_arch_properties)
(mips_arch_as_flags, mips_arch_objdump_flags, mips_arch_matches)
(mips_arch_list_matching): New functions to operate on mips_arches.
(run_dump_test_arch, run_dump_test_arches, run_list_test_arch)
(run_list_test_arches): New functions.
(run_list_test): Document and add an optional "test name" argument.
* gas/mips/abs.d: Remove CPU-specific assembler and objdump flags,
and CPU names from test names.
* gas/mips/add.d: Likewise.
* gas/mips/and.d: Likewise.
* gas/mips/dli.d: Likewise.
* gas/mips/jal-empic-elf-2.d: Likewise.
* gas/mips/jal-empic-elf-3.d: Likewise.
* gas/mips/jal-empic-elf.d: Likewise.
* gas/mips/lb-svr4pic.d: Likewise.
* gas/mips/lb.d: Likewise.
* gas/mips/mips32.d: Likewise.
* gas/mips/mips4.d: Likewise.
* gas/mips/mips64.d: Likewise.
* gas/mips/rol-hw.d: Likewise.
* gas/mips/rol.d: Likewise.
* gas/mips/rol64-hw.d: Likewise.
* gas/mips/rol64.d: Likewise.
* gas/mips/elf-jal.d: Likewise. Also, indicate ELF in test name.
* gas/mips/mips64-mdmx.d: Tweak printed name to indicate that this
test uses the -mdmx flag.
* gas/mips/mips64-mips3d.d: Tweak printed name to indicate that
this test uses the -mips3d flag.
* gas/mips/mips64-mips3d-incl.d: New file.
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
"dror" entries, and reorder the remaining "dror" and "ror" entries.
[ gas/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
use hardware rotate ops as appropriate. In M_DROL_I, M_DROR_I,
M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
arrange not to issue warnings about use of AT when AT is not
actually used.
[ gas/testsuite/ChangeLog ]
2002-12-18 Chris Demetriou <cgd@broadcom.com>
* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
* gas/mips/rol64.s: Likewise.
* gas/mips/rol.l: New file.
* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
* gas/mips/rol64.l: New file.
* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
* gas/mips/rol-hw.d: New file.
* gas/mips/rol-hw.l: New file.
* gas/mips/rol64-hw.d: New file.
* gas/mips/rol64-hw.l: New file.
* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.
(Create_VMS_Object_File): Fix creat call for sane unix systems.
(Object_Record_Offset): Make it a size_t.
(Flush_VMS_Object_Record_Buffer): Fix signed/unsigned warning.
(VMS_TBT_Routine_End <Size>): Make var unsigned long.
(VMS_Fix_Indirect_Reference <Offset>): Make arg addressT.
(synthesize_data_segment <data_size>): Remove ATTRIBUTE_UNUSED.
(vms_fixup_data_section <data_size>): Add here instead.
* config/e-criself.c: Fix typo in last change.
Adjust callers.
(RELAX_BRANCH_RELOC_S2): Delete.
(append_insn): Use only BFD_RELOC_16_PCREL_S2 for branches.
Do not handle BFD_RELOC_16_PCREL.
(macro_build, mips_ip): Likewise.
(md_pcrel_from): Return 4 for undefined symbols regardless of
mips_pic.
(md_apply_fix3): Use only BFD_RELOC_16_PCREL_S2 for branches.
Don't dereference howto if no such relocation is available.
Do not apply hack for in-place zero addend in NEWABI.
(md_convert_frag): Use only BFD_RELOC_16_PCREL_S2 for branches.
(gas_m68hc11_warning): New function.
(gas_m68hc11_message): New function.
(top): New tests for assembler errors.
(gas_m68hc11_opcode_list): New function.
(top): New tests for opcode list.
(md_relax_table): Define specific relax for PC-rel offsets.
(build_indexed_byte): Use a STATE_INDEXED_PCREL relax code.
(m68hc11_relax_frag): Handle the new relax code.
(md_convert_frag): Likewise.
(md_estimate_size_before_relax): Likewise.
(ia64_gen_real_reloc_type): Handle it.
(pseudo_func): Add @ltoffx.
(md_begin): Build .<ltoffx>.
(ia64_force_relocation): True for LTOFF22X and LDXMOV.
* gas/ia64/ltoff22x-1.[ds]: New.
* gas/ia64/ia64.exp: Run it.
Move OBJ_COFF TC_FORCE_RELOCATION code here so that COFF handles
ARM_IMMEDIATE and ARM_ADRL_IMMEDIATE relocs as for ELF.
* config/tc-arm.h (TC_FORCE_RELOCATION): Define for both ELF and
COFF to call arm_force_relocation.
can find the real symbol and not a gas internal debug symbol.
* gas/m68hc11/insns.d: Update.
* gas/m68hc11/insns-dwarf2.d: Update.
* gas/m68hc11/insns12.d: Update.
* gas/m68hc11/opers12.s (min5b, min9b): Use 16 and -256 for the min.
* gas/m68hc11/opers12.d: Update after indexed offset operand fixes.
* gas/m68hc11/opers12-dwarf2.d: Likewise.
can find the real symbol and not a gas internal debug symbol.
* gas/m68hc11/insns.d: Update.
* gas/m68hc11/insns-dwarf2.d: Update.
* gas/m68hc11/insns12.d: Update.
* gas/m68hc11/opers12.s (min5b, min9b): Use 16 and -256 for the min.
* gas/m68hc11/opers12.d: Update after indexed offset operand fixes.
* gas/m68hc11/opers12-dwarf2.d: Likewise.
* config/tc-m68hc11.h (md_relax_frag): Define to support relaxations
that are not pc-relative.
(m68hc11_relax_frag): Declare.
* config/tc-m68hc11.c (build_indexed_byte): Use a frag_var to handle
the offsetable indexed addressing modes (n,r).
(build_insn): Cleanup some locals.
(m68hc11_relax_frag): New function imported from tc-cris.c to handle
relaxation of difference between two symbols of same section.
(md_convert_frag): For INDEXED_OFFSET relaxs, use the displacement
only when this is a PC-relative operand and the offset is not absolute.
(md_estimate_size_before_relax): Convert the INDEXED_OFFSET,UNDEF frag
to INDEXED_OFFSET,STATE_BITS5 when the symbol is absolute; this will
be handled by m68hc11_relax_frag.
(32-bit int, 64-bit double).
(md_longopts): New options -mshort, -mlong, -mshort-double and
-mlong-double to control the ABI.
(md_show_usage): Update.
(md_parse_option): Handle new options.
* doc/as.texinfo (Overview): Document new options for HC11/HC12.
* config/tc-mcore.c (md_begin): Use a const iterator. Don't
coalesce the name fields to use the same pointer.
* config/tc-sh.c (md_begin): Use a const iterator. Don't coalesce
the name fields to use the same pointer.
(get_specific): Check for opcodes with the same name using strcmp
as well as comparing the pointer.
* config/tc-h8300.c (struct h8_instruction): New type, used to
wrap h8_opcodes with length, noperands, idx, and size fields
(computed at run-time).
(h8_instructions): New variable.
(md_begin): Allocate the storage for h8_instructions. Fill
h8_instructions with pointers to the appropriate opcode and the
correct value for the additional fields.
(clever_message): Update to use h8_instructions instead of
h8_opcodes.
(build_bytes): Ditto.
(get_specific): Ditto.
(md_assemble): Ditto.
parameters. Added support for new opcode-list format. General
error message fixups.
(c4x_inst_add): Reject insn not for our CPU
(md_begin): Added matrix for setting the proper opcode-level &
device-flags according to cpu type and revision. Rewrite the
opcode hasher.
(c4x_operand_parse): Fix opcode bug
(c4x_operands_match): New function argument. Added dry-run
mechanism, that is optional error generation. Added constraint 'i'
and 'j'.
(c4x_insn_check): Added new function for post-verification of the
generated insn.
(md_assemble): Check all opcodes before croaking because of an
argument mismatch. Need this to be able to fully support
ortogonally arguments.
(md_parse_options): Revised commandprompt swicthes and added new
ones.
(md_show_usage): Complete rewrite of printout.
* gas/testsuite/gas/tic4x/addressing.s: Fix bug in one insn
* gas/testsuite/gas/tic4x/addressing_c3x.d: Update thereafter
* gas/testsuite/gas/tic4x/addressing_c4x.d: Update thereafter
* gas/testsuite/gas/tic4x/allopcodes.S: Add support for new
opclass.h changes
* gas/testsuite/gas/tic4x/opclasses.h: Added testsuites for
the new enhanced opcodes.
* gas/testsuite/gas/tic4x/opcodes.s: Regenerate
* gas/testsuite/gas/tic4x/opcodes_c3x.d: Update from above
* gas/testsuite/gas/tic4x/opcodes_c4x.d: Update from above
* gas/testsuite/gas/tic4x/opcodes_new.d: Added new testsuite for
the enhanced and special insns.
* gas/testsuite/gas/tic4x/tic4x.exp: Added the opcodes_new testsuite
* include/opcode/tic4x.h: File reordering. Added enhanced opcodes.
* opcodes/tic4x-dis.c: Added support for enhanced and special
insn.
(c4x_print_op): Added insn class 'i' and 'j'
(c4x_hash_opcode_special): Add to support special insn
(c4x_hash_opcode): Update to support the new opcode-list
format. Add support for the new special insns.
(c4x_disassemble): New opcode-list support.
(c4x_operands_match): Added check for 8-bits LDF insn. Give
warning when using constant direct bigger than 2^16. Add the new
arguments.
* include/opcode/tic4x.h: Major rewrite of entire file. Define
instruction classes, and put each instruction into a class.
* opcodes/tic4x-dis.c: (c4x_print_op): Add support for the new
argument format. Fix bug in 'N' register printer.
(cris_relax_frag): New function.
(md_estimate_size_before_relax) <case ENCODE_RELAX
(STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF)>: Pass on unresolved
expressions that will become absolute expressions to relaxation.
(md_convert_frag) <case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX,
STATE_WORD)>: Expect only absolute expressions. Use the symbol
value, not distance to symbol.
<case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE)>:
Ditto. Correct placement of fixup.
(md_assemble): Use SIMPLE_EXPR when dissecting expressions.
(gen_bdap): Ditto.
* config/tc-cris.h (cris_relax_frag): Declare.
(md_relax_frag): Define.
(mips_pseudo_table): Add .gpdword.
(mips_need_elf_addend_fixup): never for NEWABI.
(md_apply_fix3): Don't mark BFD_RELOC64 after GPREL16 or
GPREL32 as done.
(s_cpadd): Generate .cpadd on NEWABI.
