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Commit Graph

5193 Commits

Author SHA1 Message Date
Alan Modra
7d0b9ebc1e Don't include libbfd.h outside of bfd, part 6
Some messing with plugin code in order to not need arelt_size in
ld code.  File descriptor handling in ld/plugin.c is tidied too,
simply duping the open fd rather than opening the file again.

bfd/
	* elflink.c: Include plugin-api.h.
	* plugin.c (bfd_plugin_open_input): New function, extracted from..
	(try_claim): ..here.
	* plugin.h: Don't include bfd.h.
	(bfd_plugin_open_input): Declare.
binutils/
	* ar.c: Include plugin-api.h.
	* nm.c: Likewise.
ld/
	* plugin.c: Don't include libbfd.h.  Include plugin-api.h
	before bfd/plugin.h.
	(plugin_object_p): Use bfd_plugin_open_input.
2016-07-16 19:09:00 +09:30
Alan Modra
4212b42d79 Don't include libbfd.h outside of bfd, part 4
Not much to see here, just renaming a function.

bfd/
	* targets.c (bfd_seach_for_target): Rename to..
	(bfd_iterate_over_targets): ..this.  Rewrite doc.
	* bfd-in2.h: Regenerate.
ld/
	* ldlang.c (open_output): Replace bfd_search_for_target with
	bfd_iterate_over_targets.  Localize vars.
2016-07-16 13:29:35 +09:30
Alan Modra
76e7a75123 Don't include libbfd.h outside of bfd, part 1
Make BFD_ALIGN available to objcopy.  Fix assertions.  Don't use
bfd_log2 in ppc32elf.em or bfd_malloc in xtensaelf.em and bucomm.c.

bfd/
	* libbfd-in.h (BFD_ALIGN): Move to..
	* bfd-in.h: ..here.
	* elf32-ppc.h (struct ppc_elf_params): Add pagesize.
	* elf32-ppc.c (default_params): Adjust init.
	(ppc_elf_link_params): Set pagesize_p2.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
binutils/
	* ar.c: Don't include libbfd.h.
	* objcopy.c: Likewise.
	* bucomm.c (bfd_get_archive_filename): Use xmalloc rather than
	bfd_malloc.
gas/
	* config/bfin-parse.y: Don't include libbfd.h.
	* config/tc-bfin.c: Likewise.
	* config/tc-rl78.c: Likewise.
	* config/tc-rx.c: Likewise.
	* config/tc-metag.c: Likewise.
	(create_dspreg_htabs, create_scond_htab): Use gas_assert not BFD_ASSERT.
	* Makefile.am: Update dependencies.
	* Makefile.in: Regenerate.
ld/
	* ldlang.c: Don't include libbfd.h.
	* emultempl/nds32elf.em: Likewise.
	* emultempl/ppc64elf.em: Likewise.
	* emultempl/ppc32elf.em: Likewise.
	(pagesize): Delete.
	(params): Update init.
	(ppc_after_open_output): Use params.pagesize.  Don't call bfd_log2.
	(PARSE_AND_LIST_ARGS_CASES): Use params.pagesize.
	* emultempl/sh64elf.em: Don't include libbfd.h.
	(after_allocation): Use ASSERT, not BFD_ASSERT.
	* emultempl/xtensaelf.em: Don't include libbfd.h.
	(replace_insn_sec_with_prop_sec): Use xmalloc, not bfd_malloc.
	* Makefile.am: Update dependencies.
	* Makefile.in: Regenerate.
2016-07-16 13:25:11 +09:30
Thomas Preud'homme
7635954182 Add support for creating ELF import libraries
2016-07-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
	* elf-bfd.h (elf_backend_filter_implib_symbols): Declare backend hook.
	(_bfd_elf_filter_global_symbols): Declare.
	* elf.c (_bfd_elf_filter_global_symbols): New function.
	* elflink.c (elf_filter_global_symbols): Likewise.
	(elf_output_implib): Likewise.
	(bfd_elf_final_link): Call above function, failing if it does.
	* elfxx-target.h (elf_backend_filter_implib_symbols): Define macro and
	default it to NULL.
	(elf_backend_copy_indirect_symbol): Fix spacing.
	(elf_backend_hide_symbol): Likewise.
	(elfNN_bed): Initialize elf_backend_filter_implib_symbols backend hook.

include/
	* bfdlink.h (struct bfd_link_info): Declare new ldscript_def and
	out_implib_bfd fields.

2016-07-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
	    Nick Clifton  <nickc@redhat.com>

ld/
	* emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Open import
	library file for writing and initialize implib_bfd field of link_info
	structure.
	* emultempl/pe.em (pe_implib_filename): Remove variable declaration.
	(OPTION_IMPLIB_FILENAME): Remove macro definition.
	(gld${EMULATION_NAME}_add_options): Remove --out-implib option.
	(gld_${EMULATION_NAME}_list_options): Likewise.
	(gld${EMULATION_NAME}_handle_option): Likewise.
	(gld_${EMULATION_NAME}_finish): Use command_line.out_implib_filename
	instead of pe_implib_filename.
	* emultempl/pep.em (pep_implib_filename): Remove variable declaration.
	(OPTION_IMPLIB_FILENAME): Remove enumerator.
	(gld${EMULATION_NAME}_add_options): Remove --out-implib option.
	(gld_${EMULATION_NAME}_list_options): Likewise.
	(gld${EMULATION_NAME}_handle_option): Likewise.
	(gld_${EMULATION_NAME}_finish): Use command_line.out_implib_filename
	instead of pep_implib_filename.
	* ld.h (args_type): Declare new out_implib_filename field.
	* ld.texinfo (--out-implib): Move documentation to arch-independent
	part and rephrase to apply to ELF targets.
	* ldexp.c (exp_fold_tree_1): Set ldscript_def field to 1 for symbols
	defined in linker scripts.
	* ldlex.h (enum option_values): Declare new OPTION_OUT_IMPLIB
	enumerator.
	* lexsup.c (ld_options): Add entry for new --out-implib switch.
	(parse_args): Handle OPTION_OUT_IMPLIB case.
	* testsuite/ld-elf/elf.exp (Generate empty import library): New test.
	(Generate import library): Likewise.
	* testsuite/ld-elf/implib.s: Likewise.
	* testsuite/ld-elf/implib.rd: New file.
	* testsuite/ld-elf/empty-implib.out: Likewise
2016-07-15 17:50:48 +01:00
Nick Clifton
f7e8b360fe Tidy up debugging in the ARC port of the BFD library.
bfd	* elf32-arc.c (PR_DEBUG): Delete.
	Fix printing of debug information.  Fix formatting of debug
	statements.
	(debug_arc_reloc): Handle symbols that are not from an input file.
	(arc_do_relocation): Remove excessive exclamation points.
	(elf_arc_relocate_section): Print an informative message if the
	relocation fails, even if debugging is not enabled.
	* arc-got.h: Fix formatting.  Fix printing of debug information.
	(new_got_entry_to_list): Use xmalloc.
	* config.bfd: use the big-endian arc vector as the default vector
	for big-endian arc targets.

ld	* testsuite/ld-arc/arc.exp: Always run the sda-relocs test in
	little endian mode.
2016-07-15 12:00:03 +01:00
Maciej W. Rozycki
b416ba9b50 MIPS/GAS: Don't convert PC-relative REL relocs against absolute symbols
Don't convert PC-relative REL relocations against absolute symbols to
section-relative references and retain the original symbol reference
instead.  Offsets into the absolute section may overflow the limited
range of their in-place addend field, causing an assembly error, e.g.:

$ cat test.s
	.text
	.globl	foo
	.ent	foo
foo:
	b	bar
	.end	foo

	.set	bar, 0x12345678
$ as -EB -32 -o test.o test.s
test.s: Assembler messages:
test.s:3: Error: relocation overflow
$

With the original reference retained the source can now be assembled and
linked successfully:

$ as -EB -32 -o test.o test.s
$ objdump -dr test.o

test.o:     file format elf32-tradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	1000ffff 	b	0 <foo>
			0: R_MIPS_PC16	bar
   4:	00000000 	nop
	...
$ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o
$ objdump -dr test

test:     file format elf32-tradbigmips

Disassembly of section .text:

12340000 <foo>:
12340000:	1000159d 	b	12345678 <bar>
12340004:	00000000 	nop
	...
$

For simplicity always retain the original symbol reference, even if it
would indeed fit.

Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes
R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch
relocations against absolute symbols to be converted on RELA targets to
section-relative references.  This is an intended effect of this change.
Absolute symbols carry no ISA annotation in their `st_other' field and
their value is not going to change with linker relaxation, so it is safe
to discard the original reference and keep the calculated final symbol
value only in the relocation's addend.

Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring
absolute symbols can be safely converted even on REL targets, as there
the in-place addend of these relocations covers the entire 32-bit
address space so it can hold the calculated final symbol value, and
likewise the value referred won't be affected by any linker relaxation.

Add a set of suitable test cases and enable REL linker tests which now
work and were previously used as dump patterns for RELA tests only.

	gas/
	* config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro.
	(mips_force_relocation_abs): New prototype.
	* config/tc-mips.c (mips_force_relocation_abs): New function.
	* testsuite/gas/mips/branch-absolute.d: Adjust dump patterns.
	* testsuite/gas/mips/mips16-branch-absolute.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
	Likewise.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
	Likewise.
	* testsuite/gas/mips/branch-absolute-addend.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-addend.d: New test.
	* testsuite/gas/mips/micromips-branch-absolute-addend.d: New
	test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/mips-elf.exp: Run
	`branch-absolute-addend', `mips16-branch-absolute',
	`mips16-branch-absolute-addend' and
	`micromips-branch-absolute-addend'.
2016-07-14 20:11:03 +01:00
Maciej W. Rozycki
96e9ba5fbb MIPS/GAS: Keep the ISA bit in the addend of branch relocations
Correct a problem with the ISA bit being stripped from the addend of
compressed branch relocations, affecting RELA targets.  It has been
there since microMIPS support has been added, with:

commit df58fc944d
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date:   Sun Jul 24 14:20:15 2011 +0000

<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS:
microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and
R_MICROMIPS_PC16_S1 relocations originally affected, and the
R_MIPS16_PC16_S1 relocation recently added with commit c9775dde32
("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually
triggering a linker error, due to its heightened processing strictness
level:

$ cat test.s
	.text
	.set	mips16
foo:
	b	bar

	.set	bar, 0x1235
	.align	4, 0
$ as -EB -n32 -o test.o test.s
$ objdump -dr test.o

test.o:     file format elf32-ntradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	f000 1000 	b	4 <foo+0x4>
			0: R_MIPS16_PC16_S1	*ABS*+0x1230
	...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o
test.o: In function `foo':
(.text+0x0): Branch to a non-instruction-aligned address
$

This is because the ISA bit of the branch target does not match the ISA
bit of the referring branch, hardwired to 1 of course.

Retain the ISA bit then, so that the linker knows this is really MIPS16
code referred:

$ objdump -dr fixed.o

fixed.o:     file format elf32-ntradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	f000 1000 	b	4 <foo+0x4>
			0: R_MIPS16_PC16_S1	*ABS*+0x1231
	...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o
$

Add a set of MIPS16 tests to cover the relevant cases, excluding linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.

	gas/
	* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1>
	<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
	<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the
	addend calculated.
	* testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit
	in `bar', export `foo'.
	* testsuite/gas/mips/mips16-branch-absolute.d: Adjust
	accordingly.
	* testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise.
	* testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise.
	* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d:
	Likewise.
	* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d:
	Likewise.

	ld/
	* testsuite/ld-mips-elf/mips16-branch-absolute.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New
	test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New
	test.
	* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New
	test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
	from `mips16-branch-absolute' and
	`mips16-branch-absolute-addend', referred indirectly only.
2016-07-14 20:08:59 +01:00
Maciej W. Rozycki
0c11728627 BFD: Let targets handle relocations against absolute symbols
Fix a generic BFD issue with relocations against absolute symbols, which
are installed without using any individual relocation handler provided
by the backend.  This causes any absolute section's addend to be lost on
REL targets such as o32 MIPS, and also relocation-specific calculation
adjustments are not made.

As an example assembling this program:

$ cat test.s
	.text
foo:
	b	bar
	b	baz

	.set	bar, 0x1234
$ as -EB -32 -o test-o32.o test.s
$ as -EB -n32 -o test-n32.o test.s

produces this binary code:

$ objdump -dr test-o32.o test-n32.o

test-o32.o:     file format elf32-tradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	10000000 	b	4 <foo+0x4>
			0: R_MIPS_PC16	*ABS*
   4:	00000000 	nop
   8:	1000ffff 	b	8 <foo+0x8>
			8: R_MIPS_PC16	baz
   c:	00000000 	nop

test-n32.o:     file format elf32-ntradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	10000000 	b	4 <foo+0x4>
			0: R_MIPS_PC16	*ABS*+0x1230
   4:	00000000 	nop
   8:	10000000 	b	c <foo+0xc>
			8: R_MIPS_PC16	baz-0x4
   c:	00000000 	nop
$

where it is clearly visible in `test-o32.o', which uses REL relocations,
that the absolute section's addend equivalent to the value of `bar' -- a
reference to which cannot be fully resolved at the assembly time,
because the reference is PC-relative -- has been lost, as has been the
relocation-specific adjustment of -4, required to take into account the
PC+4-relative calculation made by hardware with branches and seen in the
external symbol reference to `baz' as the `ffff' addend encoded in the
instruction word.  In `test-n32.o', which uses RELA relocations, the
absolute section's addend has been correctly retained.

Give precedence then in `bfd_perform_relocation' and
`bfd_install_relocation' to any individual relocation handler the
backend selected may have provided, while still resorting to the generic
calculation otherwise.  This retains the semantics which we've had since
forever or before the beginning of our repository history, and is at the
very least compatible with `bfd_elf_generic_reloc' being used as the
handler.

Retain the `bfd_is_und_section' check unchanged at the beginning of
`bfd_perform_relocation' since this does not affect the semantics of the
function.  The check returns the same `bfd_reloc_undefined' code the
check for a null `howto' does, so swapping the two does not matter.
Also the check is is mutually exclusive with the `bfd_is_abs_section'
check, since a section cannot be absolute and undefined both at once, so
swapping the two does not matter either.

With this change applied the program quoted above now has the in-place
addend correctly calculated and installed in the field being relocated:

$ objdump -dr fixed-o32.o

fixed-o32.o:     file format elf32-tradbigmips

Disassembly of section .text:

00000000 <foo>:
   0:	1000048c 	b	1234 <bar>
			0: R_MIPS_PC16	*ABS*
   4:	00000000 	nop
   8:	1000ffff 	b	8 <foo+0x8>
			8: R_MIPS_PC16	baz
   c:	00000000 	nop
$

Add a set of MIPS tests to cover the relevant cases, including absolute
symbols with addends, and verifying that PC-relative relocations against
symbols concerned resolve to the same value in the final link regardless
of whether the REL or the RELA relocation form is used.  Exclude linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.

	bfd/
	* reloc.c (bfd_perform_relocation): Try the `howto' handler
	first with relocations against absolute symbols.
	(bfd_install_relocation): Likewise.

	gas/
	* testsuite/gas/mips/mips16-branch-absolute.d: Update patterns.
	* testsuite/gas/mips/branch-absolute.d: New test.
	* testsuite/gas/mips/branch-absolute-n32.d: New test.
	* testsuite/gas/mips/branch-absolute-n64.d: New test.
	* testsuite/gas/mips/branch-absolute-addend-n32.d: New test.
	* testsuite/gas/mips/branch-absolute-addend-n64.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-n32.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-n64.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d: New
	test.
	* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d: New
	test.
	* testsuite/gas/mips/micromips-branch-absolute.d: New test.
	* testsuite/gas/mips/micromips-branch-absolute-n32.d: New test.
	* testsuite/gas/mips/micromips-branch-absolute-n64.d: New test.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: New
	test.
	* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: New
	test.
	* testsuite/gas/mips/branch-absolute.s: New test source.
	* testsuite/gas/mips/branch-absolute-addend.s: New test source.
	* testsuite/gas/mips/mips16-branch-absolute-addend.s: New test
	source.
	* testsuite/gas/mips/micromips-branch-absolute.s: New test
	source.
	* testsuite/gas/mips/micromips-branch-absolute-addend.s: New
	test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/branch-absolute.d: New test.
	* testsuite/ld-mips-elf/branch-absolute-n32.d: New test.
	* testsuite/ld-mips-elf/branch-absolute-n64.d: New test.
	* testsuite/ld-mips-elf/branch-absolute-addend.d: New test.
	* testsuite/ld-mips-elf/branch-absolute-addend-n32.d: New test.
	* testsuite/ld-mips-elf/branch-absolute-addend-n64.d: New test.
	* testsuite/ld-mips-elf/micromips-branch-absolute.d: New test.
	* testsuite/ld-mips-elf/micromips-branch-absolute-n32.d: New
	test.
	* testsuite/ld-mips-elf/micromips-branch-absolute-n64.d: New
	test.
	* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: New
	test.
	* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n32.d:
	New test.
	* testsuite/ld-mips-elf/micromips-branch-absolute-addend-n64.d:
	New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
	from `branch-absolute-addend' and
	`micromips-branch-absolute-addend', referred indirectly only.
2016-07-14 20:06:37 +01:00
Claudiu Zissulescu
fa1c017017 [ARC] Fix/improve small data support.
The R_ARC_SDA32 is wrongly described as a ME relocation, fix it.  Offset the
__SDATA_BEGIN__ to take advantage of the signed 9-bit field of the
load/store instructions.

include/
2016-07-08  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.

ld/
2016-07-08  Claudiu Zissulescu  <claziss@synopsys.com>

	* emulparams/arcelf.sh (SDATA_START_SYMBOLS): Add offset.
	* testsuite/ld-arc/sda-relocs.dd: New file.
	* testsuite/ld-arc/sda-relocs.ld: Likewise.
	* testsuite/ld-arc/sda-relocs.rd: Likewise.
	* testsuite/ld-arc/sda-relocs.s: Likewise.
	* testsuite/ld-arc/arc.exp: Add SDA tests.
2016-07-14 10:08:57 +02:00
Claudiu Zissulescu
764cfd4ad7 [ARC] Update test.
ld/
2016-07-11  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/ld-arc/nps-1b.err: Update test to handle more
	verbosity.
2016-07-11 15:41:23 +02:00
Alan Modra
32a0481fb1 PR20337, Objdump makes poor choice of symbols
binutils/
	PR binutils/20337
	* objdump.c (compare_symbols): For ELF, sort same value/type
	symbols according to size.
ld/
	* testsuite/ld-powerpc/elfv2exe.d: Update.
2016-07-09 16:53:33 +09:30
jamesbowman
3a5ce9503e FT32 linker script cleanup
Fix a typo (__PMSIZE was written as __PMSIZE_) and add section alignment
for DATA and BSS.

ld/ChangeLog:

  * scripttempl/ft32.sc (__PMSIZE): Correct __PMSIZE_.
    (DATA): add ALIGN.
    (BSS): add ALIGN
2016-07-06 18:58:10 -07:00
H.J. Lu
29d7478bc6 Add -flto to PR ld/20321 test
Before GCC 4.9, -flto is required for final LTO link.  Add -flto to PR
ld/20321 test to support older versions of GCC.

	* testsuite/ld-plugin/lto.exp: Add -flto to PR ld/20321 test.
2016-07-05 07:35:52 -07:00
Andre Vieria
d5a67c0290 [ARM] Purecode compatible long branch veneer for M-profile targets with MOVW.
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

	* elf32-arm.c (THUMB32_MOVT): New veneer macro.
	(THUMB32_MOVW): Likewise.
	(elf32_arm_stub_long_branch_thumb2_only_pure): New.
	(DEF_STUBS): Define long_branch_thumb2_only_pure.
	(arm_stub_is_thumb): Add new veneer stub.
	(arm_type_of_stub): Use new veneer.
	(arm_stub_required_alignment): Add new veneer.

2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

	* testsuite/ld-arm/farcall-thumb2-purecode.d: New test result.
	* testsuite/ld-arm/farcall-thumb2-purecode.s: New test.
	* testsuite/ld-arm/arm-elf.exp: Run it.
2016-07-05 11:39:06 +01:00
Andre Vieria
f0728ee368 [ARM] Change noread to purecode.
bfd/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * bfd-in2.h (SEC_ELF_NOREAD): Rename to ...
          (SEC_ELF_PURECODE): ... this.
        * elf32-arm.c (elf32_arm_post_process_headers): Rename SEC_ELF_NOREAD
          to SEC_ELF_NOREAD.
          (elf32_arm_fake_sections): Likewise.
          (elf_32_arm_section_flags): Likewise.
          (elf_32_arm_lookup_section_flags): Likewise.
        * section.c (SEC_ELF_NOREAD): Rename to ...
          (SEC_ELF_PURECODE): ... this.

binutils/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * objdump.c (dump_section_header): Rename SEC_ELF_NOREAD
          to SEC_ELF_NOREAD.
        * readelf.c (get_elf_section_flags): Rename ARM_NOREAD to
          ARM_PURECODE and SHF_ARM_NOREAD to SHF_ARM_PURECODE.
          (process_section_headers): Rename noread to purecode.

        * section.c (SEC_ELF_NOREAD): Rename to ...
          (SEC_ELF_PURECODE): ... this.

include/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * elf/arm.h (SHF_ARM_NOREAD): Rename to ...
          (SHF_ARM_PURECODE): ... this.

ld/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * testsuite/ld-arm/arm_noread.ld: Renamed to ...
          testsuite/ld-arm/arm_purecode.ld: ... this, and replaced
          all noread's by purecode.
2016-07-05 11:28:46 +01:00
Jan Beulich
1753ed6811 ld: track linker-definedness of symbols
Keep "lineno" as zero while not processing any script, and use it being
zero to set the "linker_def" field to true.
2016-07-05 11:36:08 +02:00
H.J. Lu
c3e1c28ebf Warn and return for duplicated plugin
If a plugin has been loaded already, we should warn and return, instead
of adding it on the plugin list.

	PR ld/20321
	* plugin.c (plugin_opt_plugin): Warn and return if plugin has
	been loaded already.
	* testsuite/ld-plugin/lto.exp: Run PR ld/20321 test.
	* testsuite/ld-plugin/pr20321.c: New file.
2016-07-04 08:55:20 -07:00
Nick Clifton
1dc8bf195d Allow the flash and ram memory region sizes to be specified in the default FT32 linker script.
* scripttempl/ft32.sc (__PMSIZE_): If not defined, set to 256K.
	(__RAMSIZE): If not defined, set to 64K.
	(MEMORY): Set the flash region size to __PMSIZE and the ram region
	size to __RAMSIZE.
2016-07-04 15:44:10 +01:00
Maciej W. Rozycki
6f50d61158 MIPS/LD/testsuite: Resurrect `branch-misc-2' test
Revert:

commit c9c1e416d7
Author: Alexandre Oliva <aoliva@redhat.com>
Date:   Thu Dec 12 04:39:44 2002 +0000

<https://sourceware.org/ml/binutils/2002-11/msg00657.html>, ("mips:
branches to external labels are broken"), complementing:

commit bad36eacda
Author: Daniel Jacobowitz <drow@false.org>
Date:   Wed Nov 23 14:04:18 2005 +0000

<https://sourceware.org/ml/binutils/2005-11/msg00324.html>,
("R_MIPS_PC16, again").

	ld/
	* testsuite/ld-mips-elf/branch-misc-2.d: New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run it.
2016-07-02 23:16:41 +01:00
Thomas Preud'homme
5e866f5aee Fix Thumb-2 BL detection
2016-07-01  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
	* elf32-arm.c (using_thumb2_bl): New function.
	(arm_type_of_stub): Declare thumb2 variable together and change type
	to bfd_boolean.  Use using_thumb2_bl () to determine whether
	THM_MAX_FWD_BRANCH_OFFSET or THM2_MAX_FWD_BRANCH_OFFSET should be
	checked for BL range.
	(elf32_arm_final_link_relocate): Use using_thumb2_bl () to determine
	the bit size of BL offset.

ld/
	* testsuite/ld-arm/arm-elf.exp (Thumb-2 BL): Assemble for ARMv7.
	(Thumb-2 BL on ARMv6-M): New testcase.
	* testsuite/ld-arm/thumb2-bl.d: Do not try to match testcase filename.
	* testsuite/ld-arm/thumb2-bl.s: Do not select architecture.
2016-07-01 16:13:25 +01:00
Tristan Gingold
96a84ea350 Add marker for 2.27 branch.
binutils/
2016-07-01  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.27.

gas/
2016-07-01  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.27.

ld/
2016-07-01  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.27.
2016-07-01 10:58:29 +02:00
H.J. Lu
f4ab0e2d1d Skip version check for unreferenced and undefined symbol
No need to check version if symbol is unreferenced and undefined.

bfd/

	PR ld/20306
	* elflink.c (elf_link_check_versioned_symbol): Return false
	for unreferenced undefined symbol.

ld/testsuite/

	* testsuite/ld-gc/gc.exp: Run pr20306 test.
	* ld-gc/pr20306.c: New file.
	* ld-gc/pr20306.d: Likewise.
2016-06-28 08:08:30 -07:00
Nick Clifton
1b857aeed3 Fix more linker testsuite failures.
bfin	* elf32-bfin.c (bfin_adjust_dynamic_symbol): Fail if a COPY reloc
	is needed.

ld	* testsuite/ld-elf/comm-data.exp: Expect comm-data2 test to fail
	for bfin.
	* testsuite/ld-elf/elf.exp: Expect pr14170 and symbolic function
	tests to fail for bfin.
	* testsuite/ld-elf/endsym.d: Expect to fail with cr16, crx, dlx,
	nds32 and visium.
	* testsuite/ld-elf/var1.d: Expect to fail with d30v, dlx, ft32 and
	microblaze.
	* testsuite/ld-pe/pe.exp: Expect foreign symbol test to fail for
	mcore-pe.
2016-06-28 15:55:22 +01:00
Nick Clifton
8b9a915daf Fix RX and M68HC11 linker testsuite failures.
ld	* testsuite/ld-elf/merge.d: Add m68hc11 to list of targets that
	expect to fail this test.
	* testsuite/ld-scripts/overlay-size.d: Skip the entire test for
	RX.
	* testsuite/ld-scripts/rgn-at10.d: No longer expect this test to
	fail for the RX.
	* testsuite/ld-scripts/rgn-at11.d: Likewise.
	* testsuite/ld-scripts/rgn-at2.d: Likewise.
	* testsuite/ld-scripts/rgn-at6.d: Likewise.
	* testsuite/ld-scripts/rgn-at7.d: Likewise.
	* testsuite/ld-scripts/rgn-at8.d: Likewise.
2016-06-28 12:43:14 +01:00
James Clarke
7160c10d65 Don't convert R_SPARC_32 to R_SPARC_RELATIVE if class is ELFCLASS64.
bfd	* elfxx-sparc.c (_bfd_sparc_elf_relocate_section): Don't convert
	R_SPARC_32 to R_SPARC_RELATIVE if class is ELFCLASS64.

gold	* sparc.cc (Target_sparc::Scan::local): Don't convert R_SPARC_32
	to R_SPARC_RELATIVE if class is ELFCLASS64.
	(Target_sparc::Scan::global): Likewise.

ld	* testsuite/ld-elf/symbolic-func.r: Allow non-zero offsets from
	.text.
2016-06-28 12:00:56 +01:00
Maciej W. Rozycki
6c9a7fb62f MIPS/LD/testsuite: Accept any UNIX OS/ABI with GNU attribute tests
Remove failures with FreeBSD targets, e.g:

regexp_diff match failure
regexp "^  OS/ABI:                            UNIX - System V$"
line   "  OS/ABI:                            UNIX - FreeBSD"
FAIL: ld-mips-elf/attr-gnu-4-50

introduced with commit 351cdf24d2 ("[MIPS] Implement O32 FPXX, FP64
and FP64A ABI extensions").

	ld/
	* testsuite/ld-mips-elf/attr-gnu-4-10.d: Match any UNIX OS/ABI.
	* testsuite/ld-mips-elf/attr-gnu-4-50.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-60.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-70.d: Likewise.
2016-06-28 11:10:21 +01:00
Alan Modra
56a30421ee Don't run ld-scripts/pr20302 on linuxaout
PR ld/20302
	* testsuite/ld-scripts/pr20302.d: Exclude *-*-*aout.
2016-06-28 19:09:11 +09:30
Maciej W. Rozycki
c9775dde32 MIPS16: Add R_MIPS16_PC16_S1 branch relocation support
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1'
and the usual MIPS16 bit shuffling applies to relocated field handling,
as per the encoding of the branch target in the extended form of the
MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions.

	include/
	* elf/mips.h (R_MIPS16_PC16_S1): New relocation.

	bfd/
	* elf32-mips.c (elf_mips16_howto_table_rel): Add
	R_MIPS16_PC16_S1.
	(mips16_reloc_map): Likewise.
	* elf64-mips.c (mips16_elf64_howto_table_rel): Likewise.
	(mips16_elf64_howto_table_rela): Likewise.
	(mips16_reloc_map): Likewise.
	* elfn32-mips.c (elf_mips16_howto_table_rel): Likewise.
	(elf_mips16_howto_table_rela): Likewise.
	(mips16_reloc_map): Likewise.
	* elfxx-mips.c (mips16_branch_reloc_p): New function.
	(mips16_reloc_p): Handle R_MIPS16_PC16_S1.
	(b_reloc_p): Likewise.
	(mips_elf_calculate_relocation): Likewise.
	(_bfd_mips_elf_check_relocs): Likewise.
	* reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

	gas/
	* config/tc-mips.c (mips16_reloc_p): Handle
	BFD_RELOC_MIPS16_16_PCREL_S1.
	(b_reloc_p): Likewise.
	(limited_pcrel_reloc_p): Likewise.
	(md_pcrel_from): Likewise.
	(md_apply_fix): Likewise.
	(tc_gen_reloc): Likewise.
	(md_convert_frag): Likewise.
	(mips_fix_adjustable): Update comment.
	* testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-addend-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-addend-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-absolute.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file.
	* testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-2.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-3.l: Remove file.
	* testsuite/gas/mips/mips16-branch-absolute.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-2.s: Add padding.
	* testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid
	implicit instruction padding, avoid MIPS16 JR->JRC conversion.
	* testsuite/gas/mips/branch-weak-6.d: New test.
	* testsuite/gas/mips/branch-weak-7.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/mips16-branch-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-3.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test.
	* testsuite/ld-mips-elf/mips16-branch.s: New test source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-28 01:29:56 +01:00
Nick Clifton
42b7a39bf6 Allow a second -T<section>=<addr> to override a previous version on the same linker command line.
PR ld/20302
	* lexsup.c (set_segment_start): If resetting the start address of
	a section, remember to generate a new script element as well.
	* testsuite/ld-scripts/pr20302.d: New test.
	* testsuite/ld-scripts/scripts.exp: Run the new test.
2016-06-27 16:35:58 +01:00
Alan Modra
78da3bc1ee aarch64 ld testsuite
Fixes failure on aarch64-rtems.

	* testsuite/ld-aarch64/aarch64-elf.exp (aarch64_choose_ilp32_emul):
	Don't error out, always return an emulation.
2016-06-24 23:05:48 +09:30
H.J. Lu
da4463c7d7 Check DEFAULT_LD_Z_RELRO for -z relro help message
* lexsup.c (elf_shlib_list_options): Check DEFAULT_LD_Z_RELRO
	for -z relro help message.
2016-06-24 05:21:43 -07:00
Maciej W. Rozycki
4041bc9b02 MIPS/LD/testsuite: Use wildcard address matching in `undefweak-overflow'
So that test case updates result in legible dump pattern changes.

	ld/
	* testsuite/ld-mips-elf/undefweak-overflow.d: Use wildcard
	address matching.
2016-06-23 00:46:16 +01:00
Maciej W. Rozycki
4861b80420 MIPS/LD/testsuite: Uniquely identify `undefweak-overflow' tests
ld/
	* testsuite/ld-mips-elf/mips-elf.exp: Uniquely identify
	`undefweak-overflow' tests.
2016-06-23 00:43:14 +01:00
H.J. Lu
647e4d4649 ld: Add a linker configure option --enable-relro
Add a configure option --enable-relro to decide whether -z relro should
be enabled in ELF linker by default.  Default to yes for all Linux
targets, except FRV, HPPA, IA64 and MIPS, since many relro tests fail
on these targets.

	PR ld/20283
	* NEWS: Mention --enable-relro.
	* configure.ac: Add --enable-relro.
	(DEFAULT_LD_Z_RELRO): New.  Set by --enable-relro.
	* configure.tgt (ac_default_ld_z_relro): Default it to 1 for
	some Linux targets.
	* config.in: Regenerated.
	* configure: Likewise.
	* emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set
	link_info.relro to DEFAULT_LD_Z_RELRO.
	* testsuite/config/default.exp (ld_elf_shared_opt): New.
	* testsuite/lib/ld-lib.exp (run_dump_test): Pass
	$ld_elf_shared_opt to ld for ELF targets with shared object
	support.
	(run_ld_link_tests): Likewise.
2016-06-22 05:37:38 -07:00
Maciej W. Rozycki
5f68df25f8 MIPS/BFD: Don't stop processing on a cross-mode jump conversion error
As with commit ed53407eec ("MIPS/BFD: Don't stop processing on
`bfd_reloc_outofrange'") don't bail out right away and instead continue
processing on a cross-mode jump conversion error, so that any further
issues are also reported.  Adjust message formatting accordingly, using
`%X' to abort processing at conclusion.  Remove the full stop from the
end of the message, for consistency across error reporting.

Adjust the corresponding test case accordingly and make it trigger the
error twice.

	bfd/
	* elfxx-mips.c (mips_elf_perform_relocation): Call
	`info->callbacks->einfo' rather than `*_bfd_error_handler' and
	use the `%X%H' format for the cross-mode jump conversion error
	message.  Remove the full stop from the end of the message.
	Continue processing rather than returning failure.

	ld/
	* testsuite/ld-mips-elf/mode-change-error-1a.s: Trigger an error
	twice rather than once.
	* testsuite/ld-mips-elf/mode-change-error-1.d: Adjust
	accordingly.  Remove the full stop from the end of the message.
2016-06-21 14:18:23 +01:00
Graham Markall
bdd582dbf1 Arc assembler: Convert nps400 from a machine type to an extension.
gas	* config/tc-arc.c (check_cpu_feature, md_parse_option):
	Add nps400 option and feature. Add check for nps400
	feature. Refactor existing checks to check subclass before
	feature enablement.
	(md_show_usage): Document flags for NPS-400 and add some other
	undocumented flags.
	(cpu_type): Remove nps400 CPU type entry
	(check_zol): Remove bfd_mach_arc_nps400 case.
	(md_show_usage): Add help on -mcpu=nps400.
	(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
	set.
	* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
	-fpuda flags.  Document -mcpu=nps400.
	* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
	expected flags to match ARC700 instead of NPS400.
	* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
	* testsuite/gas/arc/nps-400-2.d: Likewise.
	* testsuite/gas/arc/nps-400-3.d: Likewise.
	* testsuite/gas/arc/nps-400-4.d: Likewise.
	* testsuite/gas/arc/nps-400-5.d: Likewise.
	* testsuite/gas/arc/nps-400-6.d: Likewise.
	* testsuite/gas/arc/nps-400-7.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
	avoid clash with cbba instruction.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
	-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.

binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
	case.

ld	* testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
	* testsuite/ld-arc/nps-1b.d: Likewise.

include	* opcode/arc.h: Add nps400 extension and instruction
	subclass.
	Remove ARC_OPCODE_NPS400
	* elf/arc.h: Remove E_ARC_MACH_NPS400

opcodes	* arc-dis.c (arc_insn_length): Add comment on instruction length.
	Use same method for determining	instruction length on ARC700 and
	NPS-400.
	(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
	* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
	with the NPS400 subclass.
	* arc-opc.c: Likewise.

bfd	* archures.c: Remove bfd_mach_arc_nps400.
	* bfd-in2.h: Likewise.
	* cpu-arc.c (arch_info_struct): Likewise.
	* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
	Likewise.
2016-06-21 14:03:08 +01:00
H.J. Lu
7dc3990e40 Use the IR symbol table for the IR input object
ELF linker shouldn't skip the IR object when searching the symbol table
of an archive element.  If linker doesn't know if the object file is an
IR object, it should give LTO plugin a chance to get the correct symbol
table and use the IR symbol table if the input is an IR object.

bfd/

	PR ld/18250
	PR ld/20267
	* elflink.c: Include plugin.h if BFD_SUPPORTS_PLUGINS is
	defined.
	(elf_link_is_defined_archive_symbol): Call
	bfd_link_plugin_object_p on unknown plugin object and use the
	IR symbol table if the input is an IR object.
	* plugin.c (bfd_link_plugin_object_p): New function.
	* plugin.h (bfd_link_plugin_object_p): New prototype.

ld/

	PR ld/20267
	* testsuite/ld-plugin/lto.exp (lto_link_tests): Add test for
	PR ld/20267.
	(lto_run_tests): Likewise.
	* testsuite/ld-plugin/pr20267a.c: New file.
	* testsuite/ld-plugin/pr20267b.c: Likewise.
2016-06-20 05:10:46 -07:00
Alan Modra
0616a28038 PR ld/20276: Set non_ir_ref on common symbol
Also, don't check alignment on symbol from plugin dummy input.

bfd/
	PR ld/20276
	* elflink.c (elf_link_add_object_symbols): Don't check alignment
	on symbol from plugin dummy input.
ld/
	PR ld/20276
	* plugin.c (plugin_notice): Set non_ir_ref on common symbols.
	* testsuite/ld-plugin/lto.exp (lto_link_tests): Add test for
	PR ld/20276.
	(lto_run_tests): Likewise.
	* testsuite/ld-plugin/pass.out: New file.
	* testsuite/ld-plugin/pr20276a.c: Likewise.
	* testsuite/ld-plugin/pr20276b.c: Likewise.
2016-06-20 11:26:13 +09:30
H.J. Lu
49f30d83f6 Rename bfd_plugin_uknown to bfd_plugin_unknown
bfd/

	* bfd.c (bfd_plugin_format): Rename bfd_plugin_uknown to
	bfd_plugin_unknown.
	* bfd-in2.h: Regenerated.
	* plugin.c (bfd_plugin_object_p): Replace bfd_plugin_uknown
	with bfd_plugin_unknown.

ld/

	* plugin.c (plugin_object_p): Replace bfd_plugin_uknown
	with bfd_plugin_unknown.
2016-06-18 14:15:31 -07:00
H.J. Lu
233cc9c13a Don't generate PLT for IFUNC GOT/pointer reference
If a backend supports it, PLT entry isn't needed when all references
to a STT_GNU_IFUNC symbols are done via GOT or static function pointers.
For GOT entries, We generate dynamic R_*_GLOB_DAT relocations for
preemptable symbols and R_*_IRELATIVE relocations for non-preemptable
symbols to update them with real function address.  For static pointer
pointers, we generate dynamic pointer relocations and store them in:

1. .rel[a].ifunc section in PIC object.
2. .rel[a].got section in dynamic executable.
3. .rel[a].iplt section in static executable.

We don't allocate GOT entry if it isn't used.

bfd/

	PR ld/20253
	* elf-bfd.h (_bfd_elf_allocate_ifunc_dyn_relocs): Add an
	bfd_boolean argument.
	* elf-ifunc.c (_bfd_elf_create_ifunc_sections): Replace
	"shared object" with "PIC object" in comments.
	(_bfd_elf_allocate_ifunc_dyn_relocs): Updated.  Replace
	"shared object" with "PIC object" in comments.  Avoid PLT if
	requested.  Generate dynamic relocations for non-GOT references.
	Make room for the special first entry in PLT and allocate PLT
	entry only for PLT and PC-relative references.  Store dynamic
	GOT relocations in .rel[a].iplt section for static executables.
	If PLT isn't used, always use GOT for symbol value.  Don't
	allocate GOT entry if it isn't used.
	* elf32-i386.c (elf_i386_check_relocs): Increment PLT reference
	count only in the code section.  Allocate dynamic pointer
	relocation against STT_GNU_IFUNC symbol in the non-code section.
	(elf_i386_adjust_dynamic_symbol): Increment PLT reference count
	only for PC-relative references.
	(elf_i386_allocate_dynrelocs): Pass TRUE to
	_bfd_elf_allocate_ifunc_dyn_relocs.
	(elf_i386_relocate_section): Allow R_386_GOT32/R_386_GOT32X
	relocations against STT_GNU_IFUNC symbols without PLT.  Generate
	dynamic pointer relocation against STT_GNU_IFUNC symbol in
	the non-code section and store it in the proper REL section.
	Don't allow non-pointer relocation against STT_GNU_IFUNC symbol
	without PLT.
	(elf_i386_finish_dynamic_symbol): Generate dynamic
	R_386_IRELATIVE and R_386_GLOB_DAT GOT relocations against
	STT_GNU_IFUNC symbols without PLT.
	(elf_i386_finish_dynamic_sections): Don't handle local
	STT_GNU_IFUNC symbols here.
	(elf_i386_output_arch_local_syms): Handle local STT_GNU_IFUNC
	symbols here.
	(elf_backend_output_arch_local_syms): New.
	* elf32-x86-64.c (elf_i386_check_relocs): Increment PLT reference
	count only in the code section.  Allocate dynamic pointer
	relocation against STT_GNU_IFUNC symbol in the non-code section.
	(elf_x86_64_adjust_dynamic_symbol): Increment PLT reference
	count only for PC-relative references.
	(elf_x86_64_allocate_dynrelocs): Pass TRUE to
	_bfd_elf_allocate_ifunc_dyn_relocs.
	(elf_x86_64_relocate_section): Allow R_X86_64_GOTPCREL,
	R_X86_64_GOTPCRELX, R_X86_64_REX_GOTPCRELX and
	R_X86_64_GOTPCREL64 relocations against STT_GNU_IFUNC symbols
	without PLT.  Generate dynamic pointer relocation against
	STT_GNU_IFUNC symbol in the non-code section and store it in
	the proper RELA section.  Don't allow non-pointer relocation
	against STT_GNU_IFUNC symbol without PLT.
	(elf_x86_64_finish_dynamic_symbol): Generate dynamic
	R_X86_64_IRELATIVE and R_X86_64_GLOB_DAT GOT relocations against
	STT_GNU_IFUNC symbols without PLT.
	(elf_x86_64_finish_dynamic_sections): Don't handle local
	STT_GNU_IFUNC symbols here.
	(elf_x86_64_output_arch_local_syms): Handle local STT_GNU_IFUNC
	symbols here.
	(elf_backend_output_arch_local_syms): New.
	* elfnn-aarch64.c (elfNN_aarch64_allocate_ifunc_dynrelocs):
	Pass FALSE to _bfd_elf_allocate_ifunc_dyn_relocs.

ld/

	PR ld/20253
	* testsuite/ld-i386/i386.exp: Run PR ld/20253 tests.
	* testsuite/ld-i386/no-plt.exp: Likewise.
	* testsuite/ld-x86-64/no-plt.exp: Likewise.
	* testsuite/ld-i386/pr13302.d: Remove .rel.plt section.
	* testsuite/ld-ifunc/ifunc-13-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-13-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-15-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-15-x86-64.d: Likewise.
	* testsuite/ld-x86-64/pr13082-5a.d: Likewise.
	* testsuite/ld-x86-64/pr13082-5b.d: Likewise.
	* testsuite/ld-x86-64/pr13082-6a.d: Likewise.
	* testsuite/ld-x86-64/pr13082-6b.d: Likewise.
	* testsuite/ld-i386/pr20244-2a.d: Remove .plt section.
	* testsuite/ld-ifunc/ifunc-21-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-21-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-22-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-22-x86-64.d: Likewise.
	* testsuite/ld-i386/pr20244-2b.d: Updated.
	* testsuite/ld-i386/pr20244-2c.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18a-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18a-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18b-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18b-x86-64.d: Likewise.
	* testsuite/ld-i386/pr20253-1a.c: New file.
	* testsuite/ld-i386/pr20253-1b.S: Likewise.
	* testsuite/ld-i386/pr20253-1c.S: Likewise.
	* testsuite/ld-i386/pr20253-1d.S: Likewise.
	* testsuite/ld-i386/pr20253-2a.c: Likewise.
	* testsuite/ld-i386/pr20253-2b.S: Likewise.
	* testsuite/ld-i386/pr20253-2c.S: Likewise.
	* testsuite/ld-i386/pr20253-2d.S: Likewise.
	* testsuite/ld-i386/pr20253-3.d: Likewise.
	* testsuite/ld-i386/pr20253-3.s: Likewise.
	* testsuite/ld-i386/pr20253-4.s: Likewise.
	* testsuite/ld-i386/pr20253-4a.d: Likewise.
	* testsuite/ld-i386/pr20253-4b.d: Likewise.
	* testsuite/ld-i386/pr20253-4c.d: Likewise.
	* testsuite/ld-i386/pr20253-5.d: Likewise.
	* testsuite/ld-i386/pr20253-5.s: Likewise.
	* testsuite/ld-ifunc/ifunc-23-x86.s: Likewise.
	* testsuite/ld-ifunc/ifunc-23a-x86.d: Likewise.
	* testsuite/ld-ifunc/ifunc-23b-x86.d: Likewise.
	* testsuite/ld-ifunc/ifunc-23c-x86.d: Likewise.
	* testsuite/ld-ifunc/ifunc-24-x86.s: Likewise.
	* testsuite/ld-ifunc/ifunc-24a-x86.d: Likewise.
	* testsuite/ld-ifunc/ifunc-24b-x86.d: Likewise.
	* testsuite/ld-ifunc/ifunc-24c-x86.d: Likewise.
	* testsuite/ld-ifunc/ifunc-25-x86.s: Likewise.
	* testsuite/ld-ifunc/ifunc-25a-x86.d: Likewise.
	* testsuite/ld-ifunc/ifunc-25b-x86.d: Likewise.
	* testsuite/ld-ifunc/ifunc-25c-x86.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1.s: Likewise.
	* testsuite/ld-x86-64/pr20253-1a.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1b.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1c.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1d.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1e.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1f.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1g.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1h.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1i.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1j.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1k.d: Likewise.
	* testsuite/ld-x86-64/pr20253-1l.d: Likewise.
	* testsuite/ld-x86-64/pr20253-2a.c: Likewise.
	* testsuite/ld-x86-64/pr20253-2b.S: Likewise.
	* testsuite/ld-x86-64/pr20253-2c.S: Likewise.
	* testsuite/ld-x86-64/pr20253-2d.S: Likewise.
	* testsuite/ld-x86-64/pr20253-3.d: Likewise.
	* testsuite/ld-x86-64/pr20253-3.s: Likewise.
	* testsuite/ld-x86-64/pr20253-4.s: Likewise.
	* testsuite/ld-x86-64/pr20253-4a.d: Likewise.
	* testsuite/ld-x86-64/pr20253-4b.d: Likewise.
	* testsuite/ld-x86-64/pr20253-4c.d: Likewise.
	* testsuite/ld-x86-64/pr20253-4d.d: Likewise.
	* testsuite/ld-x86-64/pr20253-4e.d: Likewise.
	* testsuite/ld-x86-64/pr20253-4f.d: Likewise.
	* testsuite/ld-x86-64/pr20253-5.s: Likewise.
	* testsuite/ld-x86-64/pr20253-5a.d: Likewise.
	* testsuite/ld-x86-64/pr20253-5b.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18a-i386.d: Remove extra IRELATIVE
	relocation.
	* testsuite/ld-ifunc/ifunc-18a-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18b-i386.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18b-x86-64.d: Likewise.
	* testsuite/ld-ifunc/ifunc-18a.s: Fix a typo.
	* testsuite/ld-x86-64/x86-64.exp: Run pr20253-1 tests.
2016-06-18 09:17:25 -07:00
Thomas Preud'homme
80c135e554 Add support for Thumb-2 long branch veneers
2016-06-17  Thomas Preud'homme  <thomas.preudhomme@arm.com>
	    Tony Wang  <tony.wang@arm.com>

bfd/
	* elf32-arm.c (elf32_arm_stub_long_branch_thumb2_only): Define stub
	sequence.
	(stub_long_branch_thumb2_only): Define stub.
	(arm_stub_is_thumb): Add case for arm_stub_long_branch_thumb2_only.
	(arm_stub_long_branch_thumb2_only): Likewise.
	(arm_type_of_stub): Use arm_stub_long_branch_thumb2_only for Thumb-2
	capable targets.

ld/
	* testsuite/ld-arm/arm-elf.exp (Thumb-Thumb farcall M profile):
	Assemble for ARMv6-M.
	(Thumb2-Thumb2 farcall M profile): New testcase.
	* testsuite/ld-arm/farcall-thumb2-thumb2-m.d: New file.
	* testsuite/ld-arm/jump-reloc-veneers-cond-long-backward.d: Update to
	reflect the use of Thumb-2 veneers for Thumb-2 capable targets.
	* testsuite/ld-arm/jump-reloc-veneers-cond-long.d: Likewise.
2016-06-17 18:28:08 +01:00
H.J. Lu
ca45f6e990 Add missing ChangeLog entries
commit bf52d7c720
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Jun 15 10:35:38 2016 -0700

    Don't check undefined symbol for IFUNC reloc
2016-06-16 12:38:34 -07:00
H.J. Lu
bf52d7c720 Don't check undefined symbol for IFUNC reloc
Since x86 elf_*_check_relocs is called after all symbols have been
resolved, there is no need to check undefined symbols for relocations
against IFUNC symbols.

bfd/

	* elf32-i386.c (elf_i386_check_relocs): Don't check undefined
	symbols for relocations against IFUNC symbols.
	* elf64-x86-64.c (elf_x86_64_check_relocs): Likewise.

ld/

	* testsuite/ld-i386/i386.exp: Run pr19636-2e-nacl.
	* testsuite/ld-i386/pr19636-2e.d: Skip for NaCl targets.
	Remove .rel.plt section.
	* testsuite/ld-i386/pr19636-2e-nacl.d: New file.
2016-06-16 11:28:29 -07:00
H.J. Lu
3a4b0e0f96 X86: Add tests for static function pointer
* testsuite/ld-i386/no-plt-check1a.S (check): Test static
	function pointer.
	* testsuite/ld-i386/no-plt-check1b.S (check): Likewise.
	* testsuite/ld-x86-64/no-plt-check1.S (check): Likewise.
	* testsuite/ld-i386/no-plt-extern1a.S (func_p): New.  Static
	function pointer.
	* testsuite/ld-i386/no-plt-extern1b.S (func_p): Likewise.
	* testsuite/ld-x86-64/no-plt-extern1.S (func_p): Likewise.
	* testsuite/ld-i386/no-plt-1a.dd: Updated.
	* testsuite/ld-i386/no-plt-1b.dd: Likewise.
	* testsuite/ld-i386/no-plt-1c.dd: Likewise.
	* testsuite/ld-i386/no-plt-1d.dd: Likewise.
	* testsuite/ld-i386/no-plt-1e.dd: Likewise.
	* testsuite/ld-i386/no-plt-1f.dd: Likewise.
	* testsuite/ld-i386/no-plt-1g.dd: Likewise.
	* testsuite/ld-i386/no-plt-1h.dd: Likewise.
	* testsuite/ld-i386/no-plt-1i.dd: Likewise.
	* testsuite/ld-i386/no-plt-1j.dd: Likewise.
	* testsuite/ld-x86-64/no-plt-1a.dd: Likewise.
	* testsuite/ld-x86-64/no-plt-1b.dd: Likewise.
	* testsuite/ld-x86-64/no-plt-1c.dd: Likewise.
	* testsuite/ld-x86-64/no-plt-1d.dd: Likewise.
	* testsuite/ld-x86-64/no-plt-1e.dd: Likewise.
	* testsuite/ld-x86-64/no-plt-1f.dd: Likewise.
	* testsuite/ld-x86-64/no-plt-1g.dd: Likewise.
2016-06-15 09:44:21 -07:00
Senthil Kumar Selvaraj
31eef93e71 Fix PR ld/20254
This patch fixes another edge case related to alignment property
records - reloc offsets adjacent to property record offsets were not
getting adjusted during relaxation.

bfd/

	PR ld/20254
	* elf32-avr.c (elf32_avr_relax_delete_bytes): Adjust reloc
	offsets until reloc_toaddr.

ld/

	PR ld/20254
	* testsuite/ld-avr/avr-prop-6.d: New test.
	* testsuite/ld-avr/avr-prop-6.s: New test.
2016-06-15 12:47:46 +05:30
Alan Modra
0aa7f5862e Formatting fixes.
* ldbuildid.c: Formatting.
	* ldcref.c: Formatting.
	* ldctor.c: Formatting.
	* ldemul.c: Formatting.
	* ldexp.c: Formatting.
	* ldfile.c: Formatting.
	* ldlang.c: Formatting.
	* ldmain.c: Formatting.
	* ldwrite.c: Formatting.
2016-06-14 13:25:21 +09:30
Alan Modra
3860d2b4b7 Delete bfd_my_archive macro
Many more places use abfd->my_archive rather than bfd_my_archive (abfd),
so let's make the code consistently use the first idiom.

bfd/
	* bfd-in.h (bfd_my_archive): Delete.
	* bfd-in2.h: Regenerate.
binutils/
	* ar.c: Expand uses of bfd_my_archive.
	* size.c: Likewise.
ld/
	* ldlang.c: Expand uses of bfd_my_archive.
	* ldmain.c: Likewise.
	* ldmisc.c: Likewise.
	* plugin.c: Likewise.
2016-06-14 13:24:37 +09:30
Alan Modra
b0cffb4767 Set my_archive for thin archives
LTO plugin support in plugin_maybe_claim wants to close the IR bfd
after replacing it with the recompiled object, but can't do so for
archive elements due to various pointers that access the archive bfd.
Thin archives have the same problem.  They too cannot have their
element bfds closed.

	PR ld/20241
bfd/
	* archive.c (open_nested_file): Set my_archive.
	* bfd.c (_bfd_default_error_handler <%B>): Exclude archive file name
	for thin archives.
	* bfdio.c (bfd_tell): Don't adjust origin for thin archives.
	(bfd_seek): Likewise.
	* bfdwin.c (bfd_get_file_window): Likewise.
	* cache.c (cache_bmmap): Likewise.
	(bfd_cache_lookup_worker): Don't look in my_archive for thin archives.
	* mach-o.c (bfd_mach_o_follow_dsym): Don't open my_archive for
	thin archives.
	* plugin.c (try_claim): Likewise.
	* xcofflink.c (xcoff_link_add_dynamic_symbols): Use import path of
	file within thin archive, not the archive.
binutils/
	* bucomm.c (bfd_get_archive_filename): Return file name within thin
	archive.
ld/
	* ldmain.c (add_archive_element): Just print file name of file within
	thin archives.
	* ldmisc.c (vfinfo): Likewise.
	* plugin.c (plugin_object_p): Open file within thin archives.
	(plugin_maybe_claim): Expand comment.
2016-06-14 13:12:00 +09:30
H.J. Lu
712ec27916 Add the GOT base for GOT32 relocs against IFUNC
Add the GOT base for R_386_GOT32/R_386_GOT32X relocations against IFUNC
symbols if there is no base register and disallow them for PIC.

bfd/

	PR ld/20244
	* elf32-i386.c (elf_i386_relocate_section): Add the .got.plt
	section address for R_386_GOT32/R_386_GOT32X relocations against
	IFUNC symbols if there is no base register and return error for
	PIC.

ld/

	PR ld/20244
	* testsuite/ld-i386/i386.exp: Run pr20244-2a, pr20244-2b,
	pr20244-2c and pr20244-2d.
	* testsuite/ld-i386/no-plt.exp: Run pr20244-3a and pr20244-3b.
	* testsuite/ld-i386/pr20244-2.s: New file.
	* testsuite/ld-i386/pr20244-2a.d: Likewise.
	* testsuite/ld-i386/pr20244-2b.d: Likewise.
	* testsuite/ld-i386/pr20244-2c.d: Likewise.
	* testsuite/ld-i386/pr20244-2d.d: Likewise.
	* testsuite/ld-i386/pr20244-3a.c: Likewise.
	* testsuite/ld-i386/pr20244-3b.S: Likewise.
	* testsuite/ld-i386/pr20244-3c.S: Likewise.
	* testsuite/ld-i386/pr20244-3d.S: Likewise.
2016-06-13 11:11:23 -07:00
H.J. Lu
ca8c86efe7 Add 2 i386 tests to call IFUNC functions via GOT
bfd/

	* elf32-i386.c (elf_i386_relocate_section): Simplify IFUNC
	GOT32 adjustment for static executables.

ld/

2016-06-13  H.J. Lu  <hongjiu.lu@intel.com>

	* testsuite/ld-i386/i386.exp: Run ifunc-1a and ifunc-1b.
	* testsuite/ld-i386/ifunc-1a.c: New file.
	* testsuite/ld-i386/ifunc-1b.S: Likewise.
	* testsuite/ld-i386/ifunc-1c.S: Likewise.
	* testsuite/ld-i386/ifunc-1d.S: Likewise.
2016-06-13 09:27:12 -07:00