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64a336ac13
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867 Commits

Author SHA1 Message Date
Palmer Dabbelt
64a336ac13
RISC-V: Add fence.tso instruction 
The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso".  This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.

I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets.  I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.

gas/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * testsuite/gas/riscv/fence-tso.d: New file.
        * testsuite/gas/riscv/fence-tso.s: Likewise.

include/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
        (MASK_FENCE_TSO): Likewise.

opcodes/ChangeLog

2018-10-02  Palmer Dabbelt  <palmer@sifive.com>

        * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 2018-10-02 08:26:32 -07:00
Nick Clifton
fbaf61ad52 Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! 
We have not only removed all unsupported and obsolete code, but also supported lost of new features,
including better link-time relaxations and TLS implementations. Besides, the files generated by the
newly assembler and linker usually get higher performance and more optimized code size.

ld	* emultempl/nds32elf.em (hyper_relax): New variable.
	(nds32_elf_create_output_section_statements):
	the parameters of bfd_elf32_nds32_set_target_option
	(PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
	PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax.
	* emultempl/nds32elf.em (nds32_elf_after_open): Updated.
	* emultempl/nds32elf.em (tls_desc_trampoline): New variable.
	* (nds32_elf_create_output_section_statements): Updated.
	* (nds32_elf_after_parse): Disable relaxations when PIC is enable.
	* (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS,
	PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline.

include	* elf/nds32.h: Remove the unused target features.
	* dis-asm.h (disassemble_init_nds32): Declared.
	* elf/nds32.h (E_NDS32_NULL): Removed.
	(E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
	* opcode/nds32.h: Ident.
	(N32_SUB6, INSN_LW): New macros.
	(enum n32_opcodes): Updated.
	* elf/nds32.h: Doc fixes.
	* elf/nds32.h: Add R_NDS32_LSI.
	* elf/nds32.h: Add new relocations for TLS.

gas 	* config/tc-nds32.c: Remove the unused target features.
	(nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp,
	nds32_set_elf_flags_by_insn, nds32_insert_relax_entry,
	nds32_apply_fix): Likewise.
	(nds32_no_ex9_begin): Removed.
	* config/tc-nds32.c (add_mapping_symbol_for_align,
	make_mapping_symbol, add_mapping_symbol): New functions.
	* config/tc-nds32.h (enum mstate): New.
	(nds32_segment_info_type): Likewise.
	* configure.ac (--enable-dsp-ext, --enable-zol-ext): New options.
	* config.in: Regenerated.
	* configure: Regenerated.
	* config/tc-nds32.c (nds32_dx_regs):
	Set the value according to the configuration.
	(nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext):
	Likewise.
	(nds32_dsp_ext): New variable. Set the value according to the
	configuration.
	(nds32_zol_ext): Likewise.
	(asm_desc, nds32_pseudo_opcode_table): Make them static.
	(nds32_set_elf_flags_by_insn): Updated.
	(nds32_check_insn_available): Updated.
	(nds32_str_tolower): New function.
	* config/tc-nds32.c (relax_table): Updated.
	(md_begin): Updated.
	(md_assemble): Use XNEW macro to allocate space for `insn.info',
	and then remember to free it.
	(md_section_align): Cast (-1) to ValueT.
	(nds32_get_align): Cast (~0U) to addressT.
	(nds32_relax_branch_instructions): Updated.
	(md_convert_frag): Add new local variable `final_r_type'.
	(invalid_prev_frag): Add new bfd_boolean parameter `relax'.
	All callers changed.
	* config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field.
	(struct nds32_hint_map): Add `option_list' field.
	(struct suffix_name, suffix_table): Remove the unused `pic' field.
	(do_pseudo_b, do_pseudo_bal): Remove the suffix checking.
	(do_pseudo_la_internal, do_pseudo_pushpopm): Indent.
	(relax_hint_bias, relax_hint_id_current): New static variables.
	(reset_bias, relax_hint_begin): New variables.
	(nds_itoa): New function.
	(CLEAN_REG, GET_OPCODE): New macros.
	(struct relax_hint_id): New.
	(nds32_relax_hint): For .relax_hint directive, we can use `begin'
	and `end' to mark the relax pattern without giving exactly id number.
	(nds32_elf_append_relax_relocs): Handle the case that the .relax_hint
	directives are attached to pseudo instruction.
	(nds32_elf_save_pseudo_pattern): Change the second parameter from
	instruction's opcode to byte code.
	(nds32_elf_build_relax_relation): Add new bfd_boolean parameter
	`pseudo_hint'.
	(nds32_lookup_pseudo_opcode): Fix the overflow issue.
	(enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT.
	(nds32_elf_record_fixup_exp, relax_ls_table, hint_map,
	nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name):
	Updated.
	* config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6.
	(enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and
	NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add
	NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and
	NDS32_RELAX_HINT_LA_GOTOFF.
	* config/tc-nds32.h (relax_ls_table): Add floating load/store
	to gp relax pattern.
	(hint_map, nds32_find_reloc_table): Likewise.
	* configure.ac: Define NDS32_LINUX_TOOLCHAIN.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-nds32.h (enum nds32_ramp): Updated.
	(enum nds32_relax_hint_type): Likewise.
	* config/tc-nds32.c: Include "errno.h" and "limits.h".
	(relax_ls_table): Add TLS relax patterns.
	(nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on
	each instructions of TLS patterns.
	(nds32_elf_record_fixup_exp): Updated.
	(nds32_apply_fix): Likewise.
	(suffix_table): Add TLSDESC suffix.

binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number
	from 215 to 255 for NDS32.

bfd	* elf32-nds32.c (nds32_elf_relax_loadstore):
	Remove the unused target features.
	(bfd_elf32_nds32_set_target_option): Remove the unused parameters.
	(nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12,
	nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls,
	nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff
	nds32_elf_relax_gotoff_suff, calculate_plt_memory_address,
	calculate_plt_offset, calculate_got_memory_address,
	nds32_elf_check_dup_relocs): Removed.
	All callers changed.
	* elf32-nds32.h: Remove the unused macros and defines.
	(elf_nds32_link_hash_table): Remove the unused variable.
	(bfd_elf32_nds32_set_target_option): Update prototype.
	(nds32_elf_ex9_init): Removed.
	* elf32-nds32.c (nds32_convert_32_to_16): Updated.
	* elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros
	to initialize array nds32_elf_howto_table in any order
	without lots of EMPTY_HOWTO.
	(nds32_reloc_map): Updated.
	* reloc.c: Add BFD_RELOC_NDS32_LSI.
	* bfd-in2.h: Regenerated.
	* bfd/libbfd.h: Regenerated.
	* elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI.
	(nds32_reloc_map): Likewise.
	(nds32_elf_relax_flsi): New function.
	(nds32_elf_relax_section): Support floating load/store relaxation.
	* elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset):
	New macro.
	(struct elf_nds32_link_hash_entry): New `offset_to_gp' field.
	(struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields.
	(elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard,
	nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym):
	New functions.
	(nds32_info_to_howto_rel): Add BFD_ASSERT.
	(bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc,
	nds32_elf_link_hash_table_create, nds32_elf_relocate_section,
	nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label,
	bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated.
	(nds32_elf_final_sda_base): Improve it to find the better gp value.
	(insert_nds32_elf_blank): Must consider `len' when inserting blanks.
	* elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype.
	(struct elf_nds32_link_hash_table): Add new variable `hyper_relax'.
	* elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function.
	(create_got_section): Likewise.
	(allocate_dynrelocs, nds32_elf_size_dynamic_sections,
	nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated.
	(nds32_elf_check_relocs): Fix the issue that the shared library may
	has TEXTREL entry in the dynamic section.
	(nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs
	since the TEXTREL issue is fixed in the nds32_elf_check_relocs.
	(nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ
	dynamic entry.
	(calculate_offset): Remove the unused parameter `pic_ext_target' and
	related codes.
	All callers changed.
	(elf_backend_dtrel_excludes_plt): Disable it temporarily since it
	will cause some errors for our test cases.
	* elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the
	generic object.
	* reloc.c: Add TLS relocations.
	* libbfd.h: Regenerated.
	* bfd-in2.h: Regenerated.
	* elf32-nds32.h (struct section_id_list_t): New.
	(elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group,
	elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model):
	New prototypes.
	(elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent):
	New macro.
	(nds32_insertion_sort, bfd_elf32_nds32_set_target_option,
	elf_nds32_link_hash_table): Updated.
	* elf32-nds32.c (enum elf_nds32_tls_type): New.
	(struct elf32_nds32_relax_group_t, struct relax_group_list_t): New.
	(elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type,
	fls, ones32, list_insert, list_insert_sibling, dump_chain,
	elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id,
	elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions.
	(elf_nds32_obj_tdata): Add new fields.
	(elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros.
	(nds32_elf_howto_table): Add TLS relocations.
	(nds32_reloc_map): Likewise.
	(nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections,
	nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info,
	nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option,
	nds32_elf_check_relocs, allocate_dynrelocs): Updated.
	(nds32_elf_relax_section): Call nds32_elf_unify_tls_model.
	(dtpoff_base): Rename it to `gottpof' and then update it.

opcodes	* nds32-asm.c (operand_fields): Remove the unused fields.
	(nds32_opcodes): Remove the unused instructions.
	* nds32-dis.c (nds32_ex9_info): Removed.
	(nds32_parse_opcode): Updated.
	(print_insn_nds32): Likewise.
	* nds32-asm.c (config.h, stdlib.h, string.h): New includes.
	(LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
	(nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
	build_opcode_hash_table): New functions.
	(nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
	nds32_opcode_table): New.
	(hw_ktabs): Declare it to a pointer rather than an array.
	(build_hash_table): Removed.
	* nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
	SYN_ROPT and upadte HW_GPR and HW_INT.
	* nds32-dis.c (keywords): Remove const.
	(match_field): New function.
	(nds32_parse_opcode): Updated.
	* disassemble.c (disassemble_init_for_target):
	Add disassemble_init_nds32.
	* nds32-dis.c (eum map_type): New.
	(nds32_private_data): Likewise.
	(get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
	nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
	(print_insn_nds32): Updated.
	* nds32-asm.c (parse_aext_reg): Add new parameter.
	(parse_re, parse_re2, parse_aext_reg): Only reduced registers
	are allowed to use.
	All callers changed.
	* nds32-asm.c (keyword_usr, keyword_sr): Updated.
	(operand_fields): Add new fields.
	(nds32_opcodes): Add new instructions.
	(keyword_aridxi_mx): New keyword.
	* nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
	and NASM_ATTR_ZOL.
	(ALU2_1, ALU2_2, ALU2_3): New macros.
	* nds32-dis.c (nds32_filter_unknown_insn): Updated.
 2018-09-20 13:32:58 +01:00
Jim Wilson
43135d3b15 RISC-V: Allow instruction require more than one extension 
2018-08-29  Kito Cheng  <kito@andestech.com>

gas/
	* config/tc-riscv.c (riscv_subset_supports): New argument:
	xlen_required.
	(riscv_multi_subset_supports): New function, able to check more
	than one extension.
	(riscv_ip): Use riscv_multi_subset_supports instead of
	riscv_subset_supports.
	(riscv_set_arch): Update call-site for riscv_subset_supports.
	(riscv_after_parse_args): Likewise.

include/
	*opcode/riscv.h (MAX_SUBSET_NUM): New.
	(riscv_opcode): Add xlen_requirement field and change type of
	subset.

opcodes/
	* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
	riscv_opcode.xlen_requirement.
	* riscv-opc.c (riscv_opcodes): Update for struct change.
 2018-08-30 13:23:12 -07:00
Chenghua Xu
9108bc33b1 [MIPS] Add Loongson 2K1000 proccessor support. 
bfd/
	* archures.c (bfd_architecture): New machine
	bfd_mach_mips_gs264e.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
	E_MIPS_MACH_GS264E.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Map bfd_mach_mips_gs264e to
	bfd_mach_mips_gs464e extension.

binutils/
	* NEWS: Mention Loongson 2K1000 proccessor support.
	* readelf.c (get_machine_flags): Handle gs264e.

elfcpp/
	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS264E.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS264E.
	(mips_cpu_info_table): Add gs264e descriptors.
	* doc/as.texi (march table): Add gs264e.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
	* opcode/mips.h (CPU_XXX): New CPU_GS264E.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
	gs264e and gs464e.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 2018-08-29 20:55:25 +08:00
Chenghua Xu
bd782c07b9 [MIPS] Add Loongson 3A2000/3A3000 proccessor support. 
bfd/
	* archures.c (bfd_architecture): New machine
	bfd_mach_mips_gs464e.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle
	E_MIPS_MACH_GS464E.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Map bfd_mach_mips_gs464e to
	bfd_mach_mips_gs464 extension.

binutils/
	* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
	* readelf.c (get_machine_flags): Handle gs464e.

elfcpp/
	* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
	(mips_cpu_info_table): Add gs464e descriptors.
	* doc/as.texi (march table): Add gs464e.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
	* opcode/mips.h (CPU_XXX): New CPU_GS464E.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
	gs464e and gs464.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 2018-08-29 20:43:19 +08:00
Chenghua Xu
ac8cb70f36 [MIPS] Add Loongson 3A1000 proccessor support. 
bfd/
	* archures.c (bfd_architecture): Rename
	bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (enum I_xxx): Likewise.
	(arch_info_struct): Likewise.
	* elfxx-mips.c (_bfd_elf_mips_mach): Likewise.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Likewise.
	(bfd_mips_isa_ext_mach): Likewise.
	(bfd_mips_isa_ext): Likewise.
	(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.

binutils/
	* NEWS: Mention Loongson 3A1000 proccessor support.
	* readelf.c (get_machine_flags): Rename loongson-3a to gs464.
	(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.

elfcpp/
	* mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to
	E_MIPS_MACH_GS464.

gas/
	* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename
	CPU_LOONGSON_3A to CPU_GS464.
	(mips_cpu_info_table): Add gs464 descriptors, Keep
	loongson3a as an alias of gs464 for compatibility.
	* doc/as.texi (march table): Rename loongson3a to gs464.
	* testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension"
	flag to None.

gold/
	* mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach):
	Rename loongson3a to gs464.
	(mips_isa_ext_mach, mips_isa_ext): Delete loongson3a.
	(infer_abiflags): Use ases instead of isa_ext for infer ABI
flags.
	(elf_mips_mach_name): Rename loongson3a to gs464.

include/
	* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
	E_MIPS_MACH_GS464.
	(AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
	* opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
	(CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
	* opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.

ld/
	* testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a
	to gs464.

opcodes/
	* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
	loongson3a as an alias of gs464 for compatibility.
	* mips-opc.c (mips_opcodes): Change Comments.
 2018-08-29 20:32:30 +08:00
Chenghua Xu
a693765e23 [MIPS/GAS] Add Loongson EXT2 Instructions support. 
bfd/
	* elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension.

binutils/
	* readelf.c (print_mips_ases): Add Loongson EXT2 extension.

gas/
	* NEWS: Mention Loongson EXTensions R2 (EXT2) support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_EXT2 and
	OPTION_NO_LOONGSON_EXT2.
	(md_longopts): Likewise.
	(mips_ases): Define availability for EXT.
	(mips_convert_ase_flags): Map ASE_LOONGSON_EXT2 to
	AFL_ASE_LOONGSON_EXT2.
	(md_show_usage): Add help for -mloongson-ext2 and
	-mno-loongson-ext2.
	* doc/as.texi: Document -mloongson-ext2, -mno-loongson-ext2.
	* doc/c-mips.texi: Document -mloongson-ext2, -mno-loongson-ext2,
	.set loongson-ext2 and .set noloongson-ext2.
	* testsuite/gas/mips/loongson-ext2.d: New test.
	* testsuite/gas/mips/loongson-ext2.s: New test.
	* testsuite/gas/mips/mips.exp: Run loongson-ext2 test.

include/
	* elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
	* opcode/mips.h (ASE_LOONGSON_EXT2): New macro.

opcodes/
	* mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
	option.
	(print_mips_disassembler_options): Document -M loongson-ext.
	* mips-opc.c (LEXT2): New macro.
	(mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 2018-08-29 20:08:58 +08:00
Chenghua Xu
bdc6c06e3b [MIPS/GAS] Split Loongson EXT Instructions from loongson3a. 
bfd/
	 * elfxx-mips.c (infer_mips_abiflags): Use ases instead of
	 isa_ext for infer ABI flags.
	 (print_mips_ases): Add Loongson EXT extension.

binutils/
	 * readelf.c (print_mips_ases): Add Loongson EXT extension.

elfcpp/
	 * mips.h (AFL_ASE_LOONGSON_EXT): New enum.

gas/
	 * NEWS: Mention Loongson EXTensions (EXT) support.
	 * config/tc-mips.c (options): Add OPTION_LOONGSON_EXT and
	 OPTION_NO_LOONGSON_EXT.
	 (md_longopts): Likewise.
	 (mips_ases): Define availability for EXT.
	 (mips_convert_ase_flags): Map ASE_LOONGSON_EXT to
	 AFL_ASE_LOONGSON_EXT.
	 (mips_cpu_info_table): Add ASE_LOONGSON_EXT for loongson3a.
	 (md_show_usage): Add help for -mloongson-ext and
	 -mno-loongson-ext.
	 * doc/as.texi: Document -mloongson-ext, -mno-loongson-ext.
	 * doc/c-mips.texi: Document -mloongson-ext, -mno-loongson-ext,
	 .set loongson-ext and .set noloongson-ext.
	 * testsuite/gas/mips/loongson-mmi.d: Add ASE flag.

include/
	 * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
	 (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
	 * opcode/mips.h (ASE_LOONGSON_EXT): New macro.

opcodes/
	 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
	 descriptors.
	 (parse_mips_ase_option): Handle -M loongson-ext option.
	 (print_mips_disassembler_options): Document -M loongson-ext.
	 * mips-opc.c (IL3A): Delete.
	 * mips-opc.c (LEXT): New macro.
	 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
	 instructions.
 2018-08-29 19:57:39 +08:00
Chenghua Xu
716c08de28 [MIPS/GAS] Split Loongson CAM Instructions from loongson3a 
bfd/
	* elfxx-mips.c (print_mips_ases): Add CAM extension.

binutils/
	* readelf.c (print_mips_ases): Add CAM extension.

gas/
	* NEWS: Mention Loongson Content Address Memory (CAM)
	support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_CAM and
	OPTION_NO_LOONGSON_CAM.
	(md_longopts): Likewise.
	(mips_ases): Define availability for CAM.
	(mips_convert_ase_flags): Map ASE_LOONGSON_CAM to
	AFL_ASE_LOONGSON_CAM.
	(mips_cpu_info_table): Add ASE_LOONGSON_CAM for loongson3a.
	(md_show_usage): Add help for -mloongson-cam and
	-mno-loongson-cam.
	* doc/as.texi: Document -mloongson-cam, -mno-loongson-cam.
	* doc/c-mips.texi: Document -mloongson-cam, -mno-loongson-cam,
	.set loongson-cam and .set noloongson-cam.
	* testsuite/gas/mips/loongson-3a-2.d: Move cam test to ...
	* testsuite/gas/mips/loongson-cam.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-3a-2.s: Move cam test to ...
	* testsuite/gas/mips/loongson-cam.s: Here.
	* testsuite/gas/mips/loongson-3a-mmi.d: Add ASE flag.
	* testsuite/gas/mips/mips.exp: Run loongson-cam test.

include/
	* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
	* opcode/mips.h (ASE_LOONGSON_CAM): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add CAM to loongson3a
	descriptors.
	(parse_mips_ase_option): Handle -M loongson-cam option.
	(print_mips_disassembler_options): Document -M loongson-cam.
	* mips-opc.c (LCAM): New macro.
	(mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
	instructions.
 2018-08-29 19:33:09 +08:00
Alan Modra
9cf7e5687f Use operand->extract to provide defaults for optional PowerPC operands 
Most optional operands to powerpc instructions use a default value of
zero, but there are a few exceptions.  Those have been handled by
PPC_OPERAND_OPTIONAL_VALUE and an entry in the powerpc_operands table
for the default value, smuggled in the shift field.  This patch
changes that to using the operand extract function to provide non-zero
defaults.

I've also moved the code determining whether optional operands are
provided or omitted, to the point the first optional operand is seen,
and allowed for the possibility of optional base register operands
in a future patch.

The patch does change the error you get on invalid assembly like

  ld 3,4

You'll now see "missing operand" rather than
"syntax error; end of line, expected `('".

gas/
	* config/tc-ppc.c (md_assemble): Delay counting of optional
	operands until one is encountered.  Allow for the possibility
	of optional base regs, ie. PPC_OPERAND_PARENS.  Call
	ppc_optional_operand_value with extra args.
include/
	* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
	Mention use of "extract" function to provide default value.
	(PPC_OPERAND_OPTIONAL_VALUE): Delete.
	(ppc_optional_operand_value): Rewrite to use extract function.
opcodes/
	* ppc-dis.c (operand_value_powerpc): Init "invalid".
	(skip_optional_operands): Count optional operands, and update
	ppc_optional_operand_value call.
	* ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
	(extract_vlensi): Likewise.
	(extract_fxm): Return default value for missing optional operand.
	(extract_ls, extract_raq, extract_tbr): Likewise.
	(insert_sxl, extract_sxl): New functions.
	(insert_esync, extract_esync): Remove Power9 handling and simplify.
	(powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
	flag and extra entry.
	(powerpc_operands <SXL>): Likewise, and use insert_sxl and
	extract_sxl.
 2018-08-21 16:05:36 +09:30
John Darrington
7ba3ba91a3 S12Z: Move opcode header to public include directory. 
opcodes/
        * s12z.h: Delete.
	* s12z-dis.c: Adjust path of included file.

include/
        * opcode/s12z.h: New file.

gas/
	* config/tc-s12z.c: Adjust path of included file.
 2018-08-18 07:50:03 +02:00
claziss
b6523c37fb [ARC] Update handling AUX-registers. 
Update aux-registers data-base, and accept aux-registers names with
upper/lowercase names.

opcode/
2017-07-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-regs.h: Update aux-registers.

gas/
2017-07-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (find_opcode_match): Accept uppercase aux-regs
	names.
	* testsuite/gas/arc/ld2.d: Update test.
	* testsuite/gas/arc/taux.d: Likewise.
	* testsuite/gas/arc/taux.s: Likewise.

include/
2017-07-18  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (ARC_OPCODE_ARCV1): Define.
 2018-08-06 16:41:32 +03:00
Jim Wilson
eb41b24898 RISC-V: Set insn info fields correctly when disassembling. 
include/
	* opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR)
	(INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE)
	(INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New.

	opcodes/
	* riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
	fields.
	* riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 2018-07-30 13:55:41 -07:00
Andrew Jenner
b8891f8d62 Add support for the C_SKY series of processors. 
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants.  V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc.  There is support for bare-metal ELF targets and Linux with both glibc and uClibc.

This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics.  C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers.  (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about.

bfd     * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY.
        (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise.
        * Makefile.in: Regenerated.
        * archures.c (enum bfd_architecture): Add bfd_arch_csky and
        related bfd_mach defines.
        (bfd_csky_arch): Declare.
        (bfd_archures_list): Add C-SKY.
        * bfd-in.h (elf32_csky_build_stubs): Declare.
        (elf32_csky_size_stubs): Declare.
        (elf32_csky_next_input_section: Declare.
        (elf32_csky_setup_section_lists): Declare.
        * bfd-in2.h: Regenerated.
        * config.bfd: Add C-SKY.
        * configure.ac: Likewise.
        * configure: Regenerated.
        * cpu-csky.c: New file.
        * elf-bfd.h (enum elf_target_id): Add C-SKY.
        * elf32-csky.c: New file.
        * libbfd.h: Regenerated.
        * reloc.c: Add C-SKY relocations.
        * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare.
        (_bfd_target_vector): Add C-SKY target vector entries.

binutils* readelf.c: Include elf/csky.h.
        (guess_is_rela): Handle EM_CSKY.
        (dump_relocations): Likewise.
        (get_machine_name): Likewise.
        (is_32bit_abs_reloc): Likewise.

include  * dis-asm.h (csky_symbol_is_valid): Declare.
         * opcode/csky.h: New file.

opcodes  * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
         * Makefile.in: Regenerated.
         * configure.ac: Add C-SKY.
         * configure: Regenerated.
         * csky-dis.c: New file.
         * csky-opc.h: New file.
         * disassemble.c (ARCH_csky): Define.
         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.

gas      * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY.
         (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise.
         * Makefile.in: Regenerated.
         * config/tc-csky.c: New file.
         * config/tc-csky.h: New file.
         * config/te-csky_abiv1.h: New file.
         * config/te-csky_abiv1_linux.h: New file.
         * config/te-csky_abiv2.h: New file.
         * config/te-csky_abiv2_linux.h: New file.
         * configure.tgt: Add C-SKY.
         * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY.
         * doc/Makefile.in: Regenerated.
         * doc/all.texi: Set CSKY feature.
         * doc/as.texi (Overview): Add C-SKY options.
         (Machine Dependencies): Likewise.
         * doc/c-csky.texi: New file.
         * testsuite/gas/csky/*: New test cases.

ld      * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations.
        (ecskyelf.c, ecskyelf_linux.c): New rules.
        * Makefile.in: Regenerated.
        * configure.tgt: Add C-SKY.
        * emulparams/cskyelf.sh: New file.
        * emulparams/cskyelf_linux.sh: New file.
        * emultempl/cskyelf.em: New file.
        * gen-doc.texi: Add C-SKY.
        * ld.texi: Likewise.
        (Options specific to C-SKY targets): New section.
        * testsuite/ld-csky/*: New tests.
 2018-07-30 12:24:14 +01:00
Alex Chadwick
fa758a7046 PowerPC Improve support for Gekko & Broadway 
This is a relatively straightforward patch to improve support for the
IBM Gekko and IBM Broadway processors.  Broadway is functionally
equivalent to the IBM 750CL, while Gekko's functionality is a subset
of theirs.  The patch simplifies this reality and adds -mgekko and
-mbroadway as aliases for -m750cl.  I didn't feel it was worth wasting
a PPC_OPCODE_* bit to differentiate Gekko.  The patch adds a number of
simplified mnemonics for special purpose register access.  Notably,
Broadway adds 4 additional IBAT and DBAT registers but these are not
assigned sequential SPR numbers.

gas/
	* config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway.
	* doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway.
	* doc/c-ppc.texi (PowerPC-Opts): Likewise.
	* testsuite/gas/ppc/broadway.d,
	* testsuite/gas/ppc/broadway.s: New test for broadway.
	* testsuite/gas/ppc/ppc.exp: Run new test.
include/
	* opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
opcodes/
	* ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
	(powerpc_init_dialect): Handle bfd_mach_ppc_750.
	* ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
	support disjointed BAT.
	(powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
	(XSPRGQR_MASK, GEKKO, BROADWAY): Define.
	(powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 2018-07-26 17:42:47 +09:30
Chenghua Xu
8095d2f70e MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a 
The MMI instruction set has been implemented in many Loongson
processors.  There is a lot of software optimized for MMI.  This patch
splits MMI from loongson2f/3a, and adds GAS and disassembler options for
MMI instructions.

2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
            Maciej W. Rozycki  <macro@mips.com>

bfd/
	* elfxx-mips.c (print_mips_ases): Add MMI extension.

binutils/
	* readelf.c (print_mips_ases): Add MMI extension.

gas/
	* NEWS: Mention MultiMedia extensions Instructions (MMI)
	support.
	* config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and
	OPTION_NO_LOONGSON_MMI.
	(md_longopts): Likewise.
	(mips_ases): Define availability for MMI.
	(mips_convert_ase_flags): Map ASE_LOONGSON_MMI to
	AFL_ASE_LOONGSON_MMI.
	(mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a.
	(md_show_usage): Add help for -mloongson-mmi and
	-mno-loongson-mmi.
	* doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi.
	* doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi,
	.set loongson-mmi and .set noloongson-mmi.
	* testsuite/gas/mips/loongson-2f.d: Move mmi test to ...
	* testsuite/gas/mips/loongson-2f-mmi.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-2f.s: Move mmi test to ...
	* testsuite/gas/mips/loongson-2f-mmi.s: Here.
	* testsuite/gas/mips/loongson-3a.d: Move mmi test to ...
	* testsuite/gas/mips/loongson-3a-mmi.d: Here.  Add ISA/ASE
	flag verification.
	* testsuite/gas/mips/loongson-3a.s: Move mmi test to ...
	* testsuite/gas/mips/loongson-3a-mmi.s: Here.
	* testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and
	loongson-3a-mmi tests.

include/
	* elf/mips.h (AFL_ASE_MMI): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
	* opcode/mips.h (ASE_LOONGSON_MMI): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
	loongson3a descriptors.
	(parse_mips_ase_option): Handle -M loongson-mmi option.
	(print_mips_disassembler_options): Document -M loongson-mmi.
	* mips-opc.c (LMMI): New macro.
	(mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
	instructions.
 2018-07-20 13:21:33 +01:00
Tamar Christina
369c9167d4 Fix AArch64 encodings for by element instructions. 
Some instructions in Armv8-a place a limitation on FP16 registers that can be
used as the register from which to select an element from.

e.g. fmla restricts Rm to 4 bits when using an FP16 register.  This restriction
does not apply for all instructions, e.g. fcmla does not have this restriction
as it gets an extra bit from the M field.

Unfortunately, this restriction to S_H was added for all _Em operands before,
meaning for a large number of instructions you couldn't use the full register
file.

This fixes the issue by introducing a new operand _Em16 which applies this
restriction only when paired with S_H and leaves the _Em and the other
qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).

Also the patch updates all instructions that should be affected by this.

opcodes/

	PR binutils/23192
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
	* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
	* aarch64-opc.c (operand_general_constraint_met_p,
	aarch64_print_operand): Likewise.
	* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
	smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
	fmlal2, fmlsl2.
	(AARCH64_OPERANDS): Add Em2.

gas/

	PR binutils/23192
	* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
	AARCH64_OPND_Em16
	* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
	16 registers.
	* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
	* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
	* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
	* testsuite/gas/aarch64/sve.d: Likewise.

include/

	PR binutils/23192
	*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
 2018-06-29 12:14:42 +01:00
Faraz Shahbazker
6f20c942c3 MIPS: Add Global INValidate ASE support 
Add support for the Global INValidate Application Specific Extension
for Release 6 of the MIPS Architecture.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 187-191

bfd/
	* elfxx-mips.c (print_mips_ases): Add GINV extension.

binutils/
	* readelf.c (print_mips_ases): Add GINV extension.

gas/
	* NEWS: Mention MIPS Global INValidate ASE support.
	* config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
	(md_longopts): Likewise.
	(mips_ases): Define availability for GINV.
	(mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
	(md_show_usage): Add help for -mginv and -mno-ginv.
	* doc/as.texinfo: Document -mginv, -mno-ginv.
	* doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
	.set noginv.
	* testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
	ASE.
	* testsuite/gas/mips/ase-errors-2.s: Likewise.
	* testsuite/gas/mips/ase-errors-1.l: Likewise.
	* testsuite/gas/mips/ase-errors-2.l: Likewise.
	* testsuite/gas/mips/ginv.d: New test.
	* testsuite/gas/mips/ginv-err.d: New test.
	* testsuite/gas/mips/ginv-err.l: New test stderr output.
	* testsuite/gas/mips/ginv.s: New test source.
	* testsuite/gas/mips/ginv-err.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

include/
	* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
	(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
	* opcode/mips.h: Document "+\" operand format.
	(ASE_GINV): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
	mips64r6 descriptors.
	(parse_mips_ase_option): Handle -Mginv option.
	(print_mips_disassembler_options): Document -Mginv.
	* mips-opc.c (decode_mips_operand) <+\>: New operand format.
	(GINV): New macro.
	(mips_opcodes): Define ginvi and ginvt.
 2018-06-14 21:34:49 +01:00
Scott Egerton
730c31740a MIPS: Add CRC ASE support 
Add support for the CRC Application Specific Extension for Release 6 of
the MIPS Architecture.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 143-148

[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
    Instruction Set Manual", Imagination Technologies Ltd., Document
    Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
    "Alphabetical List of Instructions", pp. 165-170

ChangeLog:

bfd/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* elfxx-mips.c (print_mips_ases): Add CRC.

binutils/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* readelf.c (print_mips_ases): Add CRC.

gas/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
            Maciej W. Rozycki  <macro@mips.com>

	* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
	(md_longopts): Likewise.
	(md_show_usage): Add help for -mcrc and -mno-crc.
	(mips_ases): Define availability for CRC and CRC64.
	(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
	* doc/as.texinfo: Document -mcrc, -mno-crc.
	* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
	.set no-crc.
	* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
	ASE.
	* testsuite/gas/mips/ase-errors-2.l: Likewise.
	* testsuite/gas/mips/ase-errors-1.s: Likewise.
	* testsuite/gas/mips/ase-errors-2.s: Likewise.
	* testsuite/gas/mips/crc.d: New test.
	* testsuite/gas/mips/crc64.d: New test.
	* testsuite/gas/mips/crc-err.d: New test.
	* testsuite/gas/mips/crc64-err.d: New test.
	* testsuite/gas/mips/crc-err.l: New test stderr output.
	* testsuite/gas/mips/crc64-err.l: New test stderr output.
	* testsuite/gas/mips/crc.s: New test source.
	* testsuite/gas/mips/crc64.s: New test source.
	* testsuite/gas/mips/crc-err.s: New test source.
	* testsuite/gas/mips/crc64-err.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

include/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* elf/mips.h (AFL_ASE_CRC): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
	* opcode/mips.h (ASE_CRC): New macro.
	* opcode/mips.h (ASE_CRC64): Likewise.

opcodes/
2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
            Faraz Shahbazker  <Faraz.Shahbazker@mips.com>

	* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
	* mips-opc.c (CRC, CRC64): New macros.
	(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
	crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
	crc32cd for CRC64.
 2018-06-13 15:39:05 +01:00
Peter Bergner
98553ad33e Remove fake operand handling for extended mnemonics. 
opcodes/
	* ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
	insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
	(insert_bab, extract_bab, insert_btab, extract_btab,
	insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
	(BAT, BBA VBA RBS XB6S): Delete macros.
	(BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
	(BB, BD, RBX, XC6): Update for new macros.
	(powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
	crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
	e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
	* ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.

include/
	* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.

gas/
	* config/tc-ppc.c (md_assemble): Delete handling of fake operands.
	* testsuite/gas/ppc/common.s (crmove, cror, or., or, nor., nor): Add
	test of extended mnemonics.
	* testsuite/gas/ppc/common.d: Likewise.  Don't match instruction offset.
	* testsuite/gas/ppc/spe.s (evor, evnor): Add test of extended mnemonics.
	* testsuite/gas/ppc/spe.d: Likewise.  Don't match instruction offset.
 2018-05-21 17:31:07 -05:00
Tamar Christina
f9830ec165 Implement Read/Write constraints on system registers on AArch64 
This patch adds constraints for read and write only system registers with the
msr and mrs instructions.  The code will treat having both flags set and none
set as the same.  These flags add constraints that must be matched up. e.g. a
system register with a READ only flag set, can only be used with mrs.  If The
constraint fails a warning is emitted.

Examples of the warnings generated:

test.s: Assembler messages:
test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'

and disassembly notes:

0000000000000000 <main>:
   0:	d5130503 	msr	dbgdtrtx_el0, x3
   4:	d5130503 	msr	dbgdtrtx_el0, x3
   8:	d5330503 	mrs	x3, dbgdtrrx_el0
   c:	d5330503 	mrs	x3, dbgdtrrx_el0
  10:	d5180003 	msr	midr_el1, x3	; note: writing to a read-only register.

Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during
disassembly the constraints are use to disambiguate between the two.  An exact
constraint match is always prefered over partial ones if available.

As always the warnings can be suppressed with -w and also be made errors using
warnings as errors.

binutils/

	PR binutils/21446
	* doc/binutils.texi (-M): Document AArch64 options.

gas/

	PR binutils/21446
	* testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test.
	* testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise.
	* testsuite/gas/aarch64/sysreg-diagnostic.s: New.
	* testsuite/gas/aarch64/sysreg-diagnostic.l: New.
	* testsuite/gas/aarch64/sysreg-diagnostic.d: New.

include/

	PR binutils/21446
	* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.

opcodes/

	PR binutils/21446
	* aarch64-asm.c (opintl.h): Include.
	(aarch64_ins_sysreg): Enforce read/write constraints.
	* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
	* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
	(F_REG_READ, F_REG_WRITE): New.
	* aarch64-opc.c (aarch64_print_operand): Generate notes for
	AARCH64_OPND_SYSREG.
	(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
	(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
	mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
	id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
	id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
	id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
	mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
	id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
	id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
	id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
	csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
	rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
	mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
	mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
	pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
	* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
	msr (F_SYS_WRITE), mrs (F_SYS_READ).
 2018-05-15 17:17:36 +01:00
Tamar Christina
7d02540ab7 Allow non-fatal errors to be emitted and for disassembly notes be placed on AArch64 
This patch adds a new platform option "notes" that can be used to indicate if
disassembly notes should be placed in the disassembly as comments.

These notes can contain information about a failing constraint such as reading
from a write-only register.  The disassembly will not be blocked because of this
but -M notes will emit a comment saying that the operation is not allowed.

For assembly this patch adds a new non-fatal status for errors.  This is
essentially a warning.  The reason for not creating an actual warning type is
that this causes the interaction between the ordering of warnings and errors to
be problematic.  Currently the error buffer is almost always filled because of
the way operands are matched during assembly. An earlier template may have put
an error there that would only be displayed if no other template matches or
generates a higher priority error.  But by definition a warning is lower
priority than a warning, so the error (which is incorrect if another template
matched) will supersede the warning.  By treating warnings as errors and only
later relaxing the severity this relationship keeps working and the existing
reporting infrastructure can be re-used.

binutils/

	PR binutils/21446
	* doc/binutils.texi (-M): Document AArch64 options.
	* NEWS: Document notes and warnings.

gas/

	PR binutils/21446
	* config/tc-aarch64.c (print_operands): Indicate no notes.
	(output_operand_error_record): Support non-fatal errors.
	(output_operand_error_report, warn_unpredictable_ldst, md_assemble):
	Likewise.

include/

	PR binutils/21446
	* opcode/aarch64.h (aarch64_operand_error): Add non_fatal.
	(aarch64_print_operand): Support notes.

opcodes/

	PR binutils/21446
	* aarch64-dis.c (no_notes: New.
	(parse_aarch64_dis_option): Support notes.
	(aarch64_decode_insn, print_operands): Likewise.
	(print_aarch64_disassembler_options): Document notes.
	* aarch64-opc.c (aarch64_print_operand): Support notes.
 2018-05-15 17:17:36 +01:00
Tamar Christina
561a72d4dd Modify AArch64 Assembly and disassembly functions to be able to fail and report why. 
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.

These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.

This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.

The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.

gas/

	PR binutils/21446
	* config/tc-aarch64.c (parse_sys_reg): Return register flags.
	(parse_operands): Fill in register flags.

gdb/

	PR binutils/21446
	* aarch64-tdep.c (aarch64_analyze_prologue,
	aarch64_software_single_step, aarch64_displaced_step_copy_insn):
	Indicate not interested in errors.

include/

	PR binutils/21446
	* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
	(aarch64_decode_insn): Accept error struct.

opcodes/

	PR binutils/21446
	* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
	and take error struct.
	* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
	aarch64_ins_reglist, aarch64_ins_ldst_reglist,
	aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
	aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
	aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
	aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
	aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
	aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
	aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
	aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
	aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
	aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
	aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
	aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
	aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
	aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
	aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
	aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
	aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
	aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
	aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
	aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
	aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
	aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
	* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
	* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
	aarch64_ext_reglist, aarch64_ext_ldst_reglist,
	aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
	aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
	aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
	aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
	aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
	aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
	aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
	aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
	aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
	aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
	aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
	aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
	aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
	aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
	aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
	aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
	aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
	aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
	aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
	aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
	aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
	aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
	(determine_disassembling_preference, aarch64_decode_insn,
	print_insn_aarch64_word, print_insn_data): Take errors struct.
	(print_insn_aarch64): Use errors.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-gen.c (print_operand_inserter): Use errors and change type to
	boolean in aarch64_insert_operan.
	(print_operand_extractor): Likewise.
	* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 2018-05-15 17:17:36 +01:00
Francois H. Theron
1678bd35a3 Fix error messages in the NFP sources when building for 32-bit targets. 
bfd	* targets.c: Wrap nfp_elf64_vec in BFD64 ifdef.

include	* opcode/nfp.h: Use uint64_t instead of bfd_vma.

opcodes	* nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 2018-05-15 13:28:06 +01:00
Jim Wilson
e6f372ba66 RISC-V: Add missing hint instructions from RV128I. 
gas/
	* testsuite/gas/riscv/c-zero-imm.d: Add more tests.
	* testsuite/gas/riscv/c-zero-imm.s: Likewise.
	* testsuite/gas/riscv/c-zero-reg.d: Fix typo in test.  Add disabled
	future test for RV128 support.
	* testsuite/gas/riscv/c-zero-reg.s: Likewise.

	include/
	* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
	(MATCH_C_SRAI64, MASK_C_SRAI64): New.
	(MATCH_C_SLLI64, MASK_C_SLLI64): New.

	opcodes/
	* riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
	(match_c_slli64, match_srxi_as_c_srxi): New.
	(riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
	<srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
	<c.slli, c.srli, c.srai>: Use match_s_slli.
	<c.slli64, c.srli64, c.srai64>: New.
 2018-05-08 15:46:19 -07:00
Peter Bergner
2ceb7719f7 Cleanup ppc code dealing with opcode dumps. 
include/
	* opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
	(vle_num_opcodes): Likewise.
	(spe2_num_opcodes): Likewise.

opcodes/
	* ppc-opc.c (powerpc_num_opcodes): Likewise.
	(vle_num_opcodes): Likewise.
	(spe2_num_opcodes): Likewise.
	* ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
	initialization loop.
	(disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
	(disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
	only once.

gas/
	* config/tc-ppc.c (ppc_setup_opcodes) <powerpc_opcodes>: Rewrite code
	to dump the entire opcode table.
	(ppc_setup_opcodes) <spe2_opcodes>: Likewise.
	(ppc_setup_opcodes) <vle_opcodes>: Likewise.  Fix calculation of
	opcode index.
 2018-05-07 09:40:59 -05:00
Francois H. Theron
fe944acf8f This patch adds support to objdump for disassembly of NFP (Netronome Flow Processor) ELF files (.nffw) as well as some basic readelf support. 
bfd	* Makefile.am: Added NFP files to build.
	* archures.c: Added bfd_arch_nfp
	* config.bfd: Added NFP support.
	* configure.ac: Added NFP support.
	* cpu-nfp.c: New, for NFP support.
	* elf-bfd.h: Added elf_section_info()
	* elf64-nfp.c: New, for NFP support.
	* po/SRC-POTFILES.in: Added NFP source files.
	* targets.c: Added nfp_elf64_vec
	* bfd-in2.h: Regenerate.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

binutils* readelf.c: Very basic support for EM_NFP and its section types.
	* testsuite/binutils-all/nfp: New directory.
	* testsuite/binutils-all/nfp/objdump.exp: New file.  Run new
	tests.
	* testsuite/binutils-all/nfp/test2_ctx8.d: New file.
	* testsuite/binutils-all/nfp/test2_no-pc_ctx4.d: New file.
	* testsuite/binutils-all/nfp/test1.d: New file.
	* testsuite/binutils-all/nfp/nfp6000.nffw: New file.
	* testsuite/binutils-all/nfp/test2_nfp6000.nffw: New file.
	* NEWS: Mention the new support.

include	* dis-asm.h: Added print_nfp_disassembler_options prototype.
	* elf/common.h: Added EM_NFP, officially assigned. See Google Group
	Generic System V Application Binary Interface.
	* elf/nfp.h: New, for NFP support.
	* opcode/nfp.h: New, for NFP support.

opcodes	Makefile.am: Added nfp-dis.c.
	configure.ac: Added bfd_nfp_arch.
	disassemble.h: Added print_insn_nfp prototype.
	disassemble.c: Added ARCH_nfp and call to print_insn_nfp
	nfp-dis.c: New, for NFP support.
	po/POTFILES.in: Added nfp-dis.c to the list.
	Makefile.in: Regenerate.
	configure: Regenerate.
 2018-04-30 17:02:59 +01:00
Alan Modra
c2bf1eecf9 Remove m88k support 
include/
	* coff/internal.h: Remove m88k support.
	* coff/m88k.h: Delete.
	* opcode/m88k.h: Delete.
bfd/
	* Makefile.am: Remove m88k support.
	* aoutx.h: Likewise.
	* archures.c: Likewise.
	* coffcode.h: Likewise.
	* coffswap.h: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* cpu-ns32k.c: Likewise.
	* elf32-nds32.c: Likewise.
	* mach-o.c: Likewise.
	* netbsd-core.c: Likewise.
	* reloc.c: Likewise.
	* targets.c: Likewise.
	* coff-m88k.c: Delete.
	* cpu-m88k.c: Delete.
	* elf32-m88k.c: Delete.
	* hosts/m88kmach3.h: Delete.
	* m88kmach3.c: Delete.
	* m88kopenbsd.c: Delete.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
opcodes/
	* Makefile.am: Remove m88k support.
	* configure.ac: Likewise.
	* disassemble.c: Likewise.
	* disassemble.h: Likewise.
	* m88k-dis.c: Delete.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
binutils/
	* MAINTAINERS (Mark Kettenis): Move to past maintainers.
	* testsuite/binutils-all/objdump.exp: Remove m88k support.
gas/
	* configure.ac: Remove m88k support.
	* config.in: Regenerate.
	* configure: Regenerate.
ld/
	* Makefile.am: Remove m88k support.
	* configure.host: Likewise.
	* configure.tgt: Likewise.
	* testsuite/ld-elf/sec-to-seg.exp: Likewise.
	* emulparams/m88kbcs.sh: Delete.
	* scripttempl/m88kbcs.sc: Delete.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
 2018-04-16 15:23:38 +09:30
Alan Modra
6793974daa Remove i370 support 
include/
	* elf/i370.h: Delete.
	* opcode/i370.h: Delete.
bfd/
	* Makefile.am: Remove i370 support.
	* archures.c: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* cpu-i370.c: Delete.
	* elf32-i370.c: Delete.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
opcodes/
	* Makefile.am: Remove i370 support.
	* configure.ac: Likewise.
	* disassemble.c: Likewise.
	* disassemble.h: Likewise.
	* i370-dis.c: Delete.
	* i370-opc.c: Delete.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
binutils/
	* readelf.c: Remove i370 support.
	* testsuite/binutils-all/objdump.exp: Likewise.
gas/
	* Makefile.am: Remove i370 support.
	* app.c: Likewise.
	* config/obj-elf.c: Likewise.
	* configure.tgt: Likewise.
	* doc/Makefile.am: Likewise.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/all/gas.exp: Likewise.
	* testsuite/gas/elf/warn-2.s: Likewise.
	* testsuite/gas/lns/lns.exp: Likewise.
	* config/tc-i370.c: Delete.
	* config/tc-i370.h: Delete.
	* doc/c-i370.texi: Delete.
	* Makefile.in: Regenerate.
	* doc/Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
ld/
	* Makefile.am: Remove i370 support.
	* configure.tgt: Likewise.
	* testsuite/ld-elf/compressed1d.d: Likewise.
	* testsuite/ld-elf/group8a.d: Likewise.
	* testsuite/ld-elf/group8b.d: Likewise.
	* testsuite/ld-elf/group9a.d: Likewise.
	* testsuite/ld-elf/group9b.d: Likewise.
	* testsuite/ld-elf/merge.d: Likewise.
	* testsuite/ld-elf/pr12851.d: Likewise.
	* testsuite/ld-elf/pr12975.d: Likewise.
	* testsuite/ld-elf/pr13177.d: Likewise.
	* testsuite/ld-elf/pr13195.d: Likewise.
	* testsuite/ld-elf/pr17615.d: Likewise.
	* testsuite/ld-elf/pr21562a.d: Likewise.
	* testsuite/ld-elf/pr21562b.d: Likewise.
	* testsuite/ld-elf/pr21562c.d: Likewise.
	* testsuite/ld-elf/pr21562d.d: Likewise.
	* testsuite/ld-elf/pr21562i.d: Likewise.
	* testsuite/ld-elf/pr21562j.d: Likewise.
	* testsuite/ld-elf/pr21562k.d: Likewise.
	* testsuite/ld-elf/pr21562l.d: Likewise.
	* testsuite/ld-elf/pr21562m.d: Likewise.
	* testsuite/ld-elf/pr21562n.d: Likewise.
	* testsuite/ld-elf/pr22677.d: Likewise.
	* testsuite/lib/ld-lib.exp: Likewise.
	* emulparams/elf32i370.sh: Delete.
	* scripttempl/elfi370.sc: Delete.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
 2018-04-16 15:21:56 +09:30
Alan Modra
fceadf0951 Remove tahoe support 
include/
	* opcode/tahoe.h: Delete.
bfd/
	* archures.c: Remove tahoe support.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* hosts/tahoe.h: Delete.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
opcodes/
	* configure.ac: Remove tahoe support.
	* configure: Regenerate.
binutils/
	* testsuite/binutils-all/objdump.exp: Remove tahoe support.
gprof/
	* Makefile.am: Remove tahoe support.
	* corefile.c: Likewise.
	* tahoe.c: Delete.
	* Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
 2018-04-16 15:08:40 +09:30
Alan Modra
a8eb42a8b7 Remove i860, i960, bout and aout-adobe targets 
Plus remove a few leftovers from the 29k support.

include/
	* aout/adobe.h: Delete.
	* aout/reloc.h: Delete.
	* coff/i860.h: Delete.
	* coff/i960.h: Delete.
	* elf/i860.h: Delete.
	* elf/i960.h: Delete.
	* opcode/i860.h: Delete.
	* opcode/i960.h: Delete.
	* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
	* aout/ar.h (ARMAGB): Remove.
	* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
	union internal_auxent): Remove i960 support.
bfd/
	* aout-adobe.c: Delete.
	* bout.c: Delete.
	* coff-i860.c: Delete.
	* coff-i960.c: Delete.
	* cpu-i860.c: Delete.
	* cpu-i960.c: Delete.
	* elf32-i860.c: Delete.
	* elf32-i960.c: Delete.
	* hosts/i860mach3.h: Delete.
	* Makefile.am: Remove i860, i960, bout, and adobe support.
	* archures.c: Remove i860 and i960 support.
	* coffcode.h: Likewise.
	* reloc.c: Likewise.
	* aoutx.h: Comment updates.
	* archive.c: Remove BOUT and i960 support.
	* bfd.c: Remove BOUT support.
	* coffswap.h: Remove i960 support.
	* config.bfd: Remove i860, i960 and adobe targets.
	* configure.ac: Remove adode, bout, i860, i960, icoff targets.
	* targets.c: Likewise.
	* ieee.c: Remove i960 support.
	* mach-o.c: Remove i860 support.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* libbfd.h: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
opcodes/
	* opcodes/i860-dis.c: Delete.
	* opcodes/i960-dis.c: Delete.
	* Makefile.am: Remove i860 and i960 support.
	* configure.ac: Likewise.
	* disassemble.c: Likewise.
	* disassemble.h: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
binutils/
	* ieee.c: Remove i960 support.
	* od-macho.c: Remove i860 support.
	* readelf.c: Remove i860 and i960 support.
	* testsuite/binutils-all/objcopy.exp: Likewise.
	* testsuite/binutils-all/objdump.exp: Likewise.
	* testsuite/lib/binutils-common.exp: Likewise.
gas/
	* config/aout_gnu.h: Delete.
	* config/tc-i860.c: Delete.
	* config/tc-i860.h: Delete.
	* config/tc-i960.c: Delete.
	* config/tc-i960.h: Delete.
	* doc/c-i860.texi: Delete.
	* doc/c-i960.texi: Delete.
	* testsuite/gas/i860/README.i860: Delete.
	* testsuite/gas/i860/bitwise.d: Delete.
	* testsuite/gas/i860/bitwise.s: Delete.
	* testsuite/gas/i860/branch.d: Delete.
	* testsuite/gas/i860/branch.s: Delete.
	* testsuite/gas/i860/bte.d: Delete.
	* testsuite/gas/i860/bte.s: Delete.
	* testsuite/gas/i860/dir-align01.d: Delete.
	* testsuite/gas/i860/dir-align01.s: Delete.
	* testsuite/gas/i860/dir-intel01.d: Delete.
	* testsuite/gas/i860/dir-intel01.s: Delete.
	* testsuite/gas/i860/dir-intel02.d: Delete.
	* testsuite/gas/i860/dir-intel02.s: Delete.
	* testsuite/gas/i860/dir-intel03-err.l: Delete.
	* testsuite/gas/i860/dir-intel03-err.s: Delete.
	* testsuite/gas/i860/dual01.d: Delete.
	* testsuite/gas/i860/dual01.s: Delete.
	* testsuite/gas/i860/dual02-err.l: Delete.
	* testsuite/gas/i860/dual02-err.s: Delete.
	* testsuite/gas/i860/dual03.d: Delete.
	* testsuite/gas/i860/dual03.s: Delete.
	* testsuite/gas/i860/fldst01.d: Delete.
	* testsuite/gas/i860/fldst01.s: Delete.
	* testsuite/gas/i860/fldst02.d: Delete.
	* testsuite/gas/i860/fldst02.s: Delete.
	* testsuite/gas/i860/fldst03.d: Delete.
	* testsuite/gas/i860/fldst03.s: Delete.
	* testsuite/gas/i860/fldst04.d: Delete.
	* testsuite/gas/i860/fldst04.s: Delete.
	* testsuite/gas/i860/fldst05.d: Delete.
	* testsuite/gas/i860/fldst05.s: Delete.
	* testsuite/gas/i860/fldst06.d: Delete.
	* testsuite/gas/i860/fldst06.s: Delete.
	* testsuite/gas/i860/fldst07.d: Delete.
	* testsuite/gas/i860/fldst07.s: Delete.
	* testsuite/gas/i860/fldst08.d: Delete.
	* testsuite/gas/i860/fldst08.s: Delete.
	* testsuite/gas/i860/float01.d: Delete.
	* testsuite/gas/i860/float01.s: Delete.
	* testsuite/gas/i860/float02.d: Delete.
	* testsuite/gas/i860/float02.s: Delete.
	* testsuite/gas/i860/float03.d: Delete.
	* testsuite/gas/i860/float03.s: Delete.
	* testsuite/gas/i860/float04.d: Delete.
	* testsuite/gas/i860/float04.s: Delete.
	* testsuite/gas/i860/form.d: Delete.
	* testsuite/gas/i860/form.s: Delete.
	* testsuite/gas/i860/i860.exp: Delete.
	* testsuite/gas/i860/iarith.d: Delete.
	* testsuite/gas/i860/iarith.s: Delete.
	* testsuite/gas/i860/ldst01.d: Delete.
	* testsuite/gas/i860/ldst01.s: Delete.
	* testsuite/gas/i860/ldst02.d: Delete.
	* testsuite/gas/i860/ldst02.s: Delete.
	* testsuite/gas/i860/ldst03.d: Delete.
	* testsuite/gas/i860/ldst03.s: Delete.
	* testsuite/gas/i860/ldst04.d: Delete.
	* testsuite/gas/i860/ldst04.s: Delete.
	* testsuite/gas/i860/ldst05.d: Delete.
	* testsuite/gas/i860/ldst05.s: Delete.
	* testsuite/gas/i860/ldst06.d: Delete.
	* testsuite/gas/i860/ldst06.s: Delete.
	* testsuite/gas/i860/pfam.d: Delete.
	* testsuite/gas/i860/pfam.s: Delete.
	* testsuite/gas/i860/pfmam.d: Delete.
	* testsuite/gas/i860/pfmam.s: Delete.
	* testsuite/gas/i860/pfmsm.d: Delete.
	* testsuite/gas/i860/pfmsm.s: Delete.
	* testsuite/gas/i860/pfsm.d: Delete.
	* testsuite/gas/i860/pfsm.s: Delete.
	* testsuite/gas/i860/pseudo-ops01.d: Delete.
	* testsuite/gas/i860/pseudo-ops01.s: Delete.
	* testsuite/gas/i860/regress01.d: Delete.
	* testsuite/gas/i860/regress01.s: Delete.
	* testsuite/gas/i860/shift.d: Delete.
	* testsuite/gas/i860/shift.s: Delete.
	* testsuite/gas/i860/simd.d: Delete.
	* testsuite/gas/i860/simd.s: Delete.
	* testsuite/gas/i860/system.d: Delete.
	* testsuite/gas/i860/system.s: Delete.
	* testsuite/gas/i860/xp.d: Delete.
	* testsuite/gas/i860/xp.s: Delete.
	* Makefile.am: Remove i860 and i960 support.
	* configure.tgt: Likewise.
	* doc/Makefile.am: Likewise.
	* doc/all.texi: Likewise.
	* testsuite/gas/all/gas.exp
	* config/obj-coff.h: Remove i960 support.
	* doc/internals.texi: Likewise.
	* expr.c: Likewise.
	* read.c: Likewise.
	* write.c: Likewise.
	* write.h: Likewise.
	* testsuite/gas/lns/lns.exp: Likewise.
	* testsuite/gas/symver/symver.exp: Likewise.
	* config/tc-m68k.c: Remove BOUT support.
	* config/tc-score.c: Likewise.
	* config/tc-score7.c: Likewise.
	* config/tc-sparc.c: Likewise.
	* symbols.c: Likewise.
	* doc/h8.texi: Likewise.
	* configure.ac: Remove BOUT and i860 support.
	* doc/as.texinfo: Remove BOUT, i860 and i960 support
	* Makefile.in: Regenerate.
	* config.in: Regenerate.
	* configure: Regenerate.
	* doc/Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
ld/
	* emulparams/coff_i860.sh: Delete.
	* emulparams/elf32_i860.sh: Delete.
	* emulparams/elf32_i960.sh: Delete.
	* emulparams/gld960.sh: Delete.
	* emulparams/gld960coff.sh: Delete.
	* emulparams/lnk960.sh: Delete.
	* emultempl/gld960.em: Delete.
	* emultempl/gld960c.em: Delete.
	* emultempl/lnk960.em: Delete.
	* scripttempl/i860coff.sc: Delete.
	* scripttempl/i960.sc: Delete.
	* ld.texinfo: Remove i960 support.
	* Makefile.am: Remove i860 and i960 support.
	* configure.tgt: Likewise.
	* testsuite/ld-discard/extern.d: Likewise.
	* testsuite/ld-discard/start.d: Likewise.
	* testsuite/ld-discard/static.d: Likewise.
	* testsuite/ld-elf/compressed1d.d: Likewise.
	* testsuite/ld-elf/group1.d: Likewise.
	* testsuite/ld-elf/group3b.d: Likewise.
	* testsuite/ld-elf/group8a.d: Likewise.
	* testsuite/ld-elf/group8b.d: Likewise.
	* testsuite/ld-elf/group9a.d: Likewise.
	* testsuite/ld-elf/group9b.d: Likewise.
	* testsuite/ld-elf/linkonce2.d: Likewise.
	* testsuite/ld-elf/merge.d: Likewise.
	* testsuite/ld-elf/merge2.d: Likewise.
	* testsuite/ld-elf/merge3.d: Likewise.
	* testsuite/ld-elf/orphan-10.d: Likewise.
	* testsuite/ld-elf/orphan-11.d: Likewise.
	* testsuite/ld-elf/orphan-12.d: Likewise.
	* testsuite/ld-elf/orphan-9.d: Likewise.
	* testsuite/ld-elf/orphan-region.d: Likewise.
	* testsuite/ld-elf/orphan.d: Likewise.
	* testsuite/ld-elf/orphan3.d: Likewise.
	* testsuite/ld-elf/pr12851.d: Likewise.
	* testsuite/ld-elf/pr12975.d: Likewise.
	* testsuite/ld-elf/pr13177.d: Likewise.
	* testsuite/ld-elf/pr13195.d: Likewise.
	* testsuite/ld-elf/pr17550a.d: Likewise.
	* testsuite/ld-elf/pr17550b.d: Likewise.
	* testsuite/ld-elf/pr17550c.d: Likewise.
	* testsuite/ld-elf/pr17550d.d: Likewise.
	* testsuite/ld-elf/pr17615.d: Likewise.
	* testsuite/ld-elf/pr20528a.d: Likewise.
	* testsuite/ld-elf/pr20528b.d: Likewise.
	* testsuite/ld-elf/pr21562a.d: Likewise.
	* testsuite/ld-elf/pr21562b.d: Likewise.
	* testsuite/ld-elf/pr21562c.d: Likewise.
	* testsuite/ld-elf/pr21562d.d: Likewise.
	* testsuite/ld-elf/pr21562i.d: Likewise.
	* testsuite/ld-elf/pr21562j.d: Likewise.
	* testsuite/ld-elf/pr21562k.d: Likewise.
	* testsuite/ld-elf/pr21562l.d: Likewise.
	* testsuite/ld-elf/pr21562m.d: Likewise.
	* testsuite/ld-elf/pr21562n.d: Likewise.
	* testsuite/ld-elf/pr22677.d: Likewise.
	* testsuite/ld-elf/pr22836-1a.d: Likewise.
	* testsuite/ld-elf/pr22836-1b.d: Likewise.
	* testsuite/ld-elf/pr349.d: Likewise.
	* testsuite/ld-elf/sec-to-seg.exp: Likewise.
	* testsuite/ld-elf/sec64k.exp: Likewise.
	* testsuite/ld-elf/warn1.d: Likewise.
	* testsuite/ld-elf/warn2.d: Likewise.
	* testsuite/ld-elf/warn3.d: Likewise.
	* testsuite/lib/ld-lib.exp: Likewise.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
 2018-04-11 21:49:30 +09:30
Nick Clifton
c8d59609b1 Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addressing with an assumed offset register. 
PR 22988
opcode	* opcode/aarch64.h (enum aarch64_opnd): Add
	AARCH64_OPND_SVE_ADDR_R.

opcodes	* aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
	instructions with only a base address register.
	* aarch64-opc.c (operand_general_constraint_met_p): Add code to
	handle AARHC64_OPND_SVE_ADDR_R.
	(aarch64_print_operand): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64_dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas	* config/tc-aarch64.c (parse_operands): Add code to handle
	AARCH64_OPN_SVE_ADDR_R.
	* testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
	with an assumed XZR offset address register.
	* testsuite/gas/aarch64/sve.d: Update expected disassembly.
 2018-03-28 09:44:45 +01:00
Jim Wilson
0e35537d75 RISC-V: Add .insn support. 
gas/ChangeLog
	2018-03-07  Kito Cheng  <kito.cheng@gmail.com>
	* config/tc-riscv.c (opcode_name_list): New.
	(opcode_names_hash): Likewise.
	(init_opcode_names_hash): Likewise.
	(opcode_name_lookup): Likewise.
	(validate_riscv_insn): New argument length, and add new format
	which used in .insn directive.
	(md_begin): Refine hash table initialization logic into
	init_opcode_hash.
	(init_opcode_hash): New.
	(my_getOpcodeExpression): Parse opcode name for .insn.
	(riscv_ip): New argument hash, able to handle .insn directive.
	(s_riscv_insn): Handler for .insn directive.
	(riscv_pseudo_table): New entry for .insn.
	* doc/c-riscv.texi: Add documentation for .insn directive.
	* testsuite/gas/riscv/insn.d: Add testcase for .insn directive.
	* testsuite/gas/riscv/insn.s: Likewise.

	include/ChangeLog
	2018-03-07  Kito Cheng  <kito.cheng@gmail.com>
	* opcode/riscv.h (OP_MASK_FUNCT3): New.
	(OP_SH_FUNCT3): Likewise.
	(OP_MASK_FUNCT7): Likewise.
	(OP_SH_FUNCT7): Likewise.
	(OP_MASK_OP2): Likewise.
	(OP_SH_OP2): Likewise.
	(OP_MASK_CFUNCT4): Likewise.
	(OP_SH_CFUNCT4): Likewise.
	(OP_MASK_CFUNCT3): Likewise.
	(OP_SH_CFUNCT3): Likewise.
	(riscv_insn_types): Likewise.

	opcodes/ChangeLog
	2018-03-07  Kito Cheng  <kito.cheng@gmail.com>
	* riscv-opc.c (riscv_insn_types): New.
 2018-03-14 16:04:03 -07:00
H.J. Lu
bd5dea8822 x86: Remove support for old (<= 2.8.1) versions of gcc 
Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and
fdivrp instructions.  Assembler translates them to correct ones with a
warning:

[hjl@gnu-cfl-1 gas]$ cat x.s
	fsubp %st(3),%st
[hjl@gnu-cfl-1 gas]$ gcc -c x.s
x.s: Assembler messages:
x.s:1: Warning: translating to `fsubp %st,%st(3)'
[hjl@gnu-cfl-1 gas]$

This patch removes support for old (<= 2.8.1) versions of gcc:

[hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s
x.s: Assembler messages:
x.s:1: Error: operand type mismatch for `fsubp'
[hjl@gnu-cfl-1 gas]$

gas/

	* NEWS: Mention -mold-gcc removal.
	* config/tc-i386.c (i386_error): Remove old_gcc_only.
	(old_gcc): Removed.
	(match_template): Remove old gcc support.
	(OPTION_MOLD_GCC): Removed.
	(OPTION_MRELAX_RELOCATIONS): Updated.
	(md_longopts): Remove OPTION_MOLD_GCC.
	(md_parse_option): Likewise.
	(md_show_usage): Remove -mold-gcc.
	* testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old
	(<= 2.8.1) versions of gcc.
	* testsuite/gas/i386/intel.s: Likewise.
	* testsuite/gas/i386/general.l: Updated.
	* testsuite/gas/i386/intel-intel.d: Likewise.
	* testsuite/gas/i386/intel.d: Likewise.
	* testsuite/gas/i386/intel.e: Likewise.
	* testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general.

include/

	* opcode/i386 (OLDGCC_COMPAT): Removed.

opcodes/

	* i386-gen.c (opcode_modifiers): Remove OldGcc.
	* i386-opc.h (OldGcc): Removed.
	(i386_opcode_modifier): Remove oldgcc.
	* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
	instructions for old (<= 2.8.1) versions of gcc.
	* i386-tbl.h: Regenerated.
 2018-03-08 06:31:52 -08:00
Thomas Preud'homme
5b616beff4 [ARM] Remove ARM_FEATURE_COPY macro 
Among the macros to manipulate an arm_feature_set structure is the
ARM_FEATURE_COPY which copy the value of a feature set into another.
This can be achieved with a simple assignement which most of the
existing code does. This patch removes the last 2 uses of that macro and
remove the macro altogether.

2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>

include/
	* opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition.

2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>

opcodes/
	* arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
	macro by assignements.
 2018-02-27 16:40:45 +00:00
Maciej W. Rozycki
75f3166520 MIPS16/opcodes: Free up `M' operand code 
The `M' and `m' MIPS16 operand codes are functionally the same, denoting
a 7-bit register list that is encoded the same way for both SAVE and
RESTORE.  Use `m' for both instructions then, making `M' available for a
different use.

	opcodes/
	* mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
	(mips16_opcodes): Replace `M' with `m' for "restore".

	include/
	* opcode/mips.h: Remove `M' operand code.
 2018-02-20 20:51:36 +00:00
Jim Wilson
645a2c5b46 RISC-V: Add 2 missing privileged registers. 
gas/
	* testsuite/gas/riscv/priv-reg.s: Add missing stval and mtval.
	* testsuite/gas/riscv/priv-reg.d: Likewise.

	include/
	* opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL.  Rename
	DECLARE_CSR entry.  Add alias to map sbadaddr to CSR_STVAL.
	(CSR_MBADADDR): Rename to CSR_MTVAL.  Rename DECLARE_CSR entry.
	Add alias to map mbadaddr to CSR_MTVAL.
 2018-01-04 14:17:53 -08:00
Alan Modra
219d1afa89 Update year range in copyright notice of binutils files 2018-01-03 17:49:56 +10:30
Jim Wilson
d9be0c189a RISC-V: Add missing privileged spec registers. 
gas/
	* testsuite/gas/riscv/priv-reg.d, testsuite/gas/riscv/priv-reg.s: New.

	include/
	* opcode/riscv-opc.h (DECLARE_CSR): Add missing privileged registers.
	Sort to match privileged spec documentation order.
	(DECLARE_CSR_ALIAS): Add ubadaddr, and comments.
 2017-12-28 13:21:46 -08:00
Tamar Christina
00c2093f69 Correct disassembly of dot product instructions. 
Dot products deviate from the normal disassembly rules for lane indexed
instruction. Their canonical representation is in the form of:

v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote
that these instructions select 4x 1 byte elements instead of a single 1 byte
element.

Previously we were disassembling them following the normal rules, this patch
corrects the disassembly.

gas/

	PR gas/22559
	* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
	* gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.

include/

	PR gas/22559
	* aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.

opcodes/

	PR gas/22559
	* aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
	AARCH64_OPND_QLF_S_4B
	* aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
	AARCH64_OPND_QLF_S_4B
	* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
	* aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
 2017-12-19 12:21:12 +00:00
Tamar Christina
a3b3345ae6 Add support for V_4B so we can properly reject it. 
Previously parse_vector_type_for_operand was changed to allow the use of 4b
register size for indexed lane instructions. However this had the unintended
side effect of also allowing 4b for normal vector registers.

Because this support was only partial the rest of the tool silently treated
4b as 8b and continued. This patch adds full support for 4b so it can be
properly distinguished from 8b and the correct errors are generated.

With this patch you still can't encode any instruction which actually requires
v<num>.4b but such instructions don't exist so to prevent needing a workaround
in get_vreg_qualifier_from_value this was just omitted.

gas/

	PR gas/22529
	* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B.
	* gas/testsuite/gas/aarch64/pr22529.s: New.
	* gas/testsuite/gas/aarch64/pr22529.d: New.
	* gas/testsuite/gas/aarch64/pr22529.l: New.

include/

	PR gas/22529
	* opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B.

opcodes/

	PR gas/22529
	* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
 2017-12-19 12:19:15 +00:00
Peter Bergner
0f873fd58b Use consistent types for holding instructions, instruction masks, etc. 
include/
	* opcode/ppc.h (PPC_INT_FMT): Define.
	(struct powerpc_opcode) <opcode>: Update type.
	(struct powerpc_opcode) <mask>: Likewise.
	(struct powerpc_opcode) <bitm>: Likewise.
	(struct powerpc_opcode) <insert>: Likewise.
	(struct powerpc_opcode) <extract>: Likewise.
	(ppc_optional_operand_value): Likewise.

gas/
	* config/tc-ppc.c (last_insn): Update type.
	(insn_validate) <omask, mask>: Likewise.
	(ppc_setup_opcodes) <mask, right_bit>: Likewise.
	<PRINT_OPCODE_TABLE>: Update types and printf format specifiers.
	(ppc_insert_operand): Update return and argument types and remove
	unneeded type casts.
	<min, max, right, tmp>: Update type.
	(md_assemble): Remove unneeded type casts.
	<insn, val, tmp_insn>: Update type.

opcodes/
	* opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
	(operand_value_powerpc): Update return and argument type.
	<value, top>: Update type.
	(skip_optional_operands): Update argument type.
	(lookup_powerpc): Likewise.
	(lookup_vle): Likewise.
	<table_opcd, table_mask, insn2>: Update type.
	(lookup_spe2): Update argument type.
	<table_opcd, table_mask, insn2>: Update type.
	(print_insn_powerpc) <insn, value>: Update type.
	Use PPC_INT_FMT for printing instructions and operands.
	* opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
	insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
	insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
	extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
	extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
	insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
	extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
	insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
	extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
	insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
	extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
	insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
	extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
	insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
	extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
	insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
	extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
	insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
	extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
	extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
	extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
	insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
	extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
	insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
	extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
	extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
	(OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
	BD24, BBO, Y_MASK  , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
	DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
	SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
	VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
	VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
	VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
	XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
	XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
	XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
	XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
 2017-12-01 11:20:15 -06:00
Tamar Christina
d0f7791c66 Add new AArch64 FP16 FM{A|S} instructions. 
This patch separates the new FP16 instructions backported from Armv8.4-a to Armv8.2-a
into a new flag order to distinguish them from the rest of the already existing optional
FP16 instructions in Armv8.2-a.

The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory on
Armv8.4-a.

gas/

	* config/tc-aarch64.c (fp16fml): New.
	* doc/c-aarch64.texi (fp16fml): New.
	* testsuite/gas/aarch64/armv8_2-a-crypto-fp16.d (fp16): Make fp16fml.
	* testsuite/gas/aarch64/armv8_3-a-crypto-fp16.d (fp16): Make fp16fml.

include/

	* opcode/aarch64.h: (AARCH64_FEATURE_F16_FML): New.
	(AARCH64_ARCH_V8_4): Enable AARCH64_FEATURE_F16_FML by default.

opcodes/

	* aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
	and AARCH64_FEATURE_F16.
 2017-11-16 16:27:35 +00:00
Tamar Christina
01f4802036 Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a into a new flag order to distinguish them from the rest of the already existing optional FP16 instructions in Armv8.2-a. 
The new flag "+fp16fml" is available from Armv8.2-a and implies +fp16 and is mandatory
from Armv8.4-a.

gas/

	* config/tc-arm.c (arm_ext_fp16_fml, fp16fml): New.
	(do_neon_fmac_maybe_scalar_long): Use arm_ext_fp16_fml.
	* doc/c-arm.texi (fp16, fp16fml): New.
	* testsuite/gas/arm/armv8_2-a-fp16.d (fp16): Make fp16fml.
	* testsuite/gas/arm/armv8_3-a-fp16.d (fp16): Make fp16fml.
	* testsuite/gas/arm/armv8_2-a-fp16-illegal.d (fp16): Make fp16fml.
	* testsuite/gas/arm/armv8_2-a-fp16-thumb2.d (fp16): Make fp16fml.

include/

	* opcode/arm.h: (ARM_EXT2_FP16_FML): New.
	(ARM_AEXT2_V8_4A): Add ARM_EXT2_FP16_FML.
 2017-11-15 15:56:23 +00:00
Tamar Christina
981b557a48 Enable the Dot Product extension by default for Armv8.4-a. 
include/

	* opcode/aarch64.h (AARCH64_ARCH_V8_4): Enable DOTPROD.

gas/testsuite

	* gas/aarch64/dotproduct_armv8_4.s: New.
	* gas/aarch64/dotproduct_armv8_4.d: New.
 2017-11-09 16:29:31 +00:00
Tamar Christina
f42f1a1d6c Adds the new Fields and Operand types for the new instructions in Armv8.4-a. 
gas/
	* config/tc-aarch64.c (process_omitted_operand):
	Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2
	and AARCH64_OPND_IMM_2.
	(parse_operands): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
	AARCH64_OPND_IMM_2, AARCH64_OPND_MASK
	and AARCH64_OPND_ADDR_OFFSET.

include/
	* opcode/aarch64.h:
	(aarch64_opnd): Add AARCH64_OPND_Va, AARCH64_OPND_MASK,
	AARCH64_OPND_IMM_2, AARCH64_OPND_ADDR_OFFSET
	and AARCH64_OPND_SM3_IMM2.
	(aarch64_insn_class): Add cryptosm3 and cryptosm4.
	(arch64_feature_set): Make uint64_t.

opcodes/
	* aarch64-asm.h (ins_addr_offset): New.
	* aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
	(aarch64_ins_addr_offset): New.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_addr_offset): New.
	* aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
	(aarch64_ext_addr_offset): New.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
	FLD_imm4_2 and FLD_SM3_imm2.
	* aarch64-opc.c (fields): Add FLD_imm6_2,
	FLD_imm4_2 and FLD_SM3_imm2.
	(operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
	(aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
	AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
	* aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
	* aarch64-tbl.h
	(aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
 2017-11-09 16:29:04 +00:00
Tamar Christina
b6b9ca0c3e Split the ARM Crypto ISA extensions for AES and SHA1+2 into their own options (+aes and +sha2). The reason for the split is because with the introduction of Armv8.4-a the implementation of AES has explicitly been made independent of the implementation of the other crypto extensions. 
gas	* config/tc-aarch64.c (aarch64_arch_option_table): Add armv8.4-a.
	(aarch64_features):	Added SM4 and SHA3.

include	* opcode/aarch64.h:
	(AARCH64_FEATURE_V8_4, AARCH64_FEATURE_SM4): New.
	(AARCH64_ARCH_V8_4, AARCH64_FEATURE_SHA3): New.

opcodes	* aarch64-tbl.h
	(aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
	(aarch64_feature_sm4, aarch64_feature_sha3): New.
	(aarch64_feature_fp_16_v8_2): New.
	(ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
	(V8_4_INSN, CRYPTO_V8_2_INSN): New.
	(SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
 2017-11-09 11:21:31 +00:00
Nick Clifton
21b81e67c7 Change the type of the aarch64_feature_set typedef to unsigned long long so that it will work on 32-bit hosts. 
* opcode/aarch64.h (aarch64_feature_set): Change type to unsigned
	long long.
 2017-11-09 10:28:32 +00:00
Nick Clifton
c0e7cef715 Split the AArch64 Crypto instructions for AES and SHA1+2 into their own options (+aes and +sha2). 
The new options are:

	+aes: Enables the AES instructions of Armv8-a,
	      enabled by default with +crypto.

	+sha2: Enables the SHA1 and SHA2 instructions of Armv8-a,
	       enabled by default with +crypto.

These options have been turned on by default when +crypto
is used, as such no breakage is expected.

The reason for the split is because with the introduction of Armv8.4-a
the implementation of AES has explicitly been made independent of the
implementation of the other crypto extensions. Backporting the split does
not break any of the previous requirements and so is safe to do.

gas	* config/tc-aarch64.c
	(aarch64_features): Include AES and SHA2 in CRYPTO.
	Add SHA2 and AES.

include	* opcode/aarch64.h:
	(AARCH64_FEATURE_SHA2, AARCH64_FEATURE_AES): New.

opcodes	* aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
	(aarch64_feature_sha2, aarch64_feature_aes): New.
	(SHA2, AES): New.
	(AES_INSN, SHA2_INSN): New.
	(pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
	(sha1h, sha1su1, sha256su0, sha1c, sha1p,
	 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
	Change to SHA2_INS.
 2017-11-08 14:30:53 +00:00
Jiong Wang
dec41383ff Adds command line support for Armv8.4-A, via the new command line option -march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A 
gas	* config/tc-arm.c (arm_extensions):
	(arm_archs): New entry for "armv8.4-a".
	Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8.
	(arm_ext_v8_2): New variable.
	(enum arm_reg_type): New enumeration REG_TYPE_NSD.
	(reg_expected_msgs): New entry for REG_TYPE_NSD.
	(parse_typed_reg_or_scalar): Handle REG_TYPE_NSD.
	(parse_scalar): Support REG_TYPE_VFS.
	(enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC.
	(parse_operands): Handle OP_RNSD and OP_RNSD_RNSC.
	(NEON_SHAPE_DEF): New entries for DHH and DHS.
	(neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding
	for new FP16 instructions in ARMv8.2-A.
	(do_neon_fmac_maybe_scalar_long): New function to encode new FP16
	instructions in ARMv8.2-A.
	(do_neon_vfmal): Wrapper function for vfmal.
	(do_neon_vfmsl): Wrapper function for vfmsl.
	(insns): New entries for vfmal and vfmsl.
	* doc/c-arm.texi (-march): Document "armv8.4-a".
	* testsuite/gas/arm/dotprod-mandatory.d: New test.
	* testsuite/gas/arm/armv8_2-a-fp16.s: New test source.
	* testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source.
	* testsuite/gas/arm/armv8_2-a-fp16.d: New test.
	* testsuite/gas/arm/armv8_3-a-fp16.d: New test.
	* testsuite/gas/arm/armv8_4-a-fp16.d: New test.
	* testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test.
	* testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test.
	* testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file.

opcodes	* arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
	FP16 instructions, including vfmal.f16 and vfmsl.f16.

include	* opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature.
	(ARM_EXT2_V8_4A): New macro.
	(ARM_AEXT2_V8_4A): Likewise.
	(ARM_ARCH_V8_4A): Likewise.
 2017-11-08 13:15:12 +00:00