* config/obj-elf.c (elf_adjust_symtab): New. Move group section
processing here from elf_frob_file. Ensure that group signature
symbols have the name of the group.
(elf_frob_file): Move group section processing to
elf_adjust_symtab.
* config/obj-elf.h (elf_adjust_symtab): Declare.
(obj_adjust_symtab): Define.
* config/tc-arm.c (arm_adjust_symtab): Call elf_adjust_symtab.
2010-10-23 Mark Mitchell <mark@codesourcery.com>
* gas/elf/elf.exp: Add group0c test.
* gas/elf/group0c.d: New.
* gas/elf/group0a.d: Expect ".group" for the name of group
sections.
* gas/elf/group0b.d: Likewise.
* gas/elf/group1a.d: Likewise.
* gas/elf/group1b.d: Likewise.
* gas/elf/groupautoa.d: Likewise.
* gas/elf/groupautob.d: Likewise.
* gas/elf/section4.d: Likewise.
* gas/ia64/group-1.d: Likewise. Adjust hard-coded constants.
2010-10-22 Mark Mitchell <mark@codesourcery.com>
* binutils-all/group-5.d: Expect ".group" for the name of group
sections.
* binutils-all/strip-2.d: Likewise.
2010-10-23 Mark Mitchell <mark@codesourcery.com>
* ld-elf/group10.d: Expect ".group" for the name of group
sections.
* ld-elf/group2.d: Likewise.
* ld-elf/group7.d: Likewise.
* emulparams/elf32_sparc_sol2.sh (OUTPUT_FORMAT): Set to
elf32-sparc-sol2.
* emulparams/elf64_sparc_sol2.sh (OUTPUT_FORMAT): Set to
elf64-sparc-sol2.
gas:
* config/tc-sparc.h [TE_SOLARIS] (ELF_TARGET_FORMAT): Define as
elf32-sparc-sol2.
(ELF64_TARGET_FORMAT): Define as elf64-sparc-sol2.
bfd:
* elfxx-sparc.c (tpoff): Define bed, static_tls_size.
Consider static_tls_alignment.
* elf32-sparc.c (TARGET_BIG_SYM): Redefine to
bfd_elf32_sparc_sol2_vec.
(TARGET_BIG_NAME): Redefine to elf32-sparc-sol2.
(elf32_bed): Redefine to elf32_sparc_sol2_bed.
(elf_backend_static_tls_alignment): Redefine to 8.
Include elf32-target.h.
(elf_backend_static_tls_alignment): Undef again for VxWorks.
* elf64-sparc.c (TARGET_BIG_SYM): Redefine to
bfd_elf64_sparc_sol2_vec.
(TARGET_BIG_NAME): Redefine to elf64-sparc-sol2.
(ELF_OSABI): Undef.
(elf64_bed): Redefine to elf64_sparc_sol2_bed.
(elf_backend_static_tls_alignment): Redefine to 16.
Include elf64-target.h.
* config.bfd (sparc-*-solaris2.[0-6]): Split from sparc-*-elf*.
Set targ_defvec to bfd_elf32_sparc_sol2_vec.
[BFD64] (sparc-*-solaris2*): Set targ_defvec to
bfd_elf32_sparc_sol2_vec.
Replace bfd_elf64_sparc_vec by bfd_elf64_sparc_sol2_vec in
targ_selvecs.
* configure.in: Handle bfd_elf32_sparc_sol2_vec,
bfd_elf64_sparc_sol2_vec.
* configure: Regenerate.
* targets.c (bfd_elf32_sparc_sol2_vec): Declare.
(bfd_elf64_sparc_sol2_vec): Declare.
(_bfd_target_vector): Add bfd_elf32_sparc_sol2_vec,
bfd_elf64_sparc_sol2_vec.
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
macros before their corresponding MIPS III hardware instructions.
gas/
* config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs.
gas/testsuite/
* gas/mips/lineno.s: Convert to o32.
* gas/mips/lineno.d: Adjust patterns accordingly. Force the o32
ABI.
The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode.
Once we've fixed that, it's easy to see that the disassembler also likes
to decode this insn incorrectly. So fix that and then add some tests.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
gas/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (_i386_insn): Add disp32_encoding.
(md_assemble): Don't call optimize_disp if disp32_encoding is
set.
(parse_insn): Support .d32 to force 32bit displacement.
(output_branch): Use BIG if disp32_encoding is set.
* doc/c-i386.texi: Document .d32 encoding suffix.
gas/testsuite/
2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/disp32.d: New.
* gas/i386/disp32.s: Likewise.
* gas/i386/x86-64-disp32.d: Likewise.
* gas/i386/x86-64-disp32.s: Likewise.
* gas/i386/i386.exp: Run disp32 and x86-64-disp32.
Currently, trying to declare single letter variables in Blackfin assembly
can sometimes lead to parser errors if that letter is used for insn flags.
For example, X, Z, S, M, and T are used to change the behavior of insns:
R0 = 1; R0 = 1 (X); R0 = 1 (Z);
But the current parser just looks for single letter tokens rather than
ones that show up in the (FLAGS) field. So only match these letters as
flags when they're in parentheses.
Not a complete fix, but it at least lets gcc tests pass now (the test
gcc/testsuite/gcc.c-torture/compile/mangle-1.c to be exact). A complete
fix would require a significant parser rewrite in order to handle:
R0 = (x) (x); /* zero extend the address of the symbol "x" */
R0 = W; R0 = W[P0];
Signed-off-by: Steve Kilbane <steve.kilbane@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current LOOP_BEGIN/LOOP_END pseudo insns hit parser errors when trying
to use numeric local labels. So add support for them.
Signed-off-by: David Gibson <david.gibson@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current LOOP_BEGIN/LOOP_END pseudo insns hit "Internal errors" when
using local labels as the loop names due to attempts at removing them.
Signed-off-by: David Gibson <david.gibson@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* config/tc-tic6x.c (tic6x_try_encode): Correct encoding of fstg field
in SPKERNEL instructions.
opcodes/
* tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
in SPKERNEL instructions.
gas/testsuite/
* gas/tic6x/insns-c674x-sploop.d: Add two more sploop/spkernel tests.
* gas/tic6x/insns-c674x-sploop.s: Likewise.
* elf32-arm.c (elf32_arm_stub_long_branch_any_arm_pic,
elf32_arm_stub_long_branch_any_arm_pic): Use a consistent name for
ip/r12.
(arm_type_of_stub): Remove superfluous braces.
gas/
* config/tc-arm.c (encode_branch): Remove superfluous braces.
(do_t_branch): Move reloc setting to end of routine.
* config/tc-mips.c (mips_fix_cn63xxp1): New variable.
(mips_ip): Add errata work around when mips_fix_cn63xxp1 set.
(OPTION_FIX_CN63XXP1, OPTION_NO_FIX_CN63XXP1): New enum options
enumerations.
(md_longopts): Add options for -mfix-cn63xxp1 and -mno-fix-cn63xxp1.
(md_parse_option): Handle OPTION_FIX_CN63XXP1 and
OPTION_NO_FIX_CN63XXP1.
(md_show_usage): Add documentation for -mfix-cn63xxp1.
* doc/c-mips.texi (-mfix-cn63xxp1, -mno-fix-cn63xxp1): Document
the new options.
2010-10-04 David Daney <ddaney@caviumnetworks.com>
* gas/mips/mips.exp (octeon-pref): Run the new test.
* gas/mips/octeon-pref.s: New test.
* gas/mips/octeon-pref.d: New expected results for the new test.
* gas/config/tc-arm.c (arm_ext_virt): New variable.
(arm_reg_type): Add REG_TYPE_RNB for banked registers.
(reg_entry): Allow registers to be larger than a byte.
(reg_alias): Fix type warning.
(parse_operands): Parse banked registers when appropriate.
(do_mrs): Add support for Virtualization Extensions.
(do_hvc): New function.
(do_t_mrs): Add support for Virtualization Extensions.
(do_t_msr): Likewise.
(do_t_hvc): New function.
(SPLRBANK): New define.
(reg_names): Add banked registers.
(insns): Add support for Virtualization Extensions.
(md_apply_fixup): Likewise.
(arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions.
(arm_extensions): Add 'virt' extension.
(aeabi_set_public_attributes): Add support for Virtualization
Extensions.
* gas/doc/c-arm.texi: Document 'virt' extension.
* gas/testsuite/gas/arm/armv7-a+virt.d: New test.
* gas/testsuite/gas/arm/armv7-a+virt.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions.
* gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test.
* gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise.
* include/opcode/arm.h (ARM_EXT_VIRT): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
Extensions.
* opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
(thumb32_opcodes): Likewise.
(banked_regname): New function.
(print_insn_arm): Add Virtualization Extensions support.
(print_insn_thumb32): Likewise.
(do_div): New function.
(insns): Accept UDIV and SDIV in ARM state.
(arm_cpus): The cortex-a15 option has all current v7-A extensions.
(arm_extensions): Add 'idiv' extension.
(aeabi_set_public_attributes): Update Tag_DIV_use values for the
Integer Divide extension.
* gas/doc/c-arm.texi: Document the idiv extension.
* gas/testsuite/gas/arm/armv7-a+idiv.d: New test.
* gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension.
* gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test.
* include/opcode/arm.h (ARM_AEXT_ADIV): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
* opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
ARM state.
(arm_ext_m): Add support for OS extension.
(arm_ext_os): New variable.
(do_t_swi): In v6-M ensure we have the OS extension.
(arm_cpus): The cortex-m1 and cortex-m0 options have the OS
extension by default.
(arm_archs): Add armv6s-m.
(arm_extensions): Add 'os' extension.
(cpu_arch_ver): Add support for v6S-M.
* gas/doc/c-arm.texi: Document the OS Extension, and v6-m and v6s-m
architecture options.
* gas/testsuite/gas/arm/archv6s-m-bad.d: New test.
* gas/testsuite/gas/arm/archv6s-m-bad.l: Likewise.
* gas/testsuite/gas/arm/archv6s-m.d: Likewise.
* gas/testsuite/gas/arm/archv6s-m.s: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6s-m.d: Likewise.
* include/opcode/arm.h (ARM_EXT_OS): New define.
(ARM_AEXT_V6SM): Likewise.
(ARM_ARCH_V6SM): Likewise.
Check for & reject attempts to use multiple store insns in a single
parallel insn combination. These are illegal per the Blackfin ISA.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin ISA supports moving just about anything to/from EMUDAT, so
make sure the assembler accepts these insns too.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Using "Register mismatch" everywhere can be a bit vague, so clarify
why exactly we're barfing on these unsupported insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some extended registers when given to the DBG/DBGCMPLX pseudo insns are
not encoded properly. So fix them, fix the display of them when being
disassembled, and add testcases.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Accept any 8bit char with the high bit set so as to support multibyte
characters. Also use the locale safe regular expressions to match
chars/digits. This brings the Blackfin assembler inline with the
behavior of other assemblers.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Support a few more ASTAT bits with the standard insns that operate on
ASTAT bits directly.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The disassembler has partial (but incomplete/broken) support already for
the pseudo debug insn OUTC, so let's fix it up and finish it. And now
that the disassembler can handle it, make sure our assembler can output
it too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
There is a pseudo debug insn named ABORT that is commonly used in
simulation, so support it in the assembler too. The disassembler
already supports it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We don't use the # character in the Blackfin assembly language, so let it
start end-of-line comments like most other assemblers.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* gas/testsuite/gas/arm/attr-cpu-directive.d: Update test for change in canonical
CPU name.
* gas/testsuite/gas/arm/attr-mcpu.d: Likewise.
* ld/testsuite/ld-arm/attr-merge-6.attr: Update tests for change in canonical
CPU name.
* ld/testsuite/ld-arm/attr-merge-7.attr: Likewise.
* ld/testsuite/ld-arm/attr-merge-2.attr: Likewise.
* ld/testsuite/ld-arm/attr-merge-arch-2.attr: Likewise.
* config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead
of just RR.
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand.
* gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also
add disassembly for test added in copro.s
2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
