(s_mips_globl): New static function; needed for Irix 5 support.
* ecoff.c (ecoff_build_symbols): If BSF_FUNCTION is set for an
external symbol with no type, set the type to st_Proc rather than
st_Global. Don't set the index of an external st_Proc or
st_StaticProc symbol unless it is also a local symbol.
(insns_since_cache_access): New static variable.
(md_begin): Set mips_cpu as well as mips_isa.
(append_insn): If mips_cpu is 4600, require four nop instructions
between an instruction which accesses the cache and certain CACHE
instructions. Keep track of the number of instructions seen since
an instruction which accesses the cache.
(md_parse_option): Set mips_cpu as well as mips_isa.
PR 5433.
(macro): Correct M_LI_SS SVR4_PIC/EMBEDDED_PIC case. After M_LI_D
or M_L_DOB or label dob, force a new frag to avoid getting
confused in tc_gen_reloc.
(mips_ip): Use RDATA_SECTION_NAME, not .rdata.
(s_change_sec): Likewise.
with the preceding instruction even if .set nobopt has been seen.
.set nobopt actually controls whether to bring up an instruction
from the branch target, which gas does not currently support.
* config/tc-mips.c (macro_build): Permit BFD_RELOC_PCREL_LO16 for
certain cases of 'i', 'j' and 'o'. Change 'u' to take an
argument, the reloc type.
(load_register): Pass reloc type to macro_build for 'u'.
(macro): Likewise. For M_LA_AB permit a difference expression
when generating embedded PIC code between an arbitrary symbol and
a symbol in the .text section.
(mips_force_relocation): Force BFD_RELOC_PCREL_HI16_S and
BFD_RELOC_PCREL_LO16 to be emitted.
(md_apply_fix): Check that most relocs are not PC relative.
Handle BFD_RELOC_PCREL_HI16_S and BFD_RELOC_PCREL_LO16.
(tc_gen_reloc): Change #error to as_fatal. Handle
BFD_RELOC_PCREL_LO16 and BFD_RELOC_PCREL_HI16_S.
macro_build for nori case.
(SWITCH_TABLE): Define.
(mips_force_relocation): Force a relocation for a switch table
entry.
(md_apply_fix): Write switch table entry value into file.
(tc_gen_reloc): Use BFD_RELOC_GPREL32 for a switch table entry,
and set the addend to the difference between the reloc address and
the subtrahend.
embedded PIC code, accept the difference between two local symbols
as being constant.
(mips_force_relocation): Only force a reloc to be generated for a
PC relative fixup.
(md_apply_fix): For BFD_RELOC_32 and BFD_RELOC_LO16, put the fixup
value into the file if the fixup will not generate a reloc.
branch with an instruction that uses $at, in case the branch is
later expanded.
(macro): If EMBEDDED_PIC, case M_JAL_A may use $at.
(md_pcrel_from): If not OBJ_AOUT, return 4 for an undefined symbol
to make it pcrel_offset.
(tc_gen_reloc): If not OBJ_AOUT, set the reloc addend to
reloc->address; another gruesome hack to get gas reloc handling to
do the right thing.
(mips_pic): Change from int to enum mips_pic_level. Change all
uses (0 becomes NO_PIC, 2 becomes SVR4_PIC).
(load_address): Handle EMBEDDED_PIC.
(macro): Handle EMBEDDED_PIC in all PIC cases.
(md_parse_option): Accept -membedded-pic to use EMBEDDED_PIC. If
OBJ_ELF, accept -KPIC and -call_shared to use SVR4_PIC and accept
-non_shared to use NO_PIC (this is how the Irix 5 assembler
works). Do not permit -G with SVR4_PIC.
(s_abicalls): Warn if -G was used, and force -G 0.
(tc_gen_reloc): Set reloc->addend to 0 for a PC relative reloc for
anything but a.out, not just for ELF. For ECOFF, don't generate a
BFD_RELOC_16_PCREL_S2 reloc unless using EMBEDDED_PIC.
(md_parse_option): Set g_switch_seen for -G option.
(s_option): If creating PIC code, force the GP size to be 0. Warn
if -G switch used with a non-zero value.
* listing.c: Include subsegs.h.
(listing_prev_line): New function.
(calc_hex): Reset byte_in_frag to zero for each new frag.
* config/tc-mips.c (append_insn): Call listing_prev_line after
emitting nop instructions.
* Makefile.in (listing.o): Depends upon subsegs.h.
OBJ_ECOFF in many cases.
(mips_any_noreorder): New variable.
(mips_cprestore_offset): Initialize to -1.
(mips_frame_reg): New variable.
(RELAX_ENCODE, RELAX_OLD, RELAX_NEW, RELAX_RELOC1,
RELAX_RELOC2, RELAX_RELOC3, RELAX_WARN): New macros.
(md_pseudo_table): Handle "gpword" and "cpadd".
(md_begin): Initialize ok to false. If OBJ_ELF, set alignment
of text, data and bss sections to 4. Set alignment of
.reginfo section to 2. If ECOFF_DEBUGGING, create .mdebug
section.
(ALIGN_ERR, ALIGN_ERR2): Removed unused and useless alignment
check.
(append_insn, macro_build, macro_build_lui): Take place
argument. Changed all callers.
(append_insn): If appending a nop, don't emit one.
(macro_build): Changed assertion for 'i', 'j', 'o' case.
(gp_reference): Removed.
(load_address): New function.
(macro): If mips_noreorder is used, set mips_any_noreorder.
Extensive changes to handle GP and PIC symbols differently.
Build both possible code choices using a variant frag, and
make a final decision at the end of assembly when all
information is known. Added PIC support for all symbol
references.
(mips_ip): Don't permit anything but a number after $ for a
coprocessor register. Don't use .lit4 or .lit8 sections when
generating PIC code. If OBJ_ELF, set alignment of .lit4 or
.lit8 section to 4.
(md_apply_fix): Accept and ignore GOT16 and GPREL32 relocs.
(s_change_sec): Set alignment of ELF .rodata or .sdata section
to 4.
(s_mipsset): If .set noreorder, set mips_any_noreorder.
(s_cpload): Ignore .cpload if not generating PIC code. Warn
if .cpload is not in noreorder section.
(s_cprestore): Ignore .cprestore if not generating PIC code.
(s_gpword, s_cpadd): New functions.
(tc_get_register): Added frame argument; if true, set
mips_frame_reg to return value. Changed all callers.
(md_estimate_size_before_relax): Don't error out, but instead
determine how much a frag should grow.
(tc_gen_reloc): Return multiple relocs if appropriate, as
determined by md_estimate_size_before_relax.
(md_convert_frag): New function.
(mips_elf_final_processing): Set ELF header flags based on
mips_any_noreorder and mips_pic.
* config/tc-mips.h (RELOC_EXPANSION_POSSIBLE): Define.
(MAX_RELOC_EXPANSION): Define to be 3.
(md_relax_frag): Define to be 0.
(md_convert_frag): Don't define.
(tc_get_register): Changed declaration.
(mips_regmask_frag): New static variable, if OBJ_ELF.
(md_begin): If OBJ_ELF, create .reginfo section and set
mips_regmask_frag to a frag.
(mips_elf_final_processing): New function, if OBJ_ELF. Set
mips_regmask_frag to register mask information.
* config/tc-mips.h (elf_tc_final_processing): New macro, defined
if OBJ_ELF.
hold register masks.
(md_begin): Initialize them to zero.
(append_insn): Update mips_gprmask and mips_cprmask. Also add
register variables pinfo and prev_pinfo.
* config/tc-mips.h (mips_gprmask, mips_cprmask): Declare.
* config/obj-ecoff.c (ecoff_frob_file): If TC_MIPS, set gprmask
and cprmask from mips_gprmask and mips_cprmask.
* config/tc-mips.c (GPOPT): Define if OBJ_ECOFF or OBJ_ELF.
(various): Change all references to GP references to apply if
GPOPT, not if OBJ_ECOFF.
(s_change_sec): Rearrange somewhat. If OBJ_ELF, use .rodata
instead of .rdata. If OBJ_ELF, set section flags for .rodata and
.sdata sections.
(s_frame, s_loc, s_mask): Comment out entire functions, rather
than just body. They're not used anyhow.
* configure.in: Set cpu_type to mips for mips*. Accept
mips-*-elfl* and mips-*-elf*.
Wrote non-BFD_ASSEMBLER subseg_new. Now subseg_new always takes a
section name, and subseg_set always takes a segT. Changed all
callers as appropriate.
* config/obj-coffbfd.c (change_to_section): Renamed to
obj_coff_add_segment. Corrected. Made callers use subseg_new.
* config/obj-coffbfd.h (obj_segment_name, obj_add_segment):
Define.
Also some more gcc warning removal.
* config/tc-mips.c (macro_build): Accept 'z', and ignore it.
(macro): Use "z,s,t" for div instructions to match corresponding
change in opcode table.
(mips_ip): Added 'z'--must be zero register.
