Previously GAS would accept .u32, .u16 and .u8 suffixes to the VQ(R)DMLAH and VQ(R)DMLASH
instructions, however the Armv8.1-M Mainline specification states that these functions only
have signed variations (.s32, .s16 and .s8 suffixes).
This is documented here:
https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf?_ga=2.143079093.1892401233.1563295591-999473562.1560847439#page=1183
gas * config/tc-arm.c (do_mve_vqdmlah): Use N_S_32 macro.
(do_neon_qrdmlah): Use N_S_32 macro.
* testsuite/gas/arm/mve-vqdmlah-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlah-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlah-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlah.d: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlah.s: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlash-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlash-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlash-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlash.d: Remove unsigned instruction tests.
* testsuite/gas/arm/mve-vqdmlash.s: Remove unsigned instruction tests.
opcodes * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
instructions.
New instruction are added, and some of them are overlapping. Update
disassembler to correctly recognize them. Introduce nps400 option.
opcodes/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
and MPY class instructions.
(parse_option): Add nps400 option.
(print_arc_disassembler_options): Add nps400 info.
gas/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/nps400-6.d: Update test.
When SHF_GNU_MBIND was added in the SHF_LOOS to SHF_HIOS range, it
should have required ELFOSABI_GNU since these flags are already in use
by other OSes. HPUX SHF_HP_TLS in fact has the same value. That
means no place in binutils should test SHF_GNU_MBIND without first
checking OSABI, and SHF_GNU_MBIND should not be set without also
setting OSABI. At least, that's the ideal, but the patch accepts
SHF_GNU_MBIND on ELFOSABI_NONE object files since gas didn't always
set OSABI. However, to reinforce the fact that SHF_GNU_MBIND isn't
proper without a non-zero OSABI, readelf will display the flag as
LOOS+0 if OSABI isn't set.
The clash with SHF_HP_TLS means that hppa64-linux either has that flag
on .tbss sections or supports GNU_MBIND, not both. (hppa64-linux
users, if there are any, may have noticed that GNU ld since 2017
mysteriously aligned their .tbss sections to a 4k boundary. That was
one consequence of SHF_HP_TLS being blindly interpreted as
SHF_GNU_MBIND.) Since it seems that binutils, gdb, gcc, glibc, and
the linux kernel don't care about SHF_HP_TLS I took that flag out of
.tbss for hppa64-linux.
bfd/
* elf-bfd.h (enum elf_gnu_osabi): Add elf_gnu_osabi_mbind.
* elf.c (_bfd_elf_make_section_from_shdr): Set elf_gnu_osabi_mbind.
(get_program_header_size): Formatting. Only test SH_GNU_MBIND
when elf_gnu_osabi_mbind is set.
(_bfd_elf_map_sections_to_segments): Likewise.
(_bfd_elf_init_private_section_data): Likewise.
(_bfd_elf_final_write_processing): Update comment.
* elf64-hppa.c (elf64_hppa_special_sections): Move .tbss entry.
(elf_backend_special_sections): Define without .tbss for linux.
binutils/
* readelf.c (get_parisc_segment_type): Split off hpux entries..
(get_ia64_segment_type): ..and these..
(get_hpux_segment_type): ..to here.
(get_segment_type): Condition GNU_MBIND on osabi. Use
get_hpux_segment_type.
(get_symbol_binding): Do not print UNIQUE for ELFOSABI_NONE.
(get_symbol_type): Do not print IFUNC for ELFOSABI_NONE.
gas/
* config/obj-elf.c (obj_elf_change_section): Don't emit a fatal
error for non-SHF_ALLOC SHF_GNU_MBIND here.
(obj_elf_parse_section_letters): Return SHF_GNU_MBIND in new
gnu_attr param.
(obj_elf_section): Adjust obj_elf_parse_section_letters call.
Formatting. Set SHF_GNU_MBIND and elf_osabi from gnu_attr.
Emit normal error for non-SHF_ALLOC SHF_GNU_MBIND and wrong osabi.
(obj_elf_type): Set elf_osabi for ifunc.
* testsuite/gas/elf/section12a.d: xfail msp430 and hpux.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.l: Adjust expected error.
ld/
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Condition
SHF_GNU_MBIND on osabi. Set output elf_gnu_osabi_mbind.
The instructions that this change apply to are:
VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH
The updated documentation is here: https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf
Fixed this by removing the check for this warning from GAS as well as opcodes.
Added testcases to test that the warning is not generated for the instructions that have a 32-bit element size
and the same source and destination operand. Also fixed tests that would previously check for this warning.
gas * config/tc-arm.c (do_mve_vqdmladh): Remove check for UNPREDICTABLE.
* testsuite/gas/arm/mve-vqdmladh-bad.l: Remove tests.
* testsuite/gas/arm/mve-vqdmladh-bad.s: Remove tests.
* testsuite/gas/arm/mve-vqdmladh.d: New tests.
* testsuite/gas/arm/mve-vqdmladh.s: New tests.
* testsuite/gas/arm/mve-vqdmlsdh-bad.l: Remove tests.
* testsuite/gas/arm/mve-vqdmlsdh-bad.s: Remove tests.
* testsuite/gas/arm/mve-vqdmlsdh.d: New tests.
* testsuite/gas/arm/mve-vqdmlsdh.s: New tests.
opcodes * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
instructions as UNPREDICTABLE.
This patch changes the eBPF CPU description to prefer the register
names %r0 and %r6 instead of %a and %ctx when disassembling. This
matches better with the current practice, vs. cBPF.
It also updates the GAS tests in order to reflect this change.
Tested in a x86_64 host.
cpu/ChangeLog:
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
%a and %ctx.
opcodes/ChangeLog:
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-desc.c: Regenerated.
gas/ChangeLog:
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.
* testsuite/gas/bpf/lddw-be.d: Likewise.
* testsuite/gas/bpf/lddw.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
Tested in a x86_64 host.
gas/ChangeLog:
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (pe_lcomm_internal): Adapted from tc-i386.c.
(pe_lcomm): Likewise.
(md_pseudo_table): Use pe_lcomm to implement .lcomm.
After some discussion, we've decided to rename the +bitperm feature
flag to +sve2-bitperm, so that it's consistent with the other SVE2
feature flags. The associated internal macros already used
"SVE2_BITPERM", so only the feature flag itself needs to change.
2019-07-19 Richard Sandiford <richard.sandiford@arm.com>
gas/
* doc/c-aarch64.texi: Remame the +bitperm extension to +sve2-bitperm.
* config/tc-aarch64.c (aarch64_features): Likewise.
* testsuite/gas/aarch64/illegal-sve2-aes.d: Update accordingly.
* testsuite/gas/aarch64/illegal-sve2-sha3.d: Likewise.
* testsuite/gas/aarch64/illegal-sve2-sm4.d: Likewise.
* testsuite/gas/aarch64/illegal-sve2.d: Likewise.
* testsuite/gas/aarch64/sve2.d: Likewise.
This patch supports using pcrel instructions in TLS code sequences. A
number of new relocations are needed, gas operand modifiers to
generate those relocations, and new TLS optimisation. For
optimisation it turns out that the new pcrel GD and LD sequences can
be distinguished from the non-pcrel GD and LD sequences by there being
different relocations on the new sequence. The final "add ra,rb,13"
on IE sequences similarly needs a new relocation, or as I chose, a
modification of R_PPC64_TLS. On pcrel IE code, the R_PPC64_TLS points
one byte into the "add" instruction rather than being on the
instruction boundary.
GD:
pla 3,z@got@tlsgd@pcrel # R_PPC64_GOT_TLSGD34
bl __tls_get_addr@notoc(z@tlsgd) # R_PPC64_TLSGD and R_PPC64_REL24_NOTOC
edited to IE
pld 3,z@got@tprel@pcrel
add 3,3,13
edited to LE
paddi 3,13,z@tprel
nop
LD:
pla 3,z@got@tlsld@pcrel # R_PPC64_GOT_TLSLD34
bl __tls_get_addr@notoc(z@tlsld) # R_PPC64_TLSLD and R_PPC64_REL24_NOTOC
..
paddi 9,3,z2@dtprel
pld 10,z3@got@dtprel@pcrel
add 10,10,3
edited to LE
paddi 3,13,0x1000
nop
IE:
pld 9,z@got@tprel@pcrel # R_PPC64_GOT_TPREL34
add 3,9,z@tls@pcrel # R_PPC64_TLS at insn+1
ldx 4,9,z@tls@pcrel
lwax 5,9,z@tls@pcrel
stdx 5,9,z@tls@pcrel
edited to LE
paddi 9,13,z@tprel
nop
ld 4,0(9)
lwa 5,0(9)
std 5,0(9)
LE:
paddi 10,13,z@tprel
include/
* elf/ppc64.h (R_PPC64_TPREL34, R_PPC64_DTPREL34),
(R_PPC64_GOT_TLSGD34, R_PPC64_GOT_TLSLD34),
(R_PPC64_GOT_TPREL34, R_PPC64_GOT_DTPREL34): Define.
(IS_PPC64_TLS_RELOC): Include new tls relocs.
bfd/
* reloc.c (BFD_RELOC_PPC64_TPREL34, BFD_RELOC_PPC64_DTPREL34),
(BFD_RELOC_PPC64_GOT_TLSGD34, BFD_RELOC_PPC64_GOT_TLSLD34),
(BFD_RELOC_PPC64_GOT_TPREL34, BFD_RELOC_PPC64_GOT_DTPREL34),
(BFD_RELOC_PPC64_TLS_PCREL): New pcrel tls relocs.
* elf64-ppc.c (ppc64_elf_howto_raw): Add howtos for pcrel tls relocs.
(ppc64_elf_reloc_type_lookup): Translate pcrel tls relocs.
(must_be_dyn_reloc, dec_dynrel_count): Add R_PPC64_TPREL64.
(ppc64_elf_check_relocs): Support pcrel tls relocs.
(ppc64_elf_tls_optimize, ppc64_elf_relocate_section): Likewise.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Map "tls@pcrel", "got@tlsgd@pcrel",
"got@tlsld@pcrel", "got@tprel@pcrel", and "got@dtprel@pcrel".
(fixup_size, md_assemble): Handle pcrel tls relocs.
(ppc_force_relocation, ppc_fix_adjustable): Likewise.
(md_apply_fix, tc_gen_reloc): Likewise.
ld/
* testsuite/ld-powerpc/tlsgd.d,
* testsuite/ld-powerpc/tlsgd.s,
* testsuite/ld-powerpc/tlsie.d,
* testsuite/ld-powerpc/tlsie.s,
* testsuite/ld-powerpc/tlsld.d,
* testsuite/ld-powerpc/tlsld.s: New tests.
* testsuite/ld-powerpc/powerpc.exp: Run them.
This little patch adds support to the eBPF port of GAS for a few data
directives. The names for the directives have been chosen to be
coherent with the suffixes used in eBPF instructions: b, h, w and dw
for 8, 16, 32 and 64-bit values respectively.
Documentation and tests included.
Tested in a x86_64 host.
gas/ChangeLog:
2019-07-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_pseudo_table): .half, .word and .dword.
* testsuite/gas/bpf/data.s: New file.
* testsuite/gas/bpf/data.d: Likewise.
* testsuite/gas/bpf/data-be.d: Likewise.
* testsuite/gas/bpf/bpf.exp: Run data and data-be.
* doc/c-bpf.texi (BPF Directives): New section.
Once operand parsing has completed, the simpler check of Operand_Mem can
be used in places where i.types[] got passed to operand_type_check().
Note that this has shown a couple of omissions of adjusting i.flags[]
when playing with i.op[] / i.types[] / i.tm.operand_types[]. Not all of
them get added here, just all of the ones needed in process_operands().
... instead of an operand type bit: It's an insn property, not an
operand one. There's just one actual change to be made to the
templates: Most are now required to have the (unswapped) destination go
into ModR/M.rm, so VMOVD template needs its opcode adjusted accordingly
and its operands swapped. {,V}MOVS{S,D}, otoh, are left alone in this
regard, as otherwise generated code would differ from what we've been
producing so far (which I don't think is wanted).
Take the opportunity and add a missing IgnoreSize to pextrb (leading to
an error in 16-bit mode), and take the liberty to once again drop stray
IgnoreSize attributes from lines changed and neighboring related ones.
They're the only exception to there generally being no mix of register
kinds possible in an insn operand template, and there being two bits per
operand for their representation is also quite wasteful, considering the
low number of uses. Fold both bits and deal with the little bit of
fallout.
Also take the liberty and drop dead code trying to set REX_B: No segment
register has RegRex set on it.
Additionally I was quite surprised that PUSH/POP with the permitted
segment registers is not covered by the test cases. Add the missing
pieces.
This patch fixes the eBPF CPU description in order to reflect the
right explicit arguments passed to the ldabs{b,h,w,dw} instructions,
updates the corresponding GAS tests, and updates the BPF section of
the GAS manual.
cpu/ChangeLog:
2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (dlabs): New pmacro.
(dlind): Likewise.
opcodes/ChangeLog:
2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-desc.c: Regenerate.
* bpf-opc.c: Likewise.
* bpf-opc.h: Likewise.
gas/ChangeLog:
2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'
register as an argument.
* testsuite/gas/bpf/mem.d: Updated accordingly.
* testsuite/gas/bpf/mem-be.d: Likewise.
* doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct
explicit arguments to ldabs and ldind instructions.
The eBPF non-generic load instructions ldind{b,h,w,dw} and
ldabs{b,h,w,dw} do not take an explicit destination register as an
argument. Instead, they put the loaded value in %r0, implicitly.
This patch fixes the CPU BPF description to not expect a 'dst'
argument in these arguments, regenerates the corresponding files in
opcodes, and updates the impacted GAS tests.
Tested in a x86-64 host.
cpu/ChangeLog:
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (dlsi): ldabs and ldind instructions do not take an
explicit 'dst' argument.
opcodes/ChangeLog:
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-desc.c: Regenerate.
* bpf-opc.c: Likewise.
gas/ChangeLog:
2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/mem.s: Do not use explicit arguments for
ldabs and ldind instructions.
* testsuite/gas/bpf/mem.d: Updated accordingly.
* testsuite/gas/bpf/mem-be.d: Likewise.
git commit f2d4ba38f5 caused many failures for mips-sgi-irix targets,
and added a new test that failed for aarch64, nds32, and rl78.
The mips failures are due to BSF_OBJECT being set in many cases for
symbols by the mips .global/.globl directive. This patch removes that
code and instead sets BSF_OBJECT in a target frob_symbol function,
also moving the mips hacks in elf_frob_symbol to the new function.
Note that common symbols are handled fine in elf.c:swap_out_syms
without needing to set BSF_OBJECT, so that old code can disappear.
* config/obj-elf.c (elf_frob_symbol): Remove mips hacks.
* config/tc-mips.h (tc_frob_symbol): Define.
(mips_frob_symbol): Declare.
* config/tc-mips.c (s_mips_globl): Don't set BSF_OBJECT for irix.
(mips_frob_symbol): Fudge symbols for irix here.
* testsuite/gas/elf/type-2.e: Allow random target symbols.
From Kito Cheng <kito.cheng@sifive.com>
gas/ChangeLog
* doc/c-riscv.texi (Instruction Formats): Add r4 type.
* testsuite/gas/riscv/insn.d: Add testcase for r4 type.
* testsuite/gas/riscv/insn.s: Ditto.
* doc/c-riscv.texi (Instruction Formats): Add b and j type.
* testsuite/gas/riscv/insn.d: Add test case for b and j type.
* testsuite/gas/riscv/insn.s: Ditto.
* testsuite/gas/riscv/insn.s: Correct instruction type for load
and store.
* testsuite/gas/riscv/insn.d: Using regular expression to match
address.
* doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB
type and fix typo.
opcode/ChangeLog
* riscv-opc.c (riscv_insn_types): Add r4 type.
* riscv-opc.c (riscv_insn_types): Add b and j type.
* opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
format for sb type and correct s type.
For another patch I wanted to use a sufficiently benign option (simply
to be able to specify one, which certain test case invocations require),
and I stumbled across -Q in the --help output. Before realizing that
this is x86-specific anyway, I've tried and and ran into a mysterious
testsuite failure, until I further realized that other than the help
text suggests the option requires an argument. Correct the help text,
and make the implementation actually match what the comment there has
been describing (and what the help text now says).
Recently a patch was submitted for a Xen Project test harness binary to
override the compiler specified @object to @func (see [1]). In a reply I
suggested we shouldn't make ourselves dependent on currently unspecified
behavior of gas here: It accumulates all requests, and then
bfd/elf.c:swap_out_syms(), in an apparently ad hoc manner, prioritizes
certain flags over others.
Make the behavior predictable: Generally the last .type is what counts.
Exceptions are directives which set multiple bits (TLS, IFUNC, and
UNIQUE): Subsequent directives requesting just the more generic bit
(i.e. FUNC following IFUNC) won't clear the more specific one. Warn
about incompatible changes, except from/to STT_NOTYPE.
Also add a new target hook, which hppa wants to use right away afaict.
In the course of adding the warning I ran into two ld testsuite
failures. I can only assume that it was a copy-and-paste mistake that
lead to the same symbol having its type set twice.
[1] https://lists.xenproject.org/archives/html/xen-devel/2019-05/msg01980.html
For example, when provided with the (incorrect) instruction
st4 {v0.16b-v3.16b}[4],[x0]
currently assembler provides the following error message
"Error: comma expected between operands at operand 2 -- `st4 {v0.16b-v3.16b}[4],[x0]'".
This was due to the assembler consuming the {v0.16b-v3.16b} as the first operand leaving
[4],[x0] as what it believed to be the second operand.
The actual error is that the first operand should be of element type and not
vector type (as provided). The new diagnostic for this error is
"Error: expected element type rather than vector type at operand 1 -- `st4 {v0.16b-v3.16b}[4],[x0]'.
Added testcases to check for the correct diagnostic message as well as checking that
variations of the structural load/store by element instruction also generate the error
when they have the same problem.
* config/tc-aarch64.c (parse_operands): Add error check.
* testsuite/gas/aarch64/diagnostic.l: New test.
* testsuite/gas/aarch64/diagnostic.s: New test.
* testsuite/gas/aarch64/illegal.l: New tests.
* testsuite/gas/aarch64/illegal.s: New tests.
The entry for the FMOV alias of FCPY was missing C_SCAN_MOVPRFX.
(The entry for FCPY itself was OK.)
This was the only /m-predicated instruction I could see that was
missing the flag.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
SVE FMOV alias of FCPY.
gas/
* testsuite/gas/aarch64/sve-movprfx_27.s,
* testsuite/gas/aarch64/sve-movprfx_27.d: New test.
SVE FCVTZS, FCVTZU, SCVTF and UCVTF need the same treatment as FCVT:
the register size used in a predicated MOVPRFX must be the wider of
the destination and source sizes.
Since I was adding a (supposedly) complete set of tests for converts,
it seemed more consistent to add a complete set of tests for shifts
as well, even though there's no bug to fix there.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
gas/
* testsuite/gas/aarch64/sve-movprfx_26.s: Also test FCVTZS, FCVTZU,
SCVTF, UCVTF, LSR and ASR.
* testsuite/gas/aarch64/sve-movprfx_26.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_26.l: Likewise.
One of the MOVPRFX tests has:
output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1'
But X1 and Z1 are not the same register, so the instruction is
actually OK.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
registers in an instruction prefixed by MOVPRFX.
gas/
* testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1
to be prefixed by MOVPRFX.
* testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
PR 24748
* write.c (create_note_reloc): Add desc2_offset parameter. Change
name of offset parameter to note_offset. Only use desc2_offset
when placing addend into REL reloc's address space.
(maybe_generate_build_notes): Update parameters passed to
create_note_reloc.
I had mistakenly given all variants of the new SVE2 instructions
pmull{t,b} a dependency on the feature +sve2-aes.
Only the variant specifying .Q -> .D sizes should have that
restriction.
This patch fixes that mistake and updates the testsuite to have extra
tests (matching the given set of tests per line in aarch64-tbl.h that
the rest of the SVE2 tests follow).
We also add a line in the documentation of the command line to clarify
how to enable `pmull{t,b}` of this larger size. This is needed because
all other instructions gated under the `sve2-aes` architecture extension
are marked in the instruction documentation by an `HaveSVE2AES` check
while pmull{t,b} is gated under the `HaveSVE2PMULL128` check.
Regtested targeting aarch64-linux.
gas/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: Update tests.
* testsuite/gas/aarch64/illegal-sve2.l: Update tests.
* doc/c-aarch64.texi: Add special note of pmull{t,b}
instructions under the sve2-aes architecture extension.
* testsuite/gas/aarch64/illegal-sve2.s: Add small size
pmull{t,b} instructions.
* testsuite/gas/aarch64/sve2.d: Add small size pmull{t,b}
disassembly.
* testsuite/gas/aarch64/sve2.s: Add small size pmull{t,b}
instructions.
include/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): sve_size_013
renamed to sve_size_13.
opcodes/ChangeLog:
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
sve_size_13 icode to account for variant behaviour of
pmull{t,b}.
* aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
(OP_SVE_VVV_Q_D): Add new qualifier.
(OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
(struct aarch64_opcode): Split pmull{t,b} into those requiring
AES and those not.
It is pretty wasteful to have a per-operand flag which is used in
exactly 4 cases. It can be relatively easily replaced, and by doing so
I've actually found some dead code to remove at the same time (there's
no case of ImmExt set at the same time as Vec_Imm4).
In quite a few cases ImmExt gets used when there's not really any
immediate, but rather a degenerate ModR/M byte. ENCL{S,U} show how this
case is supposed to be dealt with. Eliminate most abuses, leaving in
place (for now) only ones where process_immext() is involved.
It seems to be not uncommon for people to use AND or OR in this form for
just setting the status flags. TEST, which doesn't write to any
register other than EFLAGS, ought to be preferred. Make the change only
for -O2 and above though, at least for now.
When they're in the 0F opcode space, swapping their source operands may
allow switching from 3-byte to 2-byte VEX prefix encoding. Note that NaN
behavior precludes us doing so for many packed and scalar floating point
insns; such an optimization would need to be done by the compiler
instead in this case, when it knows that NaN-s have undefined behavior
anyway.
While for explicitly specified AVX/AVX2 insns the optimization (for now
at least) gets done only for -O2 and -Os, it is utilized by default in
SSE2AVX mode, as there we're re-writing the programmer's specified insns
anyway.
Rather than introducing a new attribute flag, the change re-uses one
which so far was meaningful only for EVEX-encoded insns.
This implication allows to simplify some conditionals, thus slightly
improving performance. This change also paves the way for re-using
StaticRounding for non-EVEX insns.
As long as there's no write mask as well as no broadcast, and as long
as the scaled Disp8 wouldn't result in a shorter EVEX encoding, encode
VPAND{D,Q}, VPANDN{D,Q}, VPOR{D,Q}, and VPXOR{D,Q} acting on only the
lower 16 XMM/YMM registers using their VEX equivalents with -O1.
Also take the opportunity and avoid looping twice over all operands
when dealing with memory-with-displacement ones.
While the ISA extensions doc suggests them to be made available just
like the SDM does for the PCLMULQDQ ISA extension, these weren't added
when supposrt for the new extension was introduced.
Also make sure the 64-bit non-AVX512 test actually tests VEX encodings,
not EVEX ones.
For example, this code is invalid:
smc #0x6951
The code would previously check for and encode for up to 16 bit immediate values, however
this immediate should instead be only a 4 bit value
(as documented herehttps://static.docs.arm.com/ddi0406/c/DDI0406C_C_arm_architecture_reference_manual.pdf ).
Fixed this by adding range checks in the relevant areas and also removing code that would
encode more than the first 4 bits of the immediate (code that is now redundant, as any immediate operand
larger than 0xF would error now anyway).
gas * config/tc-arm.c (do_smc): Add range check for immediate operand.
(do_t_smc): Add range check for immediate operand. Remove
obsolete immediate encoding.
(md_apply_fix): Fix range check. Remove obsolete immediate encoding.
* testsuite/gas/arm/arch6zk.d: Fix test.
* testsuite/gas/arm/arch6zk.s: Fix test.
* testsuite/gas/arm/smc-bad.d: New test.
* testsuite/gas/arm/smc-bad.l: New test.
* testsuite/gas/arm/smc-bad.s: New test.
* testsuite/gas/arm/thumb32.d: Fix test.
* testsuite/gas/arm/thumb32.s: Fix test.
These encodings aren't valid in real and VM86 modes, but they are very
well usable in 16-bit protected mode.
A few adjustments in the disassembler tables are needed where Ev or Gv
were wrongly used. Additionally an adjustment is needed to avoid
printing "addr32" when that's already recognizable by the use of %eiz.
Furthermore the Iq operand template was wrong for XOP:0Ah encoding
insns: They're having a uniform 32-bit immediate. Drop Iq and introduce
Id instead.
Clone a few existing test cases to exercise assembler and disassembler.
Noticed by a customer while looking at a tangentially related problem. The
gas testsuite for xstormy16 has two scripts that have a typo on the first
line, they are missing the !. They also use shell syntax that doesn't work
on a system where /bin/sh is dash. So I fixed the typo, changed the shell
to bash, and made them executable, so that they now work when run directly
even if /bin/sh is dash.
gas/
* testsuite/gas/xstormy16/allinsn.sh: Change first line to
#!/bin/bash and make it executable.
* testsuite/gas/xstormy16/gcc.sh: Likewise.
When MTHC1 instruction is paired with MTC1 to write a value to a
64-bit FPR, the MTC1 must be executed first, because the semantic
definition of MTC1 is not aware that software will be using an MTHC1
to complete the operation, and sets the upper half of the 64-bit FPR
to an UNPREDICTABLE value[1].
Fix the order of MTHC1 and MTC1 instructions in LI macro expansion.
Modify the expansions to exploit moves from $zero directly by-passing
the use of $AT, where ever possible.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Wave Computing, Inc., Document
Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2
"Alphabetical List of Instructions", pp. 217.
gas/
* config/tc-mips.c (macro) <M_LI>: Re-order MTHC1 with
respect to MTC1 and use $0 for either part where possible.
* testsuite/gas/mips/li-d.s: Add test cases for non-zero
words in double precision constants.
* testsuite/gas/mips/li-d.d: Update reference output.
* testsuite/gas/mips/micromips@isa-override-1.d: Likewise.
* testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise.
* testsuite/gas/mips/mips64r2@isa-override-1.d: Likewise.
For quite some time we've been using combinations of bits for
specifying various registers in operands and templates. I think it was
Alan who had indicated that likely the debug printing would need
adjustment as a result. Here we go.
Accumulator handling for GPRs gets changed to match that for FPU regs.
For this to work, OPERAND_TYPE_ACC{32,64} get repurposed, with their
original uses replaced by direct checks of the two bits of interest,
which is cheaper than operand_type_equal() invocations.
For SIMD registers nothing similar appears to be needed, as respective
operands get stripped from the (copy of the) template before pt() is
reached.
The type change on pi() is to silence a compiler diagnostic. Arguably
its other parameter could also be const-qualified.
MOVNTI was wrongly assembled with a 66h prefix. Add IgnoreSize to
address this. It and the scalar to/from integer conversion insns also
were also wrongly using Ev / Gv, leading to 16-bit register names being
printed when 32-bit ones were meant.
Clone the 32-bit SSE2 test to cover both assembler and disassembler.
This patch corrects ppc rs_align_code handling to choose the alignment
nops based on the machine in force at the alignment directive rather
than the machine at the end of file.
* config/tc-ppc.h (ppc_nop_select): Declare.
(NOP_OPCODE): Define.
* config/tc-ppc.c (ppc_elf_end, ppc_xcoff_end): Zero ppc_cpu.
(ppc_nop_encoding_for_rs_align_code): New enum.
(ppc_nop_select): New function.
(ppc_handle_align): Don't use ppc_cpu here. Get nop type from frag.
* testsuite/gas/ppc/groupnop.d,
* testsuite/gas/ppc/groupnop.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
If VEX.vvvv and EVEX.vvvv are reserved, they must be all 1s, which are
all 0s in inverted form. Add check for unused VEX.vvvv and EVEX.vvvv
when disassembling VEX and EVEX instructions.
gas/
PR binutils/24626
* testsuite/gas/i386/disassem.s: Add tests for reserved VEX.vvvv
and EVEX.vvvv.
* testsuite/gas/i386/x86-64-disassem.s: Likewise.
* testsuite/gas/i386/disassem.d: Updated.
* testsuite/gas/i386/x86-64-disassem.d: Likewise.
opcodes/
PR binutils/24626
* i386-dis.c (print_insn): Check for unused VEX.vvvv and
EVEX.vvvv when disassembling VEX and EVEX instructions.
(OP_VEX): Set vex.register_specifier to 0 after readding
vex.register_specifier.
(OP_Vex_2src_1): Likewise.
(OP_Vex_2src_2): Likewise.
(OP_LWP_E): Likewise.
(OP_EX_Vex): Don't check vex.register_specifier.
(OP_XMM_Vex): Likewise.
This fixes a bug reported on the riscv.org sw-dev mailing list. This
rejects "lui x1,symbol", as a symbol should only be accepted here when
used inside %hi(). Without the fix, this gets assembled as "lui x1,0"
with no relocation which is clearly wrong.
gas/
* config/tc-riscv.c (riscv_ip) <'u'>: Move O_constant check inside if
statement. Delete O_symbol and O_constant check after if statement.
* testsuite/gas/riscv/auipc-parsing.s: Test lui with missing %hi.
* testsuite/gas/riscv/auipc-parsing.l: Update.
For AVX512 instructions with Disp8ShiftVL and Broadcast, we may need to
add CheckRegSize to check if broadcast matches the destination register
size.
gas/
PR gas/24625
* testsuite/gas/i386/inval-avx512f.s: Add tests for AVX512_BF16
instructions with invalid broadcast.
* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.
* testsuite/gas/i386/inval-avx512f.l: Updated.
* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.
opcodes/
PR gas/24625
* i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
Disp8ShiftVL.
* i386-tbl.h: Regenerated.
Targets that lack ppc64 support were failing the new prefix-reloc
test. This patch adds some test infrastructure to deal with that, and
changes the powerpc gas usage info so that "-a64" is omitted when
unsupported.
I've been meaning to break up the usage message for a long time;
While doing so causes translators some work now, it should make it
easier next time a new powerpc option is added.
* config/tc-ppc.c (is_ppc64_target): New function.
(md_show_usage): Split up usage message. Don't show -a64 when
unsupported.
testsuite/gas/ppc/ppc.exp (supports_ppc64): New.
(prefix-reloc): Only run for ppc64.
Allow st_other values such as STO_AARCH64_VARIANT_PCS to be set for alias
symbols independently. This is needed for ifunc symbols which are
aliased to the resolver using .set and don't expect resolver attributes
to override the ifunc symbol attributes. This means .variant_pcs must be
added explicitly to aliases.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_elf_copy_symbol_attributes): Define.
* config/tc-aarch64.h (aarch64_elf_copy_symbol_attributes): Declare.
(OBJ_COPY_SYMBOL_ATTRIBUTES): Define.
* testsuite/gas/aarch64/symbol-variant_pcs-3.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-3.s: New test.
In ELF objects the specified symbol is marked with STO_AARCH64_VARIANT_PCS.
gas/ChangeLog:
* config/tc-aarch64.c (s_variant_pcs): New function.
* doc/c-aarch64.texi: Document .variant_pcs.
* testsuite/gas/aarch64/symbol-variant_pcs-1.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-1.s: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-2.d: New test.
* testsuite/gas/aarch64/symbol-variant_pcs-2.s: New test.
This patch adds initial 64-bit insn assembler/disassembler support.
The only instruction added is "pnop" along with the automatic aligning
of prefix instruction so they do not cross 64-byte boundaries.
include/
* dis-asm.h (WIDE_OUTPUT): Define.
* opcode/ppc.h (prefix_opcodes, prefix_num_opcodes): Declare.
(PPC_OPCODE_POWERXX, PPC_GET_PREFIX, PPC_GET_SUFFIX),
(PPC_PREFIX_P, PPC_PREFIX_SEG): Define.
opcodes/
* ppc-dis.c (ppc_opts): Add "future" entry.
(PREFIX_OPCD_SEGS): Define.
(prefix_opcd_indices): New array.
(disassemble_init_powerpc): Initialize prefix_opcd_indices.
(lookup_prefix): New function.
(print_insn_powerpc): Handle 64-bit prefix instructions.
* ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
(PMRR, POWERXX): Define.
(prefix_opcodes): New instruction table.
(prefix_num_opcodes): New constant.
binutils/
* objdump.c (disassemble_bytes): Set WIDE_OUTPUT in flags.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Handle prefix_opcodes.
(struct insn_label_list): New.
(insn_labels, free_insn_labels): New variables.
(ppc_record_label, ppc_clear_labels, ppc_start_line_hook): New funcs.
(ppc_frob_label, ppc_new_dot_label): Move functions earlier in file
and call ppc_record_label.
(md_assemble): Handle 64-bit prefix instructions. Align labels
that are on the same line as a prefix instruction.
* config/tc-ppc.h (tc_frob_label, ppc_frob_label): Move to
later in the file.
(md_start_line_hook): Define.
(ppc_start_line_hook): Declare.
* testsuite/gas/ppc/prefix-align.d,
* testsuite/gas/ppc/prefix-align.s: New test.
* testsuite/gas/ppc/ppc.exp: Run new test.
This option (also implied by --traditional) causes '$' to introduce
literal hexadecimal constants, rather than the modern convention '0x'.
gas/
* config/tc-s12z.c (s12z_strtol): New function. (md_show_usage): Update.
(md_parse_option): new case OPTION_DOLLAR_HEX. (s12z_init_after_args):
(<global>): Use s12z_strtol instead of strtol.
* doc/c-s12z.texi (S12Z Options): Document new option -mdollar-hex.
* testsuite/gas/s12z/dollar-hex.d: New file.
* testsuite/gas/s12z/dollar-hex.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
This patch makes changes to the <spec_reg> operand for VMRS and VMSR
instructions as per the Armv8.1-M Mainline.
New <spec_reg> options to support are:
0b0010: FPSCR_nzcvqc, access to FPSCR condition and saturation flags.
0b1100: VPR, privileged only access to the VPR register.
0b1101: P0, access to VPR.P0 predicate fields
0b1110: FPCXT_NS, enables saving and restoring of Non-secure floating
point context.
0b1111: FPCXT_S, enables saving and restoring of Secure floating point
context
*** gas/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (parse_operands): Update case OP_RVC to
parse p0 and P0.
(do_vmrs): Add checks for valid operands with respect to
cpu and fpu options.
(do_vmsr): Likewise.
(reg_names): New reg_names for FPSCR_nzcvqc, VPR, FPCXT_NS
and FPCXT_S.
* testsuite/gas/arm/armv8_1-m-spec-reg.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg.s: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.d: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad1.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad2.l: New.
* testsuite/gas/arm/armv8_1-m-spec-reg-bad3.l: New.
* testsuite/gas/arm/vfp1xD.d: Updated to allow new valid values.
* testsuite/gas/arm/vfp1xD_t2.d: Likewise.
*** opcodes/ChangeLog ***
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (coprocessor_opcodes): New instructions for VMRS
and VMSR with the new operands.
This patch adds the following instructions which are part of the
Armv8.1-M Mainline:
CINC
CINV
CNEG
CSINC
CSINV
CSNEG
CSET
CSETM
CSEL
gas/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* config/tc-arm.c (TOGGLE_BIT): New.
(T16_32_TAB): New entries for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm and csel.
(operand_parse_code): New OP_RR_ZR.
(parse_operand): Handle case for OP_RR_ZR.
(do_t_cond): New.
(insns): New instructions for cinc, cinv, cneg, csinc,
csinv, csneg, cset, csetm, csel.
* testsuite/gas/arm/armv8_1-m-cond-bad.d: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.l: New test.
* testsuite/gas/arm/armv8_1-m-cond-bad.s: New test.
* testsuite/gas/arm/armv8_1-m-cond.d: New test.
* testsuite/gas/arm/armv8_1-m-cond.s: New test.
opcodes/ChangeLog:
2019-05-21 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (enum mve_instructions): New enum
for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
and cneg.
(mve_opcodes): New instructions as above.
(is_mve_encoding_conflict): Add cases for csinc, csinv,
csneg and csel.
(print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
The MIPS64R6 TRM requires that the source register for DAUI
not be r0.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 67-68.
gas/
* testsuite/gas/mips/r6-branch-constraints.s: Rename to ...
* testsuite/gas/mips/r6-reg-constraints.s: this and add test
case for DAUI.
* testsuite/gas/mips/r6-branch-constraints.l: Rename to ...
* testsuite/gas/mips/r6-reg-constraints.l: this and add test
for DAUI.
* testsuite/gas/mips/mips.exp: Rename test from
r6-branch-constraints to r6-reg-constraints.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Change source register
constraint for DAUI.
gas/ChangeLog:
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 24559
* config/tc-arm.c (move_or_literal_pool): Set size_req to 0
for MOVW replacement.
* testsuite/gas/arm/load-pseudo.s: New test input.
* testsuite/gas/arm/m0-load-pseudo.d: New test.
* testsuite/gas/arm/m23-load-pseudo.d: New test.
* testsuite/gas/arm/m33-load-pseudo.d: New test.
In an upcoming commit, I need to be able to set the prefix used
to introduce hexadecimal literal constants using a command line
flag. This is not currently possible, because the switch which
determines this (LITERAL_PREFIXDOLLAR_HEX) is a macro set at
build time.
This change substitutes it for a variable to be set at start up.
gas/ChangeLog:
* expr.c (literal_prefix_dollar_hex): New variable.
(operand)[case '$']: Use the new variable instead of the old macro.
Also, move this instance of "case '$'" next to the other one, and
enable it only in the complementary proprocessor case.
* expr.h (literal_prefix_dollar_hex): Declare it.
* config/tc-epiphany.c (md_begin): Assign literal_prefix_dollar_hex.
* config/tc-ip2k.c: ditto
* config/tc-mt.c: ditto
* config/tc-epiphany.h (LITERAL_PREFIXDOLLAR_HEX): Remove macro definition.
* config/tc-ip2k.h: ditto
* config/tc-mt.h: ditto
On IRIX 5, every global symbol that is not explicitly labelled as
being a function is assumed to be an object. There is no reason
why IRIX behaviour should extend to all MIPS targets, so limit this
to only IRIX targets.
gas/
PR 14798
* config/tc-mips.c (s_mips_globl): Only treat symbols that are
not explicitly labelled as BSF_OBJECTs for IRIX targets.
* testsuite/gas/mips/pr14798.s: New test source.
* testsuite/gas/mips/pr14798-irix.d: New test.
* testsuite/gas/mips/pr14798.d: Likewise.
* testsuite/gas/mips/mips.exp: Run the new tests.
binutils/
PR 14798
* testsuite/binutils-all/readelf.ss-mips: Update reference output.
* testsuite/binutils-all/readelf.ss-tmips: Likewise.
ld/
PR 14798
* testsuite/ld-mips-elf/reloc-6a.s: Specify .text section for
global code symbols.
* testsuite/ld-mips-elf/reloc-6b.s: Likewise.
In an upcoming commit, I need to be able to set the prefix used
to introduce hexadecimal literal constants using a command line
flag. This is not currently possible, because the switch which
determines this (LITERAL_PREFIXDOLLAR_HEX) is a macro set at
build time.
This change substitutes it for a variable to be set at start up.
gas/ChangeLog:
* expr.c (literal_prefix_dollar_hex): New variable.
(operand)[case '$']: Use the new variable instead of the old macro.
* expr.h (literal_prefix_dollar_hex): Declare it.
* config/tc-epiphany.c (md_begin): Assign literal_prefix_dollar_hex.
* config/tc-ip2k.c: ditto
* config/tc-mt.c: ditto
* config/tc-epiphany.h (LITERAL_PREFIXDOLLAR_HEX): Remove macro definition.
* config/tc-ip2k.h: ditto
* config/tc-mt.h: ditto
GNU policy is not to include trademark acknowlegements in
documentation [1]
[1] https://www.gnu.org/prep/standards/html_node/Trademarks.html
Committing as obvious.
gas/
* doc/c-arm.texi (ARM Options): Remove "(r)" and "(tm)"
* doc/c-bfin.texi (Blackfin Syntax): Remove "(r)"
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/gas/arm/mve-tailpredloop.d: New test.
* testsuite/gas/arm/mve-tailpredloop.s: New test.
* testsuite/gas/arm/mve-vabav.d: New test.
* testsuite/gas/arm/mve-vabav.s: New test.
* testsuite/gas/arm/mve-vabd.d: New test.
* testsuite/gas/arm/mve-vabd.s: New test.
* testsuite/gas/arm/mve-vabsneg.d: New test.
* testsuite/gas/arm/mve-vabsneg.s: New test.
* testsuite/gas/arm/mve-vadc.d: New test.
* testsuite/gas/arm/mve-vadc.s: New test.
* testsuite/gas/arm/mve-vaddlv.d: New test.
* testsuite/gas/arm/mve-vaddlv.s: New test.
* testsuite/gas/arm/mve-vaddsub.d: New test.
* testsuite/gas/arm/mve-vaddsub.s: New test.
* testsuite/gas/arm/mve-vaddv.d: New test.
* testsuite/gas/arm/mve-vaddv.s: New test.
* testsuite/gas/arm/mve-vand.d: New test.
* testsuite/gas/arm/mve-vand.s: New test.
* testsuite/gas/arm/mve-vbic.d: New test.
* testsuite/gas/arm/mve-vbic.s: New test.
* testsuite/gas/arm/mve-vbrsr.d: New test.
* testsuite/gas/arm/mve-vbrsr.s: New test.
* testsuite/gas/arm/mve-vcadd.d: New test.
* testsuite/gas/arm/mve-vcadd.s: New test.
* testsuite/gas/arm/mve-vcls.d: New test.
* testsuite/gas/arm/mve-vcls.s: New test.
* testsuite/gas/arm/mve-vclz.d: New test.
* testsuite/gas/arm/mve-vclz.s: New test.
* testsuite/gas/arm/mve-vcmla.d: New test.
* testsuite/gas/arm/mve-vcmla.s: New test.
* testsuite/gas/arm/mve-vcmp.d: New test.
* testsuite/gas/arm/mve-vcmp.s: New test.
* testsuite/gas/arm/mve-vcmul.d: New test.
* testsuite/gas/arm/mve-vcmul.s: New test.
* testsuite/gas/arm/mve-vcvt-1.d: New test.
* testsuite/gas/arm/mve-vcvt-1.s: New test.
* testsuite/gas/arm/mve-vcvt-2.d: New test.
* testsuite/gas/arm/mve-vcvt-2.s: New test.
* testsuite/gas/arm/mve-vcvt-3.d: New test.
* testsuite/gas/arm/mve-vcvt-3.s: New test.
* testsuite/gas/arm/mve-vcvt-4.d: New test.
* testsuite/gas/arm/mve-vcvt-4.s: New test.
* testsuite/gas/arm/mve-vddup.d: New test.
* testsuite/gas/arm/mve-vddup.s: New test.
* testsuite/gas/arm/mve-vdup.d: New test.
* testsuite/gas/arm/mve-vdup.s: New test.
* testsuite/gas/arm/mve-veor.d: New test.
* testsuite/gas/arm/mve-veor.s: New test.
* testsuite/gas/arm/mve-vfma-vfms.d: New test.
* testsuite/gas/arm/mve-vfma-vfms.s: New test.
* testsuite/gas/arm/mve-vfmas.d: New test.
* testsuite/gas/arm/mve-vfmas.s: New test.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.d: New test.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd.s: New test.
* testsuite/gas/arm/mve-vhcadd.d: New test.
* testsuite/gas/arm/mve-vhcadd.s: New test.
* testsuite/gas/arm/mve-vmax-vmin.d: New test.
* testsuite/gas/arm/mve-vmax-vmin.s: New test.
* testsuite/gas/arm/mve-vmaxa-vmina.d: New test.
* testsuite/gas/arm/mve-vmaxa-vmina.s: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm.d: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm.s: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma.s: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv.d: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv.s: New test.
* testsuite/gas/arm/mve-vmaxv-vminv.d: New test.
* testsuite/gas/arm/mve-vmaxv-vminv.s: New test.
* testsuite/gas/arm/mve-vmla.d: New test.
* testsuite/gas/arm/mve-vmla.s: New test.
* testsuite/gas/arm/mve-vmladav.d: New test.
* testsuite/gas/arm/mve-vmladav.s: New test.
* testsuite/gas/arm/mve-vmlaldav.d: New test.
* testsuite/gas/arm/mve-vmlaldav.s: New test.
* testsuite/gas/arm/mve-vmlalv.d: New test.
* testsuite/gas/arm/mve-vmlalv.s: New test.
* testsuite/gas/arm/mve-vmlas.d: New test.
* testsuite/gas/arm/mve-vmlas.s: New test.
* testsuite/gas/arm/mve-vmlav.d: New test.
* testsuite/gas/arm/mve-vmlav.s: New test.
* testsuite/gas/arm/mve-vmlsdav.d: New test.
* testsuite/gas/arm/mve-vmlsdav.s: New test.
* testsuite/gas/arm/mve-vmlsldav.d: New test.
* testsuite/gas/arm/mve-vmlsldav.s: New test.
* testsuite/gas/arm/mve-vmov-1.d: New test.
* testsuite/gas/arm/mve-vmov-1.s: New test.
* testsuite/gas/arm/mve-vmov-2.d: New test.
* testsuite/gas/arm/mve-vmov-2.s: New test.
* testsuite/gas/arm/mve-vmul.d: New test.
* testsuite/gas/arm/mve-vmul.s: New test.
* testsuite/gas/arm/mve-vmulh.d: New test.
* testsuite/gas/arm/mve-vmulh.s: New test.
* testsuite/gas/arm/mve-vmullbt.d: New test.
* testsuite/gas/arm/mve-vmullbt.s: New test.
* testsuite/gas/arm/mve-vmvn.d: New test.
* testsuite/gas/arm/mve-vmvn.s: New test.
* testsuite/gas/arm/mve-vorn.d: New test.
* testsuite/gas/arm/mve-vorn.s: New test.
* testsuite/gas/arm/mve-vorr.d: New test.
* testsuite/gas/arm/mve-vorr.s: New test.
* testsuite/gas/arm/mve-vpnot.d: New test.
* testsuite/gas/arm/mve-vpnot.s: New test.
* testsuite/gas/arm/mve-vpsel.d: New test.
* testsuite/gas/arm/mve-vpsel.s: New test.
* testsuite/gas/arm/mve-vpt.d: New test.
* testsuite/gas/arm/mve-vpt.s: New test.
* testsuite/gas/arm/mve-vqabsneg.s: New test.
* testsuite/gas/arm/mve-vqaddsub.d: New test.
* testsuite/gas/arm/mve-vqaddsub.s: New test.
* testsuite/gas/arm/mve-vqdmladh.d: New test.
* testsuite/gas/arm/mve-vqdmladh.s: New test.
* testsuite/gas/arm/mve-vqdmlah.d: New test.
* testsuite/gas/arm/mve-vqdmlah.s: New test.
* testsuite/gas/arm/mve-vqdmlash.d: New test.
* testsuite/gas/arm/mve-vqdmlash.s: New test.
* testsuite/gas/arm/mve-vqdmlsdh.d: New test.
* testsuite/gas/arm/mve-vqdmlsdh.s: New test.
* testsuite/gas/arm/mve-vqdmulh.d: New test.
* testsuite/gas/arm/mve-vqdmulh.s: New test.
* testsuite/gas/arm/mve-vqdmull.d: New test.
* testsuite/gas/arm/mve-vqdmull.s: New test.
* testsuite/gas/arm/mve-vqmovn.d: New test.
* testsuite/gas/arm/mve-vqmovn.s: New test.
* testsuite/gas/arm/mve-vqrshl.d: New test.
* testsuite/gas/arm/mve-vqrshl.s: New test.
* testsuite/gas/arm/mve-vqrshrn.d: New test.
* testsuite/gas/arm/mve-vqrshrn.s: New test.
* testsuite/gas/arm/mve-vqshl.d: New test.
* testsuite/gas/arm/mve-vqshl.s: New test.
* testsuite/gas/arm/mve-vrev.d: New test.
* testsuite/gas/arm/mve-vrev.s: New test.
* testsuite/gas/arm/mve-vrint.d: New test.
* testsuite/gas/arm/mve-vrint.s: New test.
* testsuite/gas/arm/mve-vrmlaldavh.d: New test.
* testsuite/gas/arm/mve-vrmlaldavh.s: New test.
* testsuite/gas/arm/mve-vrshl.d: New test.
* testsuite/gas/arm/mve-vrshl.s: New test.
* testsuite/gas/arm/mve-vsbc.d: New test.
* testsuite/gas/arm/mve-vsbc.s: New test.
* testsuite/gas/arm/mve-vshl.d: New test.
* testsuite/gas/arm/mve-vshl.s: New test.
* testsuite/gas/arm/mve-vshlc.d: New test.
* testsuite/gas/arm/mve-vshlc.s: New test.
* testsuite/gas/arm/mve-vshll.d: New test.
* testsuite/gas/arm/mve-vshll.s: New test.
* testsuite/gas/arm/mve-vshr.d: New test.
* testsuite/gas/arm/mve-vshr.s: New test.
* testsuite/gas/arm/mve-vshrn.d: New test.
* testsuite/gas/arm/mve-vshrn.s: New test.
* testsuite/gas/arm/mve-vsli.d: New test.
* testsuite/gas/arm/mve-vsli.s: New test.
* testsuite/gas/arm/mve-vsri.d: New test.
* testsuite/gas/arm/mve-vsri.s: New test.
* testsuite/gas/arm/mve-vstld.d: New test.
* testsuite/gas/arm/mve-vstld.s: New test.
* testsuite/gas/arm/mve-vstrldr-1.d: New test.
* testsuite/gas/arm/mve-vstrldr-1.s: New test.
* testsuite/gas/arm/mve-vstrldr-2.d: New test.
* testsuite/gas/arm/mve-vstrldr-2.s: New test.
* testsuite/gas/arm/mve-vstrldr-3.d: New test.
* testsuite/gas/arm/mve-vstrldr-3.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vshll): New encoding function.
(do_mve_vshlc): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vshlc-bad.d: New test.
* testsuite/gas/arm/mve-vshlc-bad.l: New test.
* testsuite/gas/arm/mve-vshlc-bad.s: New test.
* testsuite/gas/arm/mve-vshll-bad.d: New test.
* testsuite/gas/arm/mve-vshll-bad.l: New test.
* testsuite/gas/arm/mve-vshll-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vqmovnt, M_MNEM_vqmovnb,
M_MNEM_vqmovunt, M_MNEM_vqmovunb): New instruction encodings.
(do_mve_vqmovn): New encoding function.
(do_neon_rshl): Change to accepte MVE variants.
(insns): Change entries and add new for MVE mnemonics.
* testsuite/gas/arm/mve-vqmovn-bad.d: New test.
* testsuite/gas/arm/mve-vqmovn-bad.l: New test.
* testsuite/gas/arm/mve-vqmovn-bad.s: New test.
* testsuite/gas/arm/mve-vqrshl-bad.d: New test.
* testsuite/gas/arm/mve-vqrshl-bad.l: New test.
* testsuite/gas/arm/mve-vqrshl-bad.s: New test.
* testsuite/gas/arm/mve-vrshl-bad.d: New test.
* testsuite/gas/arm/mve-vrshl-bad.l: New test.
* testsuite/gas/arm/mve-vrshl-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(do_mve_vqdmull): New encoding function.
(insns): Add entry for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmull-bad.d: New test.
* testsuite/gas/arm/mve-vqdmull-bad.l: New test.
* testsuite/gas/arm/mve-vqdmull-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(mve_encode_qqr): Handle new instructions.
(do_neon_qdmulh): Add support for MVE variants.
(do_neon_qrdmlah): Likewise.
(do_mve_vqdmlah): New encoding function.
(insns): Change entries and add new entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmulh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmulh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmulh-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vqdmladh): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmladh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmladh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmladh-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vpsel): New encoding function.
(do_mve_vpnot): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vpnot-bad.d: New test.
* testsuite/gas/arm/mve-vpnot-bad.l: New test.
* testsuite/gas/arm/mve-vpnot-bad.s: New test.
* testsuite/gas/arm/mve-vpsel-bad.d: New test.
* testsuite/gas/arm/mve-vpsel-bad.l: New test.
* testsuite/gas/arm/mve-vpsel-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmlas): New encoding function.
(do_mve_vmulh): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vmlas-bad.d: New test.
* testsuite/gas/arm/mve-vmlas-bad.l: New test.
* testsuite/gas/arm/mve-vmlas-bad.s: New test.
* testsuite/gas/arm/mve-vmulh-bad.d: New test.
* testsuite/gas/arm/mve-vmulh-bad.l: New test.
* testsuite/gas/arm/mve-vmulh-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operand.
(parse_operands): Handle new operand.
(mve_encode_qqr): Handle new instructions.
(do_neon_dyadic_i64_su): Accept MVE variants.
(neon_dyadic_misc): Likewise.
(do_neon_mac_maybe_scalar): Likewise.
(do_neon_mul): Likewise.
(insns): Change to accept MVE variants.
* testsuite/gas/arm/mve-vmla-bad.d: New test.
* testsuite/gas/arm/mve-vmla-bad.l: New test.
* testsuite/gas/arm/mve-vmla-bad.s: New test.
* testsuite/gas/arm/mve-vmul-bad-1.d: New test.
* testsuite/gas/arm/mve-vmul-bad-1.l: New test.
* testsuite/gas/arm/mve-vmul-bad-1.s: New test.
* testsuite/gas/arm/mve-vmul-bad-2.d: New test.
* testsuite/gas/arm/mve-vmul-bad-2.l: New test.
* testsuite/gas/arm/mve-vmul-bad-2.s: New test.
* testsuite/gas/arm/mve-vqaddsub-bad.d: New test.
* testsuite/gas/arm/mve-vqaddsub-bad.l: New test.
* testsuite/gas/arm/mve-vqaddsub-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vmlaldav, M_MNEM_vmlaldava,
M_MNEM_vmlaldavx, M_MNEM_vmlaldavax, M_MNEM_vmlsldav,
M_MNEM_vmlsldava, M_MNEM_vmlsldavx, M_MNEM_vmlsldavax,
M_MNEM_vrmlaldavhx, M_MNEM_vrmlaldavhax, M_MNEM_vrmlsldavh,
M_MNEM_vrmlsldavha, M_MNEM_vrmlsldavhx, M_MNEM_vrmlsldavhax): New
instruction encodings.
(NEON_SHAPE_DEF): New shape
(mve_encode_rrqq): New encoding helper function.
(do_mve_vmlaldav): New encoding function.
(do_mve_vrmlaldavh): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vmlaldav-bad.d: New test.
* testsuite/gas/arm/mve-vmlaldav-bad.l: New test.
* testsuite/gas/arm/mve-vmlaldav-bad.s: New test.
* testsuite/gas/arm/mve-vmlalv-bad.d: New test.
* testsuite/gas/arm/mve-vmlalv-bad.l: New test.
* testsuite/gas/arm/mve-vmlalv-bad.s: New test.
* testsuite/gas/arm/mve-vmlsldav-bad.d: New test.
* testsuite/gas/arm/mve-vmlsldav-bad.l: New test.
* testsuite/gas/arm/mve-vmlsldav-bad.s: New test.
* testsuite/gas/arm/mve-vrmlaldavh-bad.d: New test.
* testsuite/gas/arm/mve-vrmlaldavh-bad.l: New test.
* testsuite/gas/arm/mve-vrmlaldavh-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vmaxv, M_MNEM_vmaxav, M_MNEM_vminv,
M_MNEM_vminav): New instruction encodings.
(do_mve_vmaxv): New encoding function.
(insns): Add entries for new MVE mnemonics.
* testsuite/gas/arm/mve-vmaxv-vminv-bad.d: New test.
* testsuite/gas/arm/mve-vmaxv-vminv-bad.l: New test.
* testsuite/gas/arm/mve-vmaxv-vminv-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmaxnmv): New encoding function.
(insns): Add entries for new mnemonics.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmaxa_vmina): New encoding function.
(do_mve_vmaxnma_vminnma): Likewise.
(do_neon_dyadic_if_su): Change to support MVE variants.
(do_vmaxnm): Likewise.
(insns): Change to accept MVE variants and add new.
* testsuite/gas/arm/mve-vmax-vmin-bad.d: New test.
* testsuite/gas/arm/mve-vmax-vmin-bad.l: New test.
* testsuite/gas/arm/mve-vmax-vmin-bad.s: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.d: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.l: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.s: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operand.
(parse_operands): Handle new operand.
(mve_encode_qqr): Change to support new instructions.
(enum vfp_or_neon_is_neon_bits): Moved.
(vfp_or_neon_is_neon): Moved.
(check_simd_pred_availability): Moved.
(do_neon_dyadic_i_su): Changed to support MVE variants.
(neon_dyadic_misc): Changed mve_encode_qqr call.
(do_mve_vbrsr): Likewise.
(do_mve_vhcadd): New encoding function.
(insns): Change existing to accept MVE variants and add new.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d: New test.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l: New test.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s: New test.
* testsuite/gas/arm/mve-vhcadd-bad.d: New test.
* testsuite/gas/arm/mve-vhcadd-bad.l: New test.
* testsuite/gas/arm/mve-vhcadd-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_fmac): Change to support MVE variants.
(insns): Change to accept MVE variants.
* testsuite/gas/arm/mve-vfma-vfms-bad.d: New test.
* testsuite/gas/arm/mve-vfma-vfms-bad.l: New test.
* testsuite/gas/arm/mve-vfma-vfms-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vddup, M_MNEM_vdwdup, M_MNEM_vidup,
M_MNEM_viwdup): New instruction encodings.
(NEON_SHAPE_DEF): New shapes.
(do_mve_viddup): New encoding function.
(do_neon_dup): Change to support new MVE variants.
(insns): Change existing to accept MVE variants and add new.
* testsuite/gas/arm/mve-vddup-bad.d: New test.
* testsuite/gas/arm/mve-vddup-bad.l: New test.
* testsuite/gas/arm/mve-vddup-bad.s: New test.
* testsuite/gas/arm/mve-vdup-bad.d: New test.
* testsuite/gas/arm/mve-vdup-bad.l: New test.
* testsuite/gas/arm/mve-vdup-bad.s: New test.
* testsuite/gas/arm/mve-vidup-bad.d: New test.
* testsuite/gas/arm/mve-vidup-bad.l: New test.
* testsuite/gas/arm/mve-vidup-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vfmas): New encoding function.
(do_neon_cls): Change to support MVE variants.
(do_neon_clz): Change to support MVE variants.
(insns): Change to support MVE variants and add new.
* testsuite/gas/arm/mve-vcls-bad.d: New test.
* testsuite/gas/arm/mve-vcls-bad.l: New test.
* testsuite/gas/arm/mve-vcls-bad.s: New test.
* testsuite/gas/arm/mve-vclz-bad.d: New test.
* testsuite/gas/arm/mve-vclz-bad.l: New test.
* testsuite/gas/arm/mve-vclz-bad.s: New test.
* testsuite/gas/arm/mve-vfmas-bad.d: New test.
* testsuite/gas/arm/mve-vfmas-bad.l: New test.
* testsuite/gas/arm/mve-vfmas-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operands.
(parse_operands): Handle new operands.
(do_mve_vcmul): New encoding function.
(do_vcmla): Change to support MVE variants.
(do_vcadd): Change to support MVE variants.
(insns): Change existing to support MVE variants and add new.
* testsuite/gas/arm/mve-vcadd-bad-1.d: New test.
* testsuite/gas/arm/mve-vcadd-bad-1.l: New test.
* testsuite/gas/arm/mve-vcadd-bad-1.s: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.d: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.l: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.s: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.s: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operands.
(parse_operands): Handle new operands.
(enum vfp_or_neon_is_neon_bits): Moved
(vfp_or_neon_is_neon): Moved
(check_simd_pred_availability): Moved.
(do_neon_logic): Change to accept MVE variants.
(insns): Changed to accept MVE variants.
* testsuite/gas/arm/mve-vand-bad.d: New test.
* testsuite/gas/arm/mve-vand-bad.l: New test.
* testsuite/gas/arm/mve-vand-bad.s: New test.
* testsuite/gas/arm/mve-vbic-bad.d: New test.
* testsuite/gas/arm/mve-vbic-bad.l: New test.
* testsuite/gas/arm/mve-vbic-bad.s: New test.
* testsuite/gas/arm/mve-veor-bad.d: New test.
* testsuite/gas/arm/mve-veor-bad.l: New test.
* testsuite/gas/arm/mve-veor-bad.s: New test.
* testsuite/gas/arm/mve-vorn-bad.d: New test.
* testsuite/gas/arm/mve-vorn-bad.l: New test.
* testsuite/gas/arm/mve-vorn-bad.s: New test.
* testsuite/gas/arm/mve-vorr-bad.d: New test.
* testsuite/gas/arm/mve-vorr-bad.l: New test.
* testsuite/gas/arm/mve-vorr-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vaddlv, M_MNEM_vaddlva, M_MNEM_vaddv,
M_MNEM_vaddva): New instruction encodings.
(mve_encode_rq): New encoding helper function.
(do_mve_vaddlv): New encoding function.
(do_mve_vaddv): New encoding function.
* testsuite/gas/arm/mve-vaddlv-bad.d: New test.
* testsuite/gas/arm/mve-vaddlv-bad.l: New test.
* testsuite/gas/arm/mve-vaddlv-bad.s: New test.
* testsuite/gas/arm/mve-vaddv-bad.d: New test.
* testsuite/gas/arm/mve-vaddv-bad.l: New test.
* testsuite/gas/arm/mve-vaddv-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr):
New instruction encodings.
(do_mve_vadc): New encoding instruction.
(do_mve_vbrsr): Likewise.
(do_mve_vsbc): Likewise.
* testsuite/gas/arm/mve-vadc-bad.d: New test.
* testsuite/gas/arm/mve-vadc-bad.l: New test.
* testsuite/gas/arm/mve-vadc-bad.s: New test.
* testsuite/gas/arm/mve-vbrsr-bad.d: New test.
* testsuite/gas/arm/mve-vbrsr-bad.l: New test.
* testsuite/gas/arm/mve-vbrsr-bad.s: New test.
* testsuite/gas/arm/mve-vsbc-bad.d: New test.
* testsuite/gas/arm/mve-vsbc-bad.l: New test.
* testsuite/gas/arm/mve-vsbc-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (MVE_BAD_QREG): New error message.
(enum operand_parse_code): Define new operand.
(parse_operands): Handle new operand.
(do_mve_vpt): Change for VPT blocks.
(NEON_SHAPE_DEF): New shape.
(neon_logbits): Moved.
(LOW4): Moved
(HI1): Moved
(mve_get_vcmp_vpt_cond): New function to translate vpt conditions.
(do_mve_vcmp): New encoding function.
(do_vfp_nsyn_cmp): Changed to support MVE variants.
(insns): Change to support MVE variants of vcmp and add vpt.
* testsuite/gas/arm/mve-vcmp-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmp-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmp-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmp-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmp-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmp-bad-2.s: New test.
* testsuite/gas/arm/mve-vpt-bad-1.d: New test.
* testsuite/gas/arm/mve-vpt-bad-1.l: New test.
* testsuite/gas/arm/mve-vpt-bad-1.s: New test.
* testsuite/gas/arm/mve-vpt-bad-2.d: New test.
* testsuite/gas/arm/mve-vpt-bad-2.l: New test.
* testsuite/gas/arm/mve-vpt-bad-2.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (struct arm_it): Expand isscalar field to be able to
distinguish between types of scalar.
(parse_typed_reg_or_scalar): Change to accept MVE scalar variants.
(parse_scalar): Likewise.
(parse_neon_mov): Accept MVE variant.
(po_scalar_or_goto): Make use reg_type.
(parse_operands): Change uses of po_scalar_or_goto.
(do_vfp_sp_monadic): Change to accept MVE variants.
(do_vfp_reg_from_sp): Likewise.
(do_vfp_sp_from_reg): Likewise.
(do_vfp_dp_rd_rm): Likewise.
(do_vfp_dp_rd_rn_rm): Likewise.
(do_vfp_dp_rm_rd_rn): Likewise.
(M_MNEM_vmovlt, M_MNEM_vmovlb, M_MNEM_vmovnt, M_MNEM_vmovnb): New
instruction encodings.
(NEON_SHAPE_DEF): New shape.
(do_mve_mov): New encoding fuction.
(do_mve_movn): Likewise.
(do_mve_movl): Likewise.
(do_neon_mov): Change to accept MVE variants.
(mcCE): New MACRO.
(insns): Accept new MVE variants and instructions.
* testsuite/gas/arm/mve-vmov-bad-1.d: New test.
* testsuite/gas/arm/mve-vmov-bad-1.l: New test.
* testsuite/gas/arm/mve-vmov-bad-1.s: New test.
* testsuite/gas/arm/mve-vmov-bad-2.d: New test.
* testsuite/gas/arm/mve-vmov-bad-2.l: New test.
* testsuite/gas/arm/mve-vmov-bad-2.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(do_neon_cvt_1): Handle MVE variants.
(do_neon_cvttb_1): Likewise.
(insns): Accept MVE variants.
* testsuite/gas/arm/mve-vcvt-bad-1.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-1.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-1.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.s: New test.
* testsuite/gas/arm/mve-vcvt-bad.d: New test.
* testsuite/gas/arm/mve-vcvt-bad.l: New test.
* testsuite/gas/arm/mve-vcvt-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (struct arm_it): Make immisreg field larger to hold
type of register.
(enum shift_kind): Add SHIFT_UXTW shift kind.
(enum parse_shift_mode): Add SHIFT_UXTW_IMMEDIATE shift mode.
(parse_shift): Handle new shift type.
(parse_address_main): Accept new addressing modes.
(M_MNEM_vstrb, M_MNEM_vstrh, M_MNEM_vstrw, M_MNEM_vstrd,
M_MNEM_vldrb, M_MNEM_vldrh, M_MNEM_vldrw, M_MNEM_vldrd): New
instruction encodings.
(do_mve_vstr_vldr_QI): New encoding functions.
(do_mve_vstr_vldr_RQ): Likewise.
(do_mve_vstr_vldr_RI): Likewise.
(do_mve_vstr_vldr): Likewise.
* testsuite/gas/arm/mve-vldr-bad-1.d: New test.
* testsuite/gas/arm/mve-vldr-bad-1.l: New test.
* testsuite/gas/arm/mve-vldr-bad-1.s: New test.
* testsuite/gas/arm/mve-vldr-bad-2.d: New test.
* testsuite/gas/arm/mve-vldr-bad-2.l: New test.
* testsuite/gas/arm/mve-vldr-bad-2.s: New test.
* testsuite/gas/arm/mve-vldr-bad-3.d: New test.
* testsuite/gas/arm/mve-vldr-bad-3.l: New test.
* testsuite/gas/arm/mve-vldr-bad-3.s: New test.
* testsuite/gas/arm/mve-vstr-bad-1.d: New test.
* testsuite/gas/arm/mve-vstr-bad-1.l: New test.
* testsuite/gas/arm/mve-vstr-bad-1.s: New test.
* testsuite/gas/arm/mve-vstr-bad-2.d: New test.
* testsuite/gas/arm/mve-vstr-bad-2.l: New test.
* testsuite/gas/arm/mve-vstr-bad-2.s: New test.
* testsuite/gas/arm/mve-vstr-bad-3.d: New test.
* testsuite/gas/arm/mve-vstr-bad-3.l: New test.
* testsuite/gas/arm/mve-vstr-bad-3.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (BAD_MVE_AUTO): New error message.
(BAD_MVE_SRCDEST): Likewise.
(mark_feature_used): Diagnose MVE only instructions when in
auto-detection mode or -march=all.
(enum operand_parse_code): Define new operand.
(parse_operands): Handle new operand.
(M_MNEM_vmullt, M_MNEM_vmullb): New encodings.
(mve_encode_qqq): New encoding helper function.
(do_mve_vmull): New encoding function.
(insns): Handle new instructions.
* testsuite/gas/arm/mve-vmullbt-bad.d: New test.
* testsuite/gas/arm/mve-vmullbt-bad.l: New test.
* testsuite/gas/arm/mve-vmullbt-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (struct asm_opcode): Make avalue a full int.
(BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors.
(enum operand_parse_code): Handle new operands.
(parse_operands): Likewise.
(M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx,
M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx,
M_MNEM_vmlsdavax): Define new encodings.
(NEON_SHAPE_DEF): Add new shape.
(neon_check_type): Use BAD_SIMD_TYPE.
(mve_encode_rqq): New encoding helper function.
(do_mve_vabav, do_mve_vmladav): New encoding functions.
(mCEF): New MACRO.
* testsuite/gas/arm/mve-vabav-bad.d: New test.
* testsuite/gas/arm/mve-vabav-bad.l: New test.
* testsuite/gas/arm/mve-vabav-bad.s: New test.
* testsuite/gas/arm/mve-vmladav-bad.d: New test.
* testsuite/gas/arm/mve-vmladav-bad.l: New test.
* testsuite/gas/arm/mve-vmladav-bad.s: New test.
* testsuite/gas/arm/mve-vmlav-bad.d: New test.
* testsuite/gas/arm/mve-vmlav-bad.l: New test.
* testsuite/gas/arm/mve-vmlav-bad.s: New test.
* testsuite/gas/arm/mve-vmlsdav-bad.d: New test.
* testsuite/gas/arm/mve-vmlsdav-bad.l: New test.
* testsuite/gas/arm/mve-vmlsdav-bad.s: New test.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant.
(insns): Change vabs and vneg entries to accept MVE variants.
* testsuite/gas/arm/mve-vabsneg-bad-1.d: New test.
* testsuite/gas/arm/mve-vabsneg-bad-1.l: New test.
* testsuite/gas/arm/mve-vabsneg-bad-1.s: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.d: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.l: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
bfd/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch.
binutils/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values.
(arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch.
elfcpp/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* arm.h (Tag_MVE_arch): Define new enum value.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (mve_ext, mve_fp_ext): New features.
(armv8_1m_main_ext_table): Add new extensions.
(aeabi_set_public_attributes): Translate new features to new build attributes.
(arm_convert_symbolic_attribute): Add Tag_MVE_arch.
* doc/c-arm.texi: Document new extensions and new build attribute.
include/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf/arm.h (Tag_MVE_arch): Define new enum value.
* opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
Add a new machine dependent option to set a prefix for register names.
gas/
* config/tc-s12z.c (register_prefix): New variable. (md_show_usage,
md_parse_option): parse the new option.
(lex_reg_name): Scan the prefix if one is set.
* doc/c-s12z.texi (S12Z-Opts): Document the new option.
* testsuite/gas/s12z/reg-prefix.d: New file.
* testsuite/gas/s12z/reg-prefix.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
This adds another test for file numbers given in .file directives,
checking that the value can be represented as an unsigned int and that
a memory allocation expression doesn't overflow. I removed a test
added recently since an earlier test (num < 1) already covers the
(num < 0) case.
* dwarf2dbg.c: Whitespace fixes.
(get_filenum): Don't strdup "file". Adjust error message.
(dwarf2_directive_filename): Use an unsigned type for "num".
Catch truncation of file number and overflow of get_filenum
XRESIZEVEC multiplication. Delete dead code.
git commit 3076e59490 caused
tic54x-coff +FAIL: c54x subsym assignment/use
PR 24538
* config/tc-tic54x.c (tic54x_start_line_hook): Do skip end of line
chars in setting endp.
PR 24538
gas * macro.c (get_any_string): Increase size of buffer used to hold
decimal value of expression result.
* dw2gencfi.c (get_debugseg_name): Handle an empty name.
* dwarf2dbg.c (get_filenum): Catch integer wraparound when
extending allocate file array.
(dwarf2_directive_filename): Add extra checks of the computed file
number.
* config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into
warning hash table.
(s_arm_eabi_attribute): Check for obj_elf_vendor_attribute
returning -1.
* config/tc-i386.c (i386_output_nops): Catch an attempt to
generate nops of negative lengths.
* as.h (MAX_LITTLENUMS): Move definition to here from...
* config/atof-ieee.c: ...here.
* config/tc-aarch64.c: ...here.
* config/tc-arc.c: ...here.
* config/tc-arm.c: ...here.
* config/tc-epiphany.c: ...here.
* config/tc-i386.c: ...here.
* config/tc-ia64.c: ...here. (And correct the value).
* config/tc-m32c.c: ...here.
* config/tc-m32r.c: ...here.
* config/tc-metag.c: ...here.
* config/tc-microblaze.c: ...here.
* config/tc-nds32.c: ...here.
* config/tc-or1k.c: ...here.
* config/tc-score.c: ...here.
* config/tc-score7.c: ...here.
* config/tc-tic4x.c: ...here.
* config/tc-tilegx.c: ...here.
* config/tc-tilepro.c: ...here.
* config/tc-visium.c: ...here.
* config/tc-sh.c (md_assemble): Add check for an instruction with
no opcodes.
* config/tc-mips.c (mips_lookup_insn): Add check for very short
instruction name.
* config/tc-tic54x.c: Use unsigned chars to access is_end_of_line
array.
(tic54x_start_line_hook): Check for an empty line.
(next_line_shows_parallel): Do not walk off the end of the string.
(tic54x_macro_start): Check for too much macro nesting.
(tic54x_start_label): Add label_start parameter. Use this
parameter to check the first character of the label.
* config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass
line_start variable to tic54x_start_label.
PR 24538
opcodes * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
end of the table prematurely.
Release 6 of the MIPS architecture does not have an ADDI instruction.
ADD/SUB instructions with immediate operands can be expanded to load
and immediate value and then perform the operation.
gas/
* config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>:
Add expansions for MIPS r6.
* testsuite/gas/mips/add.s: Enable tests for R6.
* testsuite/gas/mips/daddi.s: Annotate to test DADD for R6.
* testsuite/gas/mips/mipsr6@add.d: Likewise.
* gas/testsuite/gas/mips/mipsr6@dadd.d: New test.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
opcodes/
* mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
macros for R6.
opcodes/
* ppc-dis.c (skip_optional_operands): Change return type and returns.
(print_insn_powerpc) <skip_optional>: Change type.
Call skip_optional_operands if we have not skipped any operands.
gas/
* testsuite/gas/ppc/476.d: Update expected output.
* testsuite/gas/ppc/power6.d: Likewise.
My testcase matched against a file format of elf64-littleaarch64 in the
objdump output. This was unnecessarily restrictive and causes testcase
failures on aarch64_be.
Here we remove that restriction.
Committed as obvious.
Testing done on aarch64_be-none-elf gas to see the failure goes away.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/sve2.d: Remove file format restriction.
Add tests that SVE2 instructions are encoded as they should be, and
tests that invalid instructions have their problems reported.
Also check that each sve2 cryptographic extension is required to use the
corresponding cryptographic instructions.
Finally, test to ensure that sve2 instructions using mnemonics that
exist in sve1 still need the sve2 feature to be used.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: New test.
* testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test.
* testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.l: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.s: Test new instructions.
* testsuite/gas/aarch64/sve1-extended-sve2.s: New test.
* testsuite/gas/aarch64/sve2.d: Test new instructions.
* testsuite/gas/aarch64/sve2.s: Test new instructions.
New operand describes a shift-left immediate encoded in bits
22:20-19:18-16 where UInt(bits) - esize == shift.
This operand is useful for instructions like sshllb.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHLIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
operand.
This includes defining a new single bit field SVE_i2h at position 20.
SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded
in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm4_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
(fields): Handle SVE_i2h field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
Include a new iclass to extract the variant from the most significant 3
bits of this operand.
Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.
The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
operand.
(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-asm.c (aarch64_ins_sve_shrimm):
(aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass decode.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHRIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
operand.
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses
in a Zn register, offset by an Xm register.
This is used with scatter/gather SVE2 instructions.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
(parse_address_main): Account for new addressing mode [Zn.S, Xm].
(parse_operands): Handle new SVE_ADDR_ZX operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_ADDR_ZX.
(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
