evex-no-scale.s has ELF directive:
.section .probe, "", @progbits
and non-ELF targets may pad text sections.
* testsuite/gas/i386/i386.exp: Run evex-no-scale-32 and
evex-no-scale-64 only for ELF targets.
* testsuite/gas/i386/prefix32.s: Append ".p2align 4,0".
* testsuite/gas/i386/prefix64.s: Likewise.
* testsuite/gas/i386/prefix32.l: Updated.
* testsuite/gas/i386/prefix64.l: Likewise.
R_PPC64_REL24_NOTOC is used on calls like "bl foo@notoc" to tell the
linker that linkage stubs for PLT calls or long branches can't use r2
for pic addressing. Instead, new stubs that generate pc-relative
addresses are used. One complication is that pc-relative offsets to
the PLT may need to be 64-bit in large programs, in contrast to the
toc-relative addressing used by older PLT linkage stubs where a 32-bit
offset is sufficient until the PLT itself exceeds 2G in size.
.eh_frame info to cover the _notoc stubs is yet to be implemented.
bfd/
* elf64-ppc.c (ADDI_R12_R11, ADDI_R12_R12, LIS_R12),
(ADDIS_R12_R11, ORIS_R12_R12_0, ORI_R12_R12_0),
(SLDI_R12_R12_32, LDX_R12_R11_R12, ADD_R12_R11_R12): Define.
(ppc64_elf_howto_raw): Add R_PPC64_REL24_NOTOC entry.
(ppc64_elf_reloc_type_lookup): Support R_PPC64_REL24_NOTOC.
(ppc_stub_type): Add ppc_stub_long_branch_notoc,
ppc_stub_long_branch_both, ppc_stub_plt_branch_notoc,
ppc_stub_plt_branch_both, ppc_stub_plt_call_notoc, and
ppc_stub_plt_call_both.
(is_branch_reloc): Add R_PPC64_REL24_NOTOC.
(build_offset, size_offset): New functions.
(plt_stub_size): Support plt_call_notoc and plt_call_both.
(ppc_build_one_stub, ppc_size_one_stub): Support new stubs.
(toc_adjusting_stub_needed): Handle R_PPC64_REL24_NOTOC.
(ppc64_elf_size_stubs): Likewise, and new stubs.
(ppc64_elf_build_stubs, ppc64_elf_relocate_section): Likewise.
* reloc.c: Add BFD_RELOC_PPC64_REL24_NOTOC.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @notoc.
(ppc_force_relocation, ppc_fix_adjustable): Handle REL24_NOTOC.
ld/
* testsuite/ld-powerpc/ext.d,
* testsuite/ld-powerpc/ext.s,
* testsuite/ld-powerpc/ext.lnk,
* testsuite/ld-powerpc/notoc.d,
* testsuite/ld-powerpc/notoc.s: New tests.
* testsuite/ld-powerpc/powerpc.exp: Run them.
A small rework of the PRU GCC port exposed that CIE data alignment is
erroneously set to 4 for PRU in GAS. In fact PRU stack must be aligned to 1.
Set the macro to -1, to allow output from GCC to be assembled without errors.
Also, while at it, set DWARF2 HW register numbering to follow latest
* config/tc-pru.c (pru_regname_to_dw2regnum): Return the starting HW
byte-register number.
(pru_frame_initial_instructions): Use byte-numbering for FP index.
* config/tc-pru.h (DWARF2_DEFAULT_RETURN_COLUMN): Use number from
latest GCC.
(DWARF2_CIE_DATA_ALIGNMENT): Set to -1.
PR 14480
* config/tc-pdp11.c (parse_op_noreg): Check for and handle auto
increment deferred.
* testsuite/gas/pdp11/pr14480.d: New test driver file.
* testsuite/gas/pdp11/pr14480.s: New test source file file.
* testsuite/gas/pdp11/pdp11.exp: Run the new test.
* config/tc-ns32k.c (addr_mode): Replace "Drop through" comment
with "Fall through" so that it will be recognised by gcc's switch
statment error checker.
There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for
handling the not uncommon case of insns allowing either form of masking
with register operands, but only merging masking with a memory operand.
Instead of hitting the abort() in output_insn() (commented by "There
should be no other prefixes for instructions with VEX prefix"), report
a proper diagnostic instead, just like we do e.g. for invalid REP
prefixes.
In commit b5014f7af2 I've removed (instead of replaced) a conditional,
resulting in addressing forms not allowing 8-bit displacements to now
get their displacements scaled under certain circumstances. Re-add the
missing conditional.
This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc.
This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about.
bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY.
(BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise.
* Makefile.in: Regenerated.
* archures.c (enum bfd_architecture): Add bfd_arch_csky and
related bfd_mach defines.
(bfd_csky_arch): Declare.
(bfd_archures_list): Add C-SKY.
* bfd-in.h (elf32_csky_build_stubs): Declare.
(elf32_csky_size_stubs): Declare.
(elf32_csky_next_input_section: Declare.
(elf32_csky_setup_section_lists): Declare.
* bfd-in2.h: Regenerated.
* config.bfd: Add C-SKY.
* configure.ac: Likewise.
* configure: Regenerated.
* cpu-csky.c: New file.
* elf-bfd.h (enum elf_target_id): Add C-SKY.
* elf32-csky.c: New file.
* libbfd.h: Regenerated.
* reloc.c: Add C-SKY relocations.
* targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare.
(_bfd_target_vector): Add C-SKY target vector entries.
binutils* readelf.c: Include elf/csky.h.
(guess_is_rela): Handle EM_CSKY.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
include * dis-asm.h (csky_symbol_is_valid): Declare.
* opcode/csky.h: New file.
opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
* Makefile.in: Regenerated.
* configure.ac: Add C-SKY.
* configure: Regenerated.
* csky-dis.c: New file.
* csky-opc.h: New file.
* disassemble.c (ARCH_csky): Define.
(disassembler, disassemble_init_for_target): Add case for ARCH_csky.
* disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY.
(TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise.
* Makefile.in: Regenerated.
* config/tc-csky.c: New file.
* config/tc-csky.h: New file.
* config/te-csky_abiv1.h: New file.
* config/te-csky_abiv1_linux.h: New file.
* config/te-csky_abiv2.h: New file.
* config/te-csky_abiv2_linux.h: New file.
* configure.tgt: Add C-SKY.
* doc/Makefile.am (CPU_DOCS): Add entry for C-SKY.
* doc/Makefile.in: Regenerated.
* doc/all.texi: Set CSKY feature.
* doc/as.texi (Overview): Add C-SKY options.
(Machine Dependencies): Likewise.
* doc/c-csky.texi: New file.
* testsuite/gas/csky/*: New test cases.
ld * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations.
(ecskyelf.c, ecskyelf_linux.c): New rules.
* Makefile.in: Regenerated.
* configure.tgt: Add C-SKY.
* emulparams/cskyelf.sh: New file.
* emulparams/cskyelf_linux.sh: New file.
* emultempl/cskyelf.em: New file.
* gen-doc.texi: Add C-SKY.
* ld.texi: Likewise.
(Options specific to C-SKY targets): New section.
* testsuite/ld-csky/*: New tests.
* config/tc-hppa.c: Include "struc-symbol.h".
(pa_build_unwind_subspace): Use call_info->start_symbol->sy_frag
instead of frag_now for local symbol replacement.
For
movsd (%esi), %ss:(%edi), %ss:(%eax)
we got
[hjl@gnu-tools-1 tmp]$ as -o x.o x.s
x.s: Assembler messages:
x.s:1: Error: too many memory references for `movsd'
munmap_chunk(): invalid pointer
x.s:1: Internal error (Aborted).
Please report this bug.
[hjl@gnu-tools-1 tmp]$
struct _i386_insn has
const seg_entry *seg[2];
3 memory references will overflow the seg array. We should issue an
error if there are more than 2 memory references.
PR gas/23453
* config/tc-i386.c (parse_operands): Check for more than 2
memory references.
* testsuite/gas/i386/inval.s: Add a movsd test with 3 memory
references.
* testsuite/gas/i386/x86-64-inval.s: Likewise.
* testsuite/gas/i386/inval.l: Updated.
* testsuite/gas/i386/x86-64-inval.l: Likewise.
This is a relatively straightforward patch to improve support for the
IBM Gekko and IBM Broadway processors. Broadway is functionally
equivalent to the IBM 750CL, while Gekko's functionality is a subset
of theirs. The patch simplifies this reality and adds -mgekko and
-mbroadway as aliases for -m750cl. I didn't feel it was worth wasting
a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of
simplified mnemonics for special purpose register access. Notably,
Broadway adds 4 additional IBAT and DBAT registers but these are not
assigned sequential SPR numbers.
gas/
* config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway.
* doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* testsuite/gas/ppc/broadway.d,
* testsuite/gas/ppc/broadway.s: New test for broadway.
* testsuite/gas/ppc/ppc.exp: Run new test.
include/
* opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
opcodes/
* ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
(powerpc_init_dialect): Handle bfd_mach_ppc_750.
* ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
support disjointed BAT.
(powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
(XSPRGQR_MASK, GEKKO, BROADWAY): Define.
(powerpc_opcodes): Add 750cl extended mnemonics for spr access.
This adds support for ".localentry 1", a new st_other
STO_PPC64_LOCAL_MASK encoding that signifies a function with a single
entry point like ".localentry 0", but unlike a ".localentry 0"
function does not preserve r2.
include/
* elf/ppc64.h: Specify byte offset to local entry for values
of two to six in STO_PPC64_LOCAL_MASK. Clarify r2 return
value for such functions when entering via global entry point.
Specify meaning of a value of one in STO_PPC64_LOCAL_MASK.
bfd/
* elf64-ppc.c (ppc64_elf_size_stubs): Use a ppc_stub_long_branch_r2off
for calls to symbols with STO_PPC64_LOCAL_MASK bits set to 1.
gas/
* config/tc-ppc.c (ppc_elf_localentry): Allow .localentry values
of 1 and 7 to directly set value into STO_PPC64_LOCAL_MASK bits.
ld/testsuite/
* ld-powerpc/elfv2.s: Add .localentry f5,1 testcase.
* ld-powerpc/elfv2exe.d: Update.
* ld-powerpc/elfv2so.d: Update.
Expand Broadcast to 3 bits so that the number of bytes to broadcast
can be computed as 1 << (Broadcast - 1). Use it to simplify x86
assembler.
gas/
* config/tc-i386.c (Broadcast_Operation): Add bytes.
(build_evex_prefix): Use i.broadcast->bytes.
(match_broadcast_size): New function.
(check_VecOperands): Use the broadcast field to compute the
number of bytes to broadcast directly. Set i.broadcast->bytes.
Use match_broadcast_size.
opcodes/
* i386-gen.c (adjust_broadcast_modifier): New function.
(process_i386_opcode_modifier): Add an argument for operands.
Adjust the Broadcast value based on operands.
(output_i386_opcode): Pass operand_types to
process_i386_opcode_modifier.
(process_i386_opcodes): Pass NULL as operands to
process_i386_opcode_modifier.
* i386-opc.h (BYTE_BROADCAST): New.
(WORD_BROADCAST): Likewise.
(DWORD_BROADCAST): Likewise.
(QWORD_BROADCAST): Likewise.
(i386_opcode_modifier): Expand broadcast to 3 bits.
* i386-tbl.h: Regenerated.
Documentation for .arch and .cpu directives currently says that it
accepts the same name as -march/-mcpu command-line options respectively.
However it only accept the architecture/CPU part of those options: it
does not accept specifying an extension which is done via
.arch_extension. This patch clarifies that the extension is not
accepted.
2018-07-25 Thomas Preud'homme <thomas.preudhomme@linaro.org>
gas/
* doc/c-arm.texi (.arch directive): Clarify that name must not include
an extension.
(.cpu directive): Likewise.
Use unsigned int to iterate through multi-length vector operands to avoid
sign-extension.
* config/tc-i386.c (build_vex_prefix): Use unsigned int to
iterate through multi-length vector operands.
(build_evex_prefix): Likewise.
Just like for their AVX counterparts and CVTSI2S{D,S}, a memory source
here is ambiguous and hence
- in source files should be qualified with a suitable suffix or operand
size specifier (not doing so is an error in Intel mode, and will gain
a diagnostic in AT&T mode in the future),
- in disassembly should be properly suffixed (the Intel operand size
specifiers were emitted correctly already).
For
.intel_syntax noprefix
vcvtps2qq xmm0, DWORD PTR [rax]
we should get
Error: broadcast is needed for operand of such type for `vcvtps2qq'
* testsuite/gas/i386/inval-avx512f.s: Add a test for missing
broadcast.
* testsuite/gas/i386/x86-64-inval-avx512f.s: Likewise.
* testsuite/gas/i386/inval-avx512f.l: Updated.
* testsuite/gas/i386/x86-64-inval-avx512f.l: Likewise.
Remove broadcast_not_on_src_operand since it is unused.
* config/tc-i386.c (i386_error): Remove
broadcast_not_on_src_operand.
(match_template): Likewse.
In ARC assembler, we accept case insensitive mnemonics, but this was
not the case for extension instruction, fix it and add a test.
gas/
Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (tokenize_extinsn): Convert to lower case the
name of extension instructions.
* testsuite/gas/arc/textinsn_case.d: New file.
* testsuite/gas/arc/textinsn_case.s: Likewise.
Determine VEX/EVEXE vector length from the last multi-length vector
operand.
* config/tc-i386.c (build_vex_prefix): Determine vector
length from the last multi-length vector operand.
(build_evex_prefix): Likewise.
match_reg_size checks size for both memory and register operands. This
patch renamed match_reg_size to match_operand_size and updated comments
for
commit 3ac21baa84
Author: Jan Beulich <jbeulich@novell.com>
Date: Mon Jul 16 08:19:21 2018 +0200
x86: fix operand size checking
which added one argument to match_reg_size, match_simd_size and
match_mem_size.
* config/tc-i386.c (match_reg_size): Renamed to ...
(match_operand_size): This. Update comments.
(match_simd_size): Update comments. Replace match_reg_size
with match_operand_size.
(match_mem_size): Likewise.
(operand_size_match): Replace match_reg_size with
match_operand_size.
The MMI instruction set has been implemented in many Loongson
processors. There is a lot of software optimized for MMI. This patch
splits MMI from loongson2f/3a, and adds GAS and disassembler options for
MMI instructions.
2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
Maciej W. Rozycki <macro@mips.com>
bfd/
* elfxx-mips.c (print_mips_ases): Add MMI extension.
binutils/
* readelf.c (print_mips_ases): Add MMI extension.
gas/
* NEWS: Mention MultiMedia extensions Instructions (MMI)
support.
* config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and
OPTION_NO_LOONGSON_MMI.
(md_longopts): Likewise.
(mips_ases): Define availability for MMI.
(mips_convert_ase_flags): Map ASE_LOONGSON_MMI to
AFL_ASE_LOONGSON_MMI.
(mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a.
(md_show_usage): Add help for -mloongson-mmi and
-mno-loongson-mmi.
* doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi.
* doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi,
.set loongson-mmi and .set noloongson-mmi.
* testsuite/gas/mips/loongson-2f.d: Move mmi test to ...
* testsuite/gas/mips/loongson-2f-mmi.d: Here. Add ISA/ASE
flag verification.
* testsuite/gas/mips/loongson-2f.s: Move mmi test to ...
* testsuite/gas/mips/loongson-2f-mmi.s: Here.
* testsuite/gas/mips/loongson-3a.d: Move mmi test to ...
* testsuite/gas/mips/loongson-3a-mmi.d: Here. Add ISA/ASE
flag verification.
* testsuite/gas/mips/loongson-3a.s: Move mmi test to ...
* testsuite/gas/mips/loongson-3a-mmi.s: Here.
* testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and
loongson-3a-mmi tests.
include/
* elf/mips.h (AFL_ASE_MMI): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
* opcode/mips.h (ASE_LOONGSON_MMI): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
loongson3a descriptors.
(parse_mips_ase_option): Handle -M loongson-mmi option.
(print_mips_disassembler_options): Document -M loongson-mmi.
* mips-opc.c (LMMI): New macro.
(mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
instructions.
A couple of SPARC gas tests FAIL on Solaris/SPARC (both
sparc-sun-solaris2.11 and sparcv9-sun-solaris2.11):
FAIL: sparc PAUSE
FAIL: sparc CBCOND
FAIL: sparc CFR
FAIL: sparc CRYPTO
FAIL: sparc HPC+VIS3
FAIL: sparc IMA
FAIL: sparc OSA2015 %mwait asr and MWAIT instruction
FAIL: sparc OSA2015 %mcdper asr
FAIL: sparc SPARC5 and VIS4.0
FAIL: OSA2015 crypto instructions
FAIL: SPARC6
FAIL: FPCMPSHL OSA2017 instructions
FAIL: OSA2017 ONADD/ONSUB/ONMUL/ONDIV instructions.
FAIL: OSA2017 RLE instructions
FAIL: sparc64 rdasr
FAIL: sparc64 rdpr
FAIL: sparc64 rdhpr
FAIL: sparc64 wrasr
FAIL: sparc64 wrpr
It turns out there's a common pattern here: failures happen for all
tests that use SPARC ISA extensions beyond sparcv9, e.g. for the sparc
PAUSE test:
regexp_diff match failure
regexp "^ 0: b7 80 40 02 wr %g1, %g2, %pause$"
line " 0: b7 80 40 02 wr %g1, %g2, %asr27"
[...]
regexp_diff match failure
regexp "^ 8: b7 80 20 08 pause 8$"
line " 8: b7 80 20 08 wr 8, %asr27"
[...]
The fix is easy, actually: just as the tests specify the ISA extension
to use as a gas flag, the same needs to be done for objdump. For the
test above, which has -Av9v, this means passing -msparc:v9v to objdump.
Doing so makes all but two (unrelated; to be reported separately)
failures go away.
This doesn't happen on Linux/SPARC, where gas emits GNU object attributes
matching the hardcare capabilities used. Since gas doesn't yet implement
Solaris-style object capabilites, the explicit -march is needed, but only
passed on Solaris.
Tested on both sparc-sun-solaris2.11 and sparcv9-sun-solaris2.11.
* testsuite/gas/sparc/sparc.exp (set_tests_arch): New proc.
Prefix v9c, v9d, v9v, v9m, v9m8 tests with corresponding
set_tests_arch.
These are special because they may not have a register operand to derive
the vector length from, which requires to also deal with the braodcast
case when determining vector length in build_evex_prefix().
Also drop IgnoreSize (and the now redundant size specifiers) from their
suffixed counterparts.
After
commit 1b54b8d7e4
Author: Jan Beulich <jbeulich@novell.com>
Date: Mon Dec 18 09:36:14 2017 +0100
x86: fold RegXMM/RegYMM/RegZMM into RegSIMD
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible
to distinguish if Xmmword can represent a memory reference when operand
specification contains SIMD register. For example, template operands
specification like these
RegXMM|...|Xmmword|...
and
RegXMM|...
The Xmmword bitfield is always set by RegXMM which is represented by
"RegSIMD|Xmmword". This patch splits each of vcvtps2qq, vcvtps2uqq,
vcvttps2qq and vcvttps2uqq into 2 templates: one template only has
RegXMM source operand and the other only has mempry source operand.
gas/
PR gas/23418
* testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq,
vcvtps2uqq, vcvttps2qq and vcvttps2uqq.
* testsuite/gas/i386/xmmword.l: Updated.
opcodes/
PR gas/23418
* i386-opc.h (Byte): Update comments.
(Word): Likewise.
(Dword): Likewise.
(Fword): Likewise.
(Qword): Likewise.
(Tbyte): Likewise.
(Xmmword): Likewise.
(Ymmword): Likewise.
(Zmmword): Likewise.
* i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
vcvttps2uqq.
* i386-tbl.h: Regenerated.
Currently mov to/from control, debug, and test register insns accept any
size GPR operand (general pattern: templates with D set and both
operands being registers in distinct register files). This is due to
improper checking of the reverse case, including not informing the
caller whether a straight and/or reverse match was successful.
The helper functions need to be told two indexes: One to index the given
operand types array, and the other to index the template one. The caller
must attempt a further straight match only if the function reported a
straight match (and respectively for reverse matches).
* testsuite/gas/elf/missing-build-notes.s: New test. Checks that
relocs are correctly generated for missing build notes.
* testsuite/gas/elf/missing-build-notes.d: New file. Expected
output from objdump.
* testsuite/gas/elf/elf.exp: Run the new test.
* config/tc-arm.c (do_neon_mov): When converting an integer
immediate into a floating point value, check that the conversion
is valid. Also warn if the immediate is valid as both a floating
point value and a bit pattern.
* testsuite/gas/arm/vfp-mov-enc.s: Add instructions that use
floating point bit patterns.
* testsuite/gas/arm/vfp-mov-enc.d: Add regexps for the disassembly
of the new insns.
For more details see: https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf
opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entry for
ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas * testsuite/gas/aarch64/system.s: Add test for ssbb
and pssbb.
* testsuite/gas/aarch64/system.d: Update accordingly
and remove explicit addresses.
This adds the missing Em16 constraints the rest of the instructions requiring them
and also adds a testcase to test all the instructions so these are checked from
now on.
The Em16 operand constrains the valid registers to the lower 16 registers when used
with a half precision qualifier.
The list has been cross checked (by hand) through the Arm ARM version Ca.
opcodes/
PR binutils/23192
* aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
sqdmulh, sqrdmulh): Use Em16.
gas/
PR binutils/23192
* testsuite/gas/aarch64/illegal-by-element.s: New.
* testsuite/gas/aarch64/illegal-by-element.d: New.
* testsuite/gas/aarch64/illegal-by-element.l: New.
See:
https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/download-the-whitepaper
opcodes * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
csdb together with them.
(thumb32_opcodes): Likewise.
gas * config/tc-arm.c (insns): Add new ssbb and pssbb instructions.
* testsuite/gas/arm/csdb.s: Add new tests for ssbb and pssbb.
* testsuite/gas/arm/csdb.d: Likewise
* testsuite/gas/arm/thumb2_it_bad.s: Likewise.
* testsuite/gas/arm/thumb2_it_bad.l: Likewise.
* testsuite/gas/arm/barrier.d: Update with ssbb.
* testsuite/gas/arm/barrier-thumb.d: Likewise.
The checking against reg16_inoutportreg can be had with a simple test of
a bit, and the value setting from inoutportreg can be replaced by using
the actual register's reg_type field.
Note that the so far redundant 2nd instance of OPERAND_TYPE_INOUTPORTREG
is left in place, for its use in type_names[].
The check_prefix label was bogus from the beginning: The special
checking is supposed to happen for PadLock insns only; no
3-opcode-byte insn should go this path.
The previous constraints were based on information already in opcodes and it
seems that a few of them were wrong. I have now hand verified the ones changed
by the previous patch and corrected where needed.
This prevents a warning to be issued when one shouldn't be.
opcodes/
PR binutils/23369
* aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
gas/testsuite/
PR binutils/23369
* gas/aarch64/msr.d (csselr_el1,
vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1): New.
* gas/aarch64/msr.s: Likewise.
In the microMIPS mode also accept %half, %got, %call, %got_hi, %got_lo,
%call_hi, %call_lo, %neg, %got_page, %highest, %got_disp, %tlsgd,
%tlsldm, %dtprel_hi, %dtprel_lo, %gottprel, %tprel_hi and %tprel_lo
percent-ops with macros, so that they can be used with instructions that
expand into sequences if relocation is required due to their limited
offset span, such as LL, LWL, etc., fixing GAS assertions:
.../gas/testsuite/gas/mips/elf-rel28.s: Assembler messages:
.../gas/testsuite/gas/mips/elf-rel28.s:17: Internal error in macro_build at .../gas/config/tc-mips.c:8854.
Please report this bug.
observed if an attempt is made to assemble the `elf-rel28.s' test case
modified to use one of the affected instructions to microMIPS code.
gas/
* config/tc-mips.c (macro_build) <'i', 'j'>: Also accept
BFD_RELOC_16, BFD_RELOC_MIPS_GOT16, BFD_RELOC_MIPS_CALL16,
BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MIPS_GOT_LO16,
BFD_RELOC_MIPS_CALL_HI16, BFD_RELOC_MIPS_CALL_LO16,
BFD_RELOC_MIPS_SUB, BFD_RELOC_MIPS_GOT_PAGE,
BFD_RELOC_MIPS_HIGHEST, BFD_RELOC_MIPS_GOT_DISP,
BFD_RELOC_MIPS_TLS_GD, BFD_RELOC_MIPS_TLS_LDM,
BFD_RELOC_MIPS_TLS_DTPREL_HI16, BFD_RELOC_MIPS_TLS_DTPREL_LO16,
BFD_RELOC_MIPS_TLS_GOTTPREL, BFD_RELOC_MIPS_TLS_TPREL_HI16 and
BFD_RELOC_MIPS_TLS_TPREL_LO16 relocations if in the microMIPS
mode.
* testsuite/gas/mips/elf-rel28-lldscd-n32.d: New test.
* testsuite/gas/mips/elf-rel28-lldscd-micromips-n32.d: New test.
* testsuite/gas/mips/elf-rel28-lldscd-n64.d: New test.
* testsuite/gas/mips/elf-rel28-lldscd-micromips-n64.d: New test.
* testsuite/gas/mips/elf-rel28.s: Add instruction selection.
* testsuite/gas/mips/mips.exp: Run the new tests.
Complement commit df58fc944d ("MIPS: microMIPS ASE support"),
<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, and add TLS
and a few miscellaneous relocations to NewABI microMIPS support, fixing
GAS assertion failures:
.../gas/testsuite/gas/mips/elf-rel28.s: Assembler messages:
.../gas/testsuite/gas/mips/elf-rel28.s:19: Internal error in append_insn at .../gas/config/tc-mips.c:7660.
Please report this bug.
observed if an attempt is made to assemble the `elf-rel28.s' test case
to microMIPS code. The relocations are the same as with o32 support,
except for `partial_inplace' and `src_mask' updates for the respective
RELA variants.
bfd/
* elf64-mips.c (micromips_elf64_howto_table_rel): Add
R_MICROMIPS_HI0_LO16, R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM,
R_MICROMIPS_TLS_DTPREL_HI16, R_MICROMIPS_TLS_DTPREL_LO16,
R_MICROMIPS_TLS_GOTTPREL, R_MICROMIPS_TLS_TPREL_HI16,
R_MICROMIPS_TLS_TPREL_LO16, R_MICROMIPS_GPREL7_S2 and
R_MICROMIPS_PC23_S2 relocation entries.
(micromips_elf64_howto_table_rela): Likewise.
(micromips_reloc_map): Likewise.
* elfn32-mips.c (elf_micromips_howto_table_rel): Likewise.
(elf_micromips_howto_table_rela): Likewise.
(micromips_reloc_map): Likewise.
gas/
* testsuite/gas/mips/elf-rel28-micromips-n32.d: New test.
* testsuite/gas/mips/elf-rel28-micromips-n64.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
BFD's bfd_get_mach () function returns a bfd specific value representing
the architecture of the target which is populated from the Tag_CPU_arch
build attribute value of that target. Among other users of that
interfacem, objdump which uses it to print the architecture version of
the binary being examinated and to decide what instruction is available
if run with "-m arm" via its own mapping from bfd_mach_arm_X values to
feature bits available.
However, both BFD and objdump's most recent known architecture is
Armv5TE. When encountering a newer architecture bfd_get_mach will return
bfd_mach_arm_unknown. This is unfortunate since objdump uses that value
to allow all instructions on all architectures which is already what it
does by default, making the "-m arm" trick useless.
This patch updates BFD and objdump's knowledge of Arm architecture
versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and
Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A)
share the same Tag_CPU_arch build attribute value and
bfd_mach_arm values, the mapping from bfd machine value to feature bits
need to return the most featureful feature bits that would yield the
given bfd machine value otherwise some instruction would not disassemble
under "-m arm" mode. The patch rework that mapping to make this clearer
and simplify writing the mapping rules. In particular, for simplicity
all FPU instructions are allowed in all cases.
Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the
TAG_CPU_ARCH_X macros rather than hardcode their value.
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ,
bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M,
bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R,
bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define.
* bfd-in2.h: Regenerate.
* cpu-arm.c (arch_info_struct): Add entries for above new
bfd_mach_arm values.
* elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to
bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later
architectures. Force assert failure for any new Tag_CPU_arch value.
gas/
* config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros
rather than hardcode their values.
ld/
* arm-dis.c (select_arm_features): Fix typo in heading comment. Allow
all FPU features and add mapping from new bfd_mach_arm values to
allowed CPU feature bits.
opcodes/
* testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
expected result.
* testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
* testsuite/ld-arm/tls-longplt-lib.d: Likewise.
* testsuite/ld-arm/tls-longplt.d: Likewise.
Binutils documentation uses a mix of spelling for the compound word
"command-line X". According to [1]:
"Sometimes compound words are written separately (nail polish),
sometimes with a hyphen (short-sighted) and sometimes as one word
(eyelashes). Often new compounds are written as two separate words and,
as they become more familiar, they are either connected with a hyphen
(-) or made into one word."
I think command-line X is common enough in our industry that the two
workds command and line should be connected. Since command-line is more
common than commandline, I propose to update binutils documentation to
consistently use "command-line" when this is used as an adjective to a
noun (eg. command-line argument, command-line switch, command-line
option and command-line flag). I've left occurences of "the command
line" as is. I've also left gdb, sim and readline alone and have only
touched public documentation (texi and NEWS files).
[1]
http://dictionary.cambridge.org/grammar/british-grammar/word-formation/compounds
2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* doc/bfdint.texi: Use command-line consistently when used in a
compount word.
* doc/bfdsumm.texi: Likewise.
binutils/
* NEWS: Use command-line consistently when used in a compount word.
* doc/binutils.texi: Likewise and fix trailing whitespace on same
line.
gas/
* NEWS: Use command-line consistently when used in a compount word.
* doc/as.texi: Likewise.
* doc/c-aarch64.texi: Likewise.
* doc/c-alpha.texi: Likewise.
* doc/c-arc.texi: Likewise.
* doc/c-arm.texi: Likewise.
* doc/c-avr.texi: Likewise.
* doc/c-bfin.texi: Likewise.
* doc/c-cris.texi: Likewise.
* doc/c-epiphany.texi: Likewise.
* doc/c-i386.texi: Likewise.
* doc/c-ia64.texi: Likewise.
* doc/c-lm32.texi: Likewise.
* doc/c-m32r.texi: Likewise.
* doc/c-m68k.texi: Likewise.
* doc/c-mips.texi: Likewise.
* doc/c-mmix.texi: Likewise.
* doc/c-msp430.texi: Likewise.
* doc/c-mt.texi: Likewise.
* doc/c-nios2.texi: Likewise.
* doc/c-ppc.texi: Likewise.
* doc/c-pru.texi: Likewise.
* doc/c-rl78.texi: Likewise.
* doc/c-rx.texi: Likewise.
* doc/c-tic6x.texi: Likewise.
* doc/c-v850.texi: Likewise.
* doc/c-vax.texi: Likewise.
* doc/c-visium.texi: Likewise.
* doc/c-xstormy16.texi: Likewise.
* doc/c-xtensa.texi: Likewise.
* doc/c-z80.texi: Likewise.
* doc/c-z8k.texi: Likewise.
* doc/internals.texi: Likewise.
gprof/
* gprof.texi: Use command-line consistently when used in a compount
word.
ld/
* NEWS: Use command-line consistently when used in a compount word.
* ld.texinfo: Likewise.
* ldint.texinfo: Likewise.
A recent case in golang highlighted that gas wasn't warning on these
unpredictable cases in the architecture. Fixed thusly.
I need to audit gcc to make sure we have early clobbers on the
patterns but that's a separate patch.
Tested aarch64-none-elf and gas
Ok ?
Ramana
2018-06-29 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/tc-aarch64.c (warn_unpredictable_ldst): Add
unpredictable cases for ldxp, stlxrb, stlxrh, stlxr. *
testsuite/gas/aarch64/diagnostic.s: New tests. *
testsuite/gas/aarch64/diagnostic.l: Adjust.
Some instructions in Armv8-a place a limitation on FP16 registers that can be
used as the register from which to select an element from.
e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction
does not apply for all instructions, e.g. fcmla does not have this restriction
as it gets an extra bit from the M field.
Unfortunately, this restriction to S_H was added for all _Em operands before,
meaning for a large number of instructions you couldn't use the full register
file.
This fixes the issue by introducing a new operand _Em16 which applies this
restriction only when paired with S_H and leaves the _Em and the other
qualifiers for _Em16 unbounded (i.e. using the full 5 bit range).
Also the patch updates all instructions that should be affected by this.
opcodes/
PR binutils/23192
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
* aarch64-opc.c (operand_general_constraint_met_p,
aarch64_print_operand): Likewise.
* aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
fmlal2, fmlsl2.
(AARCH64_OPERANDS): Add Em2.
gas/
PR binutils/23192
* config/tc-aarch64.c (process_omitted_operand, parse_operands): Add
AARCH64_OPND_Em16
* testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper
16 registers.
* testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.s: Likewise.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
* testsuite/gas/aarch64/sve.d: Likewise.
include/
PR binutils/23192
*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
With the update to newer autotools, some gas object files are now
built in config/, breaking xtensa-elf and ia64-vms. This patch fixes
the dependencies.
* configure.ac: Specify extra_objects with leading "config/"
for xtensa-relax.o and te-vms.o. Use case statements to unique
extra_objects. Formatting.
* configure: Regenerate.
PR 23335
* config/tc-msp430.c (check_reg): Only accept register name
strings that do not end in an alphanumeric character.
* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
This patch fixes a disassembly issue with the aliases to subs with a shifted
register. The subs instruction with the zero register as destination is
supposed to alias to cmp and when the first input register is the zero register
the subs is supposed to be aliased to negs.
This means that a subs with destination and first input registers the zero
register is supposed to be a cmp.
This is done by raising the priority of the cmp alias.
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
gas/
* testsuite/gas/aarch64/addsub.s: Add negs to zero reg test.
* testsuite/gas/aarch64/addsub.d: Likewise.
Also make the automake strictness "foreign". My regeneration of the
three doc/Makefile.in files already had --foreign in the automake
invocation, so this just makes it explicit.
bfd/
* doc/Makefile.am (AUTOMAKE_OPTIONS): Add "foreign".
* doc/Makefile.in: Regenerate.
binutils/
* doc/Makefile.am (AUTOMAKE_OPTIONS): Add "foreign".
* doc/Makefile.in: Regenerate.
gas/
* doc/Makefile.am (AUTOMAKE_OPTIONS): Add "foreign".
* doc/Makefile.in: Regenerate.
zlib/
* Makefile.in: Regenerate.
For more information see the email thread starting here:
https://www.sourceware.org/ml/binutils/2018-05/msg00348.html
PR 21458
* tc-arm.c (do_adr): Only set the bottom bit of an imported thumb
function symbol address if -mthumb-interwork is active.
(do_adrl): Likewise.
* doc/c-arm.texi: Update descriptions of the -mthumb-interwork
option and the ADR and ADRL pseudo-ops.
* NEWS: Mention the new behaviour of the ADR and ADRL pseudo-ops.
* testsuite/gas/arm/pr21458.d: Add -mthumb-interwork option to
assembler command line.
* testsuite/gas/arm/adr.d: Likewise.
* testsuite/gas/arm/adrl.d: Likewise.
When trying to run the update-gnulib.sh script in gdb, I get this:
Error: Wrong automake version (Unescaped left brace in regex is deprecated, passed through in regex; marked by <-- HERE in m/\${ <-- HERE ([^ =:+{}]+)}/ at /opt/automake/1.11.1/bin/automake line 4113.), we need 1.11.1.
Aborting.
Apparently, it's an issue with a regex in automake that triggers a
warning starting with Perl 5.22. It has been fixed in automake 1.15.1.
So I think it's a good excuse to bump the versions of autoconf and
automake used in the gnulib import. And to avoid requiring multiple
builds of autoconf/automake, it was suggested that we bump the required
version of those tools for all binutils-gdb.
For autoconf, the 2.69 version is universally available, so it's an easy
choice. For automake, different distros and distro versions have
different automake versions. But 1.15.1 seems to be the most readily
available as a package. In any case, it's easy to build it from source.
I removed the version checks from AUTOMAKE_OPTIONS and AC_PREREQ,
because I don't think they are useful in our case. They only specify a
lower bound for the acceptable version of automake/autoconf. That's
useful if you let the user choose the version of the tool they want to
use, but want to set a minimum version (because you use a feature that
was introduced in that version). In our case, we force people to use a
specific version anyway. For the autoconf version, we have the check in
config/override.m4 that enforces the version we want. It will be one
less thing to update next time we change autotools version.
I hit a few categories of problems that required some changes. They are
described below along with the chosen solutions.
Problem 1:
configure.ac:17: warning: AM_INIT_AUTOMAKE: two- and three-arguments forms are deprecated. For more info, see:
configure.ac:17: http://www.gnu.org/software/automake/manual/automake.html#Modernize-AM_005fINIT_005fAUTOMAKE-invocation
Solution 1:
Adjust the code based on the example at that URL.
Problem 2 (in zlib/):
Makefile.am: error: required file './INSTALL' not found
Makefile.am: 'automake --add-missing' can install 'INSTALL'
Makefile.am: error: required file './NEWS' not found
Makefile.am: error: required file './AUTHORS' not found
Makefile.am: error: required file './COPYING' not found
Makefile.am: 'automake --add-missing' can install 'COPYING'
Solution 2:
Add the foreign option to AUTOMAKE_OPTIONS.
Problem 3:
doc/Makefile.am:20: error: support for Cygnus-style trees has been removed
Solution 3:
Remove the cygnus options.
Problem 4:
Makefile.am:656: warning: 'INCLUDES' is the old name for 'AM_CPPFLAGS' (or '*_CPPFLAGS')
Solution 4:
Rename "INCLUDES = " to "AM_CPPFLAGS += " (because AM_CPPFLAGS is
already defined earlier).
Problem 5:
doc/Makefile.am:71: warning: suffix '.texinfo' for Texinfo files is discouraged; use '.texi' instead
doc/Makefile.am: warning: Oops!
doc/Makefile.am: It appears this file (or files included by it) are triggering
doc/Makefile.am: an undocumented, soon-to-be-removed automake hack.
doc/Makefile.am: Future automake versions will no longer place in the builddir
doc/Makefile.am: (rather than in the srcdir) the generated '.info' files that
doc/Makefile.am: appear to be cleaned, by e.g. being listed in CLEANFILES or
doc/Makefile.am: DISTCLEANFILES.
doc/Makefile.am: If you want your '.info' files to be placed in the builddir
doc/Makefile.am: rather than in the srcdir, you have to use the shiny new
doc/Makefile.am: 'info-in-builddir' automake option.
Solution 5:
Rename .texinfo files to .texi.
Problem 6:
doc/Makefile.am: warning: Oops!
doc/Makefile.am: It appears this file (or files included by it) are triggering
doc/Makefile.am: an undocumented, soon-to-be-removed automake hack.
doc/Makefile.am: Future automake versions will no longer place in the builddir
doc/Makefile.am: (rather than in the srcdir) the generated '.info' files that
doc/Makefile.am: appear to be cleaned, by e.g. being listed in CLEANFILES or
doc/Makefile.am: DISTCLEANFILES.
doc/Makefile.am: If you want your '.info' files to be placed in the builddir
doc/Makefile.am: rather than in the srcdir, you have to use the shiny new
doc/Makefile.am: 'info-in-builddir' automake option.
Solution 6:
Remove the hack at the bottom of doc/Makefile.am and use
the info-in-builddir automake option.
Problem 7:
doc/Makefile.am:35: error: required file '../texinfo.tex' not found
doc/Makefile.am:35: 'automake --add-missing' can install 'texinfo.tex'
Solution 7:
Use the no-texinfo.tex automake option. We also have one in
texinfo/texinfo.tex, not sure if we should point to that, or move it
(or a newer version of it added with automake --add-missing) to
top-level.
Problem 8:
Makefile.am:131: warning: source file 'config/tc-aarch64.c' is in a subdirectory,
Makefile.am:131: but option 'subdir-objects' is disabled
automake: warning: possible forward-incompatibility.
automake: At least a source file is in a subdirectory, but the 'subdir-objects'
automake: automake option hasn't been enabled. For now, the corresponding output
automake: object file(s) will be placed in the top-level directory. However,
automake: this behaviour will change in future Automake versions: they will
automake: unconditionally cause object files to be placed in the same subdirectory
automake: of the corresponding sources.
automake: You are advised to start using 'subdir-objects' option throughout your
automake: project, to avoid future incompatibilities.
Solution 8:
Use subdir-objects, that means adjusting references to some .o that will now
be in config/.
Problem 9:
configure.ac:375: warning: AC_LANG_CONFTEST: no AC_LANG_SOURCE call detected in body
../../lib/autoconf/lang.m4:193: AC_LANG_CONFTEST is expanded from...
../../lib/autoconf/general.m4:2601: _AC_COMPILE_IFELSE is expanded from...
../../lib/autoconf/general.m4:2617: AC_COMPILE_IFELSE is expanded from...
../../lib/m4sugar/m4sh.m4:639: AS_IF is expanded from...
../../lib/autoconf/general.m4:2042: AC_CACHE_VAL is expanded from...
../../lib/autoconf/general.m4:2063: AC_CACHE_CHECK is expanded from...
configure.ac:375: the top level
Solution 9:
Use AC_LANG_SOURCE, or use proper quoting.
Problem 10 (in intl/):
configure.ac:7: warning: AC_COMPILE_IFELSE was called before AC_USE_SYSTEM_EXTENSIONS
/usr/share/aclocal/threadlib.m4:36: gl_THREADLIB_EARLY_BODY is expanded from...
/usr/share/aclocal/threadlib.m4:29: gl_THREADLIB_EARLY is expanded from...
/usr/share/aclocal/threadlib.m4:318: gl_THREADLIB is expanded from...
/usr/share/aclocal/lock.m4:9: gl_LOCK is expanded from...
/usr/share/aclocal/intl.m4:211: gt_INTL_SUBDIR_CORE is expanded from...
/usr/share/aclocal/intl.m4:25: AM_INTL_SUBDIR is expanded from...
/usr/share/aclocal/gettext.m4:57: AM_GNU_GETTEXT is expanded from...
configure.ac:7: the top level
Solution 10:
Add AC_USE_SYSTEM_EXTENSIONS in configure.ac.
ChangeLog:
* libtool.m4: Use AC_LANG_SOURCE.
* configure.ac: Remove AC_PREREQ, use AC_LANG_SOURCE.
* README-maintainer-mode: Update version requirements.
* ar-lib: New file.
* test-driver: New file.
* configure: Re-generate.
bfd/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
(INCLUDES): Rename to ...
(AM_CPPFLAGS): ... this.
* configure.ac: Remove AC_PREREQ.
* doc/Makefile.am (AUTOMAKE_OPTIONS): Remove 1.9, cygnus, add
info-in-builddir no-texinfo.tex.
(info_TEXINFOS): Rename bfd.texinfo to bfd.texi.
* doc/bfd.texinfo: Rename to ...
* doc/bfd.texi: ... this.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
binutils/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* doc/Makefile.am (AUTOMAKE_OPTIONS): Remove cygnus, add
info-in-builddir no-texinfo.tex.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
config/ChangeLog:
* override.m4 (_GCC_AUTOCONF_VERSION): Bump from 2.64 to 2.69.
etc/ChangeLog:
* configure.in: Remove AC_PREREQ.
* configure: Re-generate.
gas/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11, add subdir-objects.
(TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O): Add config/ prefix.
* configure.ac (TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O, emfiles,
extra_objects): Add config/ prefix.
* doc/as.texinfo: Rename to...
* doc/as.texi: ... this.
* doc/Makefile.am: Rename as.texinfo to as.texi throughout.
Remove DISTCLEANFILES hack.
(AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add no-texinfo.tex and
info-in-builddir.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
* doc/Makefile.in: Re-generate.
gdb/ChangeLog:
* common/common-defs.h (PACKAGE_NAME, PACKAGE_VERSION,
PACKAGE_STRING, PACKAGE_TARNAME): Undefine.
* configure.ac: Remove AC_PREREQ, add missing quoting.
* gnulib/configure.ac: Modernize usage of
AC_INIT/AM_INIT_AUTOMAKE. Remove AC_PREREQ.
* gnulib/update-gnulib.sh (AUTOCONF_VERSION): Bump to 2.69.
(AUTOMAKE_VERSION): Bump to 1.15.1.
* configure: Re-generate.
* config.in: Re-generate.
* aclocal.m4: Re-generate.
* gnulib/aclocal.m4: Re-generate.
* gnulib/config.in: Re-generate.
* gnulib/configure: Re-generate.
* gnulib/import/Makefile.in: Re-generate.
gdb/gdbserver/ChangeLog:
* configure.ac: Remove AC_PREREQ, add missing quoting.
* configure: Re-generate.
* config.in: Re-generate.
* aclocal.m4: Re-generate.
gdb/testsuite/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
gold/ChangeLog:
* configure.ac: Remove AC_PREREQ, add missing quoting and usage
of AC_LANG_SOURCE.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
* testsuite/Makefile.in: Re-generate.
gprof/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* Makefile.am: Remove DISTCLEANFILES hack.
(AUTOMAKE_OPTIONS): Remove 1.11, add info-in-builddir.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
* gconfig.in: Re-generate.
intl/ChangeLog:
* configure.ac: Add AC_USE_SYSTEM_EXTENSIONS, remove AC_PREREQ.
* configure: Re-generate.
* config.h.in: Re-generate.
* aclocal.m4: Re-generate.
ld/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* Makefile.am: Remove DISTCLEANFILES hack, rename ld.texinfo to
ld.texi, ldint.texinfo to ldint.texi throughout.
(AUTOMAKE_OPTIONS): Add info-in-builddir.
* README: Rename ld.texinfo to ld.texi, ldint.texinfo to
ldint.texi throughout.
* gen-doc.texi: Likewise.
* h8-doc.texi: Likewise.
* ld.texinfo: Rename to ...
* ld.texi: ... this.
* ldint.texinfo: Rename to ...
* ldint.texi: ... this.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* config.in: Re-generate.
* configure: Re-generate.
libdecnumber/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
* aclocal.m4.
libiberty/ChangeLog:
* configure.ac: Remove AC_PREREQ.
* configure: Re-generate.
* config.in: Re-generate.
opcodes/ChangeLog:
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
* configure.ac: Remove AC_PREREQ.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
readline/ChangeLog.gdb:
* configure: Re-generate.
* examples/rlfe/configure: Re-generate.
sim/ChangeLog:
* All configure.ac: Remove AC_PREREQ.
* All configure: Re-generate.
zlib/ChangeLog.bin-gdb:
* configure.ac: Modernize AC_INIT call, remove AC_PREREQ.
* Makefile.am (AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add
foreign.
* Makefile.in: Re-generate.
* aclocal.m4: Re-generate.
* configure: Re-generate.
Add support for the Global INValidate Application Specific Extension
for Release 6 of the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 187-191
bfd/
* elfxx-mips.c (print_mips_ases): Add GINV extension.
binutils/
* readelf.c (print_mips_ases): Add GINV extension.
gas/
* NEWS: Mention MIPS Global INValidate ASE support.
* config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV.
(md_longopts): Likewise.
(mips_ases): Define availability for GINV.
(mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV.
(md_show_usage): Add help for -mginv and -mno-ginv.
* doc/as.texinfo: Document -mginv, -mno-ginv.
* doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and
.set noginv.
* testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV
ASE.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Likewise.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ginv.d: New test.
* testsuite/gas/mips/ginv-err.d: New test.
* testsuite/gas/mips/ginv-err.l: New test stderr output.
* testsuite/gas/mips/ginv.s: New test source.
* testsuite/gas/mips/ginv-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
* opcode/mips.h: Document "+\" operand format.
(ASE_GINV): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
mips64r6 descriptors.
(parse_mips_ase_option): Handle -Mginv option.
(print_mips_disassembler_options): Document -Mginv.
* mips-opc.c (decode_mips_operand) <+\>: New operand format.
(GINV): New macro.
(mips_opcodes): Define ginvi and ginvt.
Add support for the CRC Application Specific Extension for Release 6 of
the MIPS Architecture.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 143-148
[2] "MIPS Architecture for Programmers Volume II-A: The MIPS64
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 165-170
ChangeLog:
bfd/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elfxx-mips.c (print_mips_ases): Add CRC.
binutils/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* readelf.c (print_mips_ases): Add CRC.
gas/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
Maciej W. Rozycki <macro@mips.com>
* config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC.
(md_longopts): Likewise.
(md_show_usage): Add help for -mcrc and -mno-crc.
(mips_ases): Define availability for CRC and CRC64.
(mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC.
* doc/as.texinfo: Document -mcrc, -mno-crc.
* doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and
.set no-crc.
* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC
ASE.
* testsuite/gas/mips/ase-errors-2.l: Likewise.
* testsuite/gas/mips/ase-errors-1.s: Likewise.
* testsuite/gas/mips/ase-errors-2.s: Likewise.
* testsuite/gas/mips/crc.d: New test.
* testsuite/gas/mips/crc64.d: New test.
* testsuite/gas/mips/crc-err.d: New test.
* testsuite/gas/mips/crc64-err.d: New test.
* testsuite/gas/mips/crc-err.l: New test stderr output.
* testsuite/gas/mips/crc64-err.l: New test stderr output.
* testsuite/gas/mips/crc.s: New test source.
* testsuite/gas/mips/crc64.s: New test source.
* testsuite/gas/mips/crc-err.s: New test source.
* testsuite/gas/mips/crc64-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
include/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* elf/mips.h (AFL_ASE_CRC): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
* opcode/mips.h (ASE_CRC): New macro.
* opcode/mips.h (ASE_CRC64): Likewise.
opcodes/
2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
Faraz Shahbazker <Faraz.Shahbazker@mips.com>
* mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
* mips-opc.c (CRC, CRC64): New macros.
(mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
crc32cd for CRC64.
Match commit 4ffff32f75 ("Match mips_optimize to the -O option
supplied") and adjust `--help' output for `-O0', `-O', `-O1' and `-O2'
options.
gas/
* config/tc-mips.c (md_show_usage): Correct help text for `-O0'
and `-O'. Mention `-O1'. Add `-O2' and its description.
This patch adds support to gas for -mcpu=cortex-a76 in the usual way.
make check-gas passes without problems.
2018-06-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-arm.c (arm_cpus): Add Cortex-A76 entry.
* doc/c-arm.texi (-mcpu): Document cortex-a76.
This patch adds support to gas for -mcpu=cortex-a76 in the usual way.
make check-gas passes without problems.
2018-06-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/tc-aarch64.c (aarch64_cpus): Add Cortex-A76 entry.
* doc/c-aarch64.texi (-mcpu): Document cortex-a76.
Detect illegal FMOV instructions that changes the size from 32 bits to 64
bits and vice versa. Add tests for these and other undefined FMOV
instructions.
PR 20319
gas * testsuite/gas/aarch64/illegal-3.s: Test if unallocated FMOV encodings
are detected as undefined.
* testsuite/gas/aarch64/illegal-3.d: Likewise.
* testsuite/gas/aarch64/illegal.s: Test if FMOV instructions that are
changing the size from 32 bits to 64 bits and vice versa trigger an
error.
* testsuite/gas/aarch64/illegal.l: Likewise.
opcodes * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
(aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
This patch fixes an uninitialized memory issue that can under certain
circumstances turn an error into a warning because non_fatal was not initialised
in all cases.
Verified using valgrind.
gas/config/tc-aarch64.c
PR binutils/21446
* tc-aarch64.c (record_operand_error, record_operand_error_with_data):
Initialize non_fatal.
It is currently not possible to correctly match .xt.prop information
for sections with identical VMA. Allow creation of separate property
sections in the BFD. Add assembler option --separate-prop-tables to
allow creation of separate property sections.
2018-06-04 Volodymyr Arbatov <arbatov@cadence.com>
bfd/
* elf32-xtensa.c (elf32xtensa_separate_props): New global
variable.
(xtensa_add_names): New function.
(xtensa_property_section_name): Add new parameter
separate_sections, use it to choose property section name.
(xtensa_get_separate_property_section): New function.
(xtensa_get_property_section): Invoke
xtensa_get_separate_property_section to get individual property
section if it exists, common property section otherwise.
(xtensa_make_property_section): Pass elf32xtensa_separate_props
to xtensa_property_section_name.
gas/
* config/tc-xtensa.c (elf32xtensa_separate_props): New
declaration.
(option_separate_props, option_no_separate_props): New
enumeration constants.
(md_longopts): Add separate-prop-tables option.
(md_parse_option): Add cases for option_separate_props and
option_no_separate_props.
(md_show_usage): Add help for [no-]separate-prop-tables options.
Bump version number to 2.30.52 since _bfd_link_hide_symbol has been added
to bfd_target.
bfd/
* version.m4: Bump version to 2.30.52
* configure: Regenerated.
binutils/
* configure: Regenerated.
gas/
* configure: Regenerated.
gprof/
* configure: Regenerated.
ld/
* configure: Regenerated.
opcodes/
* configure: Regenerated.
Fix locviews on ia64. If we do not drop the view after copying line
info to slots in the bundle, we may attempt to compute the view more
than once and get very confused.
for gas/ChangeLog
* dwarf2dbg.c (dwarf2_consume_line_info): Drop view.
All REX bits can be specified via individual prefixes. Redundancy should
only be reported on a per-bit basis.
Note that I originally had further checks added to the test case,
checking the effect also on PDEP. I had to strip those, because my patch
to correctly handle those
(https://sourceware.org/ml/binutils/2017-02/msg00280.html) was rejected.
I continue to think that there should not be any new prefix introduced
to handle the VEX case - whether the encoding of an insn requires VEX et
al should not be of immediate interest to the programmer.
... as is already done elsewhere: There's no need for the use of
operand_type_equal() here - the bit identifying control registers isn't
used for any other purposes.
The control register is never expressed by REX.B; this bit only affects
the involved GPR. Also only one of the operands can have its "control"
flag set, so only check the correct operand.
This patch regenerates a number of files that either were edited by
hand or not regenerated when s12z support was added to binutils.
bfd/
* Makefile.in: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
gas/
* po/POTFILES.in: Regenerate.
ld/
* po/BLD-POTFILES.in: Regenerate.
opcodes/
* Makefile.in: Regenerate.
* po/POTFILES.in: Regenerate.
bfd * Makefile.am: Add s12z files.
* Makefile.in: Regenerate.
* archures.c: Add bfd_s12z_arch.
* bfd-in.h: Add exports of bfd_putb24 and bfd_putl24.
* bfd-in2.h: Regenerate.
* config.bfd: Add s12z target.
* configure.ac: Add s12z target.
* configure: Regenerate.
* cpu-s12z.c: New file.
* elf32-s12z.c: New file.
* libbfd.c (bfd_putb24): New function.
(bfd_putl24): New function.
* libbfd.h: Regenerate.
* reloc.c: Add s12z relocations.
(bfd_get_reloc_size): Handle size 5 relocs.
* targets.c: Add s12z_elf32_vec.
opcodes * Makefile.am: Add support for s12z architecture.
* configure.ac: Likewise.
* disassemble.c: Likewise.
* disassemble.h: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* s12z-dis.c: New file.
* s12z.h: New file.
include * elf/s12z.h: New header.
ld * Makefile.am: Add support for s12z architecture.
* configure.tgt: Likewise.
* Makefile.in: Regenerate.
* emulparams/m9s12zelf.sh: New file.
* scripttempl/elfm9s12z.sc: New file.
* testsuite/ld-discard/static.d: Expect to fail for the s12z
target.
* testsuite/ld-elf/endsym.d: Likewise.
* testsuite/ld-elf/merge.d: Likewise.
* testsuite/ld-elf/pr14926.d: Skip for the s12z target.
* testsuite/ld-elf/sec64k.exp: Likewise.
* testsuite/ld-s12z: New directory.
* testsuite/ld-s12z/opr-linking.d: New file.
* testsuite/ld-s12z/opr-linking.s: New file.
* testsuite/ld-s12z/relative-linking.d: New file.
* testsuite/ld-s12z/relative-linking.s: New file.
* testsuite/ld-s12z/z12s.exp: New file.
gas * Makefile.am: Add support for s12z target.
* Makefile.in: Regenerate.
* NEWS: Mention the new support.
* config/tc-s12z.c: New file.
* config/tc-s12z.h: New file.
* configure.tgt: Add s12z support.
* doc/Makefile.am: Likewise.
* doc/Makefile.in: Regenerate.
* doc/all.texi: Add s12z documentation.
* doc/as.textinfo: Likewise.
* doc/c-s12z.texi: New file.
* testsuite/gas/s12z: New directory.
* testsuite/gas/s12z/abs.d: New file.
* testsuite/gas/s12z/abs.s: New file.
* testsuite/gas/s12z/adc-imm.d: New file.
* testsuite/gas/s12z/adc-imm.s: New file.
* testsuite/gas/s12z/adc-opr.d: New file.
* testsuite/gas/s12z/adc-opr.s: New file.
* testsuite/gas/s12z/add-imm.d: New file.
* testsuite/gas/s12z/add-imm.s: New file.
* testsuite/gas/s12z/add-opr.d: New file.
* testsuite/gas/s12z/add-opr.s: New file.
* testsuite/gas/s12z/and-imm.d: New file.
* testsuite/gas/s12z/and-imm.s: New file.
* testsuite/gas/s12z/and-opr.d: New file.
* testsuite/gas/s12z/and-opr.s: New file.
* testsuite/gas/s12z/and-or-cc.d: New file.
* testsuite/gas/s12z/and-or-cc.s: New file.
* testsuite/gas/s12z/bfext-special.d: New file.
* testsuite/gas/s12z/bfext-special.s: New file.
* testsuite/gas/s12z/bfext.d: New file.
* testsuite/gas/s12z/bfext.s: New file.
* testsuite/gas/s12z/bit-manip.d: New file.
* testsuite/gas/s12z/bit-manip.s: New file.
* testsuite/gas/s12z/bit.d: New file.
* testsuite/gas/s12z/bit.s: New file.
* testsuite/gas/s12z/bra-expression-defined.d: New file.
* testsuite/gas/s12z/bra-expression-defined.s: New file.
* testsuite/gas/s12z/bra-expression-undef.d: New file.
* testsuite/gas/s12z/bra-expression-undef.s: New file.
* testsuite/gas/s12z/bra.d: New file.
* testsuite/gas/s12z/bra.s: New file.
* testsuite/gas/s12z/brclr-symbols.d: New file.
* testsuite/gas/s12z/brclr-symbols.s: New file.
* testsuite/gas/s12z/brset-clr-opr-imm-rel.d: New file.
* testsuite/gas/s12z/brset-clr-opr-imm-rel.s: New file.
* testsuite/gas/s12z/brset-clr-opr-reg-rel.d: New file.
* testsuite/gas/s12z/brset-clr-opr-reg-rel.s: New file.
* testsuite/gas/s12z/brset-clr-reg-imm-rel.d: New file.
* testsuite/gas/s12z/brset-clr-reg-imm-rel.s: New file.
* testsuite/gas/s12z/brset-clr-reg-reg-rel.d: New file.
* testsuite/gas/s12z/brset-clr-reg-reg-rel.s: New file.
* testsuite/gas/s12z/clb.d: New file.
* testsuite/gas/s12z/clb.s: New file.
* testsuite/gas/s12z/clr-opr.d: New file.
* testsuite/gas/s12z/clr-opr.s: New file.
* testsuite/gas/s12z/clr.d: New file.
* testsuite/gas/s12z/clr.s: New file.
* testsuite/gas/s12z/cmp-imm.d: New file.
* testsuite/gas/s12z/cmp-imm.s: New file.
* testsuite/gas/s12z/cmp-opr-inc.d: New file.
* testsuite/gas/s12z/cmp-opr-inc.s: New file.
* testsuite/gas/s12z/cmp-opr-rdirect.d: New file.
* testsuite/gas/s12z/cmp-opr-rdirect.s: New file.
* testsuite/gas/s12z/cmp-opr-reg.d: New file.
* testsuite/gas/s12z/cmp-opr-reg.s: New file.
* testsuite/gas/s12z/cmp-opr-rindirect.d: New file.
* testsuite/gas/s12z/cmp-opr-rindirect.s: New file.
* testsuite/gas/s12z/cmp-opr-sxe4.d: New file.
* testsuite/gas/s12z/cmp-opr-sxe4.s: New file.
* testsuite/gas/s12z/cmp-opr-xys.d: New file.
* testsuite/gas/s12z/cmp-opr-xys.s: New file.
* testsuite/gas/s12z/cmp-s-imm.d: New file.
* testsuite/gas/s12z/cmp-s-imm.s: New file.
* testsuite/gas/s12z/cmp-s-opr.d: New file.
* testsuite/gas/s12z/cmp-s-opr.s: New file.
* testsuite/gas/s12z/cmp-xy.d: New file.
* testsuite/gas/s12z/cmp-xy.s: New file.
* testsuite/gas/s12z/com-opr.d: New file.
* testsuite/gas/s12z/com-opr.s: New file.
* testsuite/gas/s12z/complex-shifts.d: New file.
* testsuite/gas/s12z/complex-shifts.s: New file.
* testsuite/gas/s12z/db-tb-cc-opr.d: New file.
* testsuite/gas/s12z/db-tb-cc-opr.s: New file.
* testsuite/gas/s12z/db-tb-cc-reg.d: New file.
* testsuite/gas/s12z/db-tb-cc-reg.s: New file.
* testsuite/gas/s12z/dbCC.d: New file.
* testsuite/gas/s12z/dbCC.s: New file.
* testsuite/gas/s12z/dec-opr.d: New file.
* testsuite/gas/s12z/dec-opr.s: New file.
* testsuite/gas/s12z/dec.d: New file.
* testsuite/gas/s12z/dec.s: New file.
* testsuite/gas/s12z/div.d: New file.
* testsuite/gas/s12z/div.s: New file.
* testsuite/gas/s12z/eor.d: New file.
* testsuite/gas/s12z/eor.s: New file.
* testsuite/gas/s12z/exg.d: New file.
* testsuite/gas/s12z/exg.s: New file.
* testsuite/gas/s12z/ext24-ld-xy.d: New file.
* testsuite/gas/s12z/ext24-ld-xy.s: New file.
* testsuite/gas/s12z/inc-opr.d: New file.
* testsuite/gas/s12z/inc-opr.s: New file.
* testsuite/gas/s12z/inc.d: New file.
* testsuite/gas/s12z/inc.s: New file.
* testsuite/gas/s12z/inh.d: New file.
* testsuite/gas/s12z/inh.s: New file.
* testsuite/gas/s12z/jmp.d: New file.
* testsuite/gas/s12z/jmp.s: New file.
* testsuite/gas/s12z/jsr.d: New file.
* testsuite/gas/s12z/jsr.s: New file.
* testsuite/gas/s12z/ld-imm-page2.d: New file.
* testsuite/gas/s12z/ld-imm-page2.s: New file.
* testsuite/gas/s12z/ld-imm.d: New file.
* testsuite/gas/s12z/ld-imm.s: New file.
* testsuite/gas/s12z/ld-immu18.d: New file.
* testsuite/gas/s12z/ld-immu18.s: New file.
* testsuite/gas/s12z/ld-large-direct.d: New file.
* testsuite/gas/s12z/ld-large-direct.s: New file.
* testsuite/gas/s12z/ld-opr.d: New file.
* testsuite/gas/s12z/ld-opr.s: New file.
* testsuite/gas/s12z/ld-s-opr.d: New file.
* testsuite/gas/s12z/ld-s-opr.s: New file.
* testsuite/gas/s12z/ld-small-direct.d: New file.
* testsuite/gas/s12z/ld-small-direct.s: New file.
* testsuite/gas/s12z/lea-immu18.d: New file.
* testsuite/gas/s12z/lea-immu18.s: New file.
* testsuite/gas/s12z/lea.d: New file.
* testsuite/gas/s12z/lea.s: New file.
* testsuite/gas/s12z/mac.d: New file.
* testsuite/gas/s12z/mac.s: New file.
* testsuite/gas/s12z/min-max.d: New file.
* testsuite/gas/s12z/min-max.s: New file.
* testsuite/gas/s12z/mod.d: New file.
* testsuite/gas/s12z/mod.s: New file.
* testsuite/gas/s12z/mov.d: New file.
* testsuite/gas/s12z/mov.s: New file.
* testsuite/gas/s12z/mul-imm.d: New file.
* testsuite/gas/s12z/mul-imm.s: New file.
* testsuite/gas/s12z/mul-opr-opr.d: New file.
* testsuite/gas/s12z/mul-opr-opr.s: New file.
* testsuite/gas/s12z/mul-opr.d: New file.
* testsuite/gas/s12z/mul-opr.s: New file.
* testsuite/gas/s12z/mul-reg.d: New file.
* testsuite/gas/s12z/mul-reg.s: New file.
* testsuite/gas/s12z/mul.d: New file.
* testsuite/gas/s12z/mul.s: New file.
* testsuite/gas/s12z/neg-opr.d: New file.
* testsuite/gas/s12z/neg-opr.s: New file.
* testsuite/gas/s12z/not-so-simple-shifts.d: New file.
* testsuite/gas/s12z/not-so-simple-shifts.s: New file.
* testsuite/gas/s12z/opr-18u.d: New file.
* testsuite/gas/s12z/opr-18u.s: New file.
* testsuite/gas/s12z/opr-expr.d: New file.
* testsuite/gas/s12z/opr-expr.s: New file.
* testsuite/gas/s12z/opr-ext-18.d: New file.
* testsuite/gas/s12z/opr-ext-18.s: New file.
* testsuite/gas/s12z/opr-idx-24-reg.d: New file.
* testsuite/gas/s12z/opr-idx-24-reg.s: New file.
* testsuite/gas/s12z/opr-idx3-reg.d: New file.
* testsuite/gas/s12z/opr-idx3-reg.s: New file.
* testsuite/gas/s12z/opr-idx3-xysp-24.d: New file.
* testsuite/gas/s12z/opr-idx3-xysp-24.s: New file.
* testsuite/gas/s12z/opr-indirect-expr.d: New file.
* testsuite/gas/s12z/opr-indirect-expr.s: New file.
* testsuite/gas/s12z/opr-symbol.d: New file.
* testsuite/gas/s12z/opr-symbol.s: New file.
* testsuite/gas/s12z/or-imm.d: New file.
* testsuite/gas/s12z/or-imm.s: New file.
* testsuite/gas/s12z/or-opr.d: New file.
* testsuite/gas/s12z/or-opr.s: New file.
* testsuite/gas/s12z/p2-mul.d: New file.
* testsuite/gas/s12z/p2-mul.s: New file.
* testsuite/gas/s12z/page2-inh.d: New file.
* testsuite/gas/s12z/page2-inh.s: New file.
* testsuite/gas/s12z/psh-pul.d: New file.
* testsuite/gas/s12z/psh-pul.s: New file.
* testsuite/gas/s12z/qmul.d: New file.
* testsuite/gas/s12z/qmul.s: New file.
* testsuite/gas/s12z/rotate.d: New file.
* testsuite/gas/s12z/rotate.s: New file.
* testsuite/gas/s12z/s12z.exp: New file.
* testsuite/gas/s12z/sat.d: New file.
* testsuite/gas/s12z/sat.s: New file.
* testsuite/gas/s12z/sbc-imm.d: New file.
* testsuite/gas/s12z/sbc-imm.s: New file.
* testsuite/gas/s12z/sbc-opr.d: New file.
* testsuite/gas/s12z/sbc-opr.s: New file.
* testsuite/gas/s12z/shift.d: New file.
* testsuite/gas/s12z/shift.s: New file.
* testsuite/gas/s12z/simple-shift.d: New file.
* testsuite/gas/s12z/simple-shift.s: New file.
* testsuite/gas/s12z/single-ops.d: New file.
* testsuite/gas/s12z/single-ops.s: New file.
* testsuite/gas/s12z/specd6.d: New file.
* testsuite/gas/s12z/specd6.s: New file.
* testsuite/gas/s12z/st-large-direct.d: New file.
* testsuite/gas/s12z/st-large-direct.s: New file.
* testsuite/gas/s12z/st-opr.d: New file.
* testsuite/gas/s12z/st-opr.s: New file.
* testsuite/gas/s12z/st-s-opr.d: New file.
* testsuite/gas/s12z/st-s-opr.s: New file.
* testsuite/gas/s12z/st-small-direct.d: New file.
* testsuite/gas/s12z/st-small-direct.s: New file.
* testsuite/gas/s12z/st-xy.d: New file.
* testsuite/gas/s12z/st-xy.s: New file.
* testsuite/gas/s12z/sub-imm.d: New file.
* testsuite/gas/s12z/sub-imm.s: New file.
* testsuite/gas/s12z/sub-opr.d: New file.
* testsuite/gas/s12z/sub-opr.s: New file.
* testsuite/gas/s12z/tfr.d: New file.
* testsuite/gas/s12z/tfr.s: New file.
* testsuite/gas/s12z/trap.d: New file.
* testsuite/gas/s12z/trap.s: New file.
binutils* readelf.c: Add support for s12z architecture.
* testsuite/lib/binutils-common.exp (is_elf_format): Excluse s12z
targets.
Remove `-Wshadow' compilation errors:
cc1: warnings being treated as errors
.../gas/config/tc-nds32.c: In function 'md_assemble':
.../gas/config/tc-nds32.c:5212: error: declaration of 'expr' shadows a global declaration
.../gas/expr.h:180: error: shadowed declaration is here
make[4]: *** [tc-nds32.o] Error 1
which for versions of GCC before 4.8 prevent support for NDS32 targets
from being built. See also GCC PR c/53066.
gas/
* tc-nds32.c (md_assemble): Rename `expr' local variable to
`insn_expr'.
This patch adds constraints for read and write only system registers with the
msr and mrs instructions. The code will treat having both flags set and none
set as the same. These flags add constraints that must be matched up. e.g. a
system register with a READ only flag set, can only be used with mrs. If The
constraint fails a warning is emitted.
Examples of the warnings generated:
test.s: Assembler messages:
test.s:5: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
test.s:7: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
test.s:8: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'
and disassembly notes:
0000000000000000 <main>:
0: d5130503 msr dbgdtrtx_el0, x3
4: d5130503 msr dbgdtrtx_el0, x3
8: d5330503 mrs x3, dbgdtrrx_el0
c: d5330503 mrs x3, dbgdtrrx_el0
10: d5180003 msr midr_el1, x3 ; note: writing to a read-only register.
Note that because dbgdtrrx_el0 and dbgdtrtx_el0 have the same encoding, during
disassembly the constraints are use to disambiguate between the two. An exact
constraint match is always prefered over partial ones if available.
As always the warnings can be suppressed with -w and also be made errors using
warnings as errors.
binutils/
PR binutils/21446
* doc/binutils.texi (-M): Document AArch64 options.
gas/
PR binutils/21446
* testsuite/gas/aarch64/illegal-sysreg-2.s: Fix pmbidr_el1 test.
* testsuite/gas/aarch64/illegal-sysreg-2.l: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-2.d: Likewise.
* testsuite/gas/aarch64/sysreg-diagnostic.s: New.
* testsuite/gas/aarch64/sysreg-diagnostic.l: New.
* testsuite/gas/aarch64/sysreg-diagnostic.d: New.
include/
PR binutils/21446
* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
opcodes/
PR binutils/21446
* aarch64-asm.c (opintl.h): Include.
(aarch64_ins_sysreg): Enforce read/write constraints.
* aarch64-dis.c (aarch64_ext_sysreg): Likewise.
* aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
(F_REG_READ, F_REG_WRITE): New.
* aarch64-opc.c (aarch64_print_operand): Generate notes for
AARCH64_OPND_SYSREG.
(F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
(aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
* aarch64-tbl.h (aarch64_opcode_table): Add constraints to
msr (F_SYS_WRITE), mrs (F_SYS_READ).
This patch adds a new platform option "notes" that can be used to indicate if
disassembly notes should be placed in the disassembly as comments.
These notes can contain information about a failing constraint such as reading
from a write-only register. The disassembly will not be blocked because of this
but -M notes will emit a comment saying that the operation is not allowed.
For assembly this patch adds a new non-fatal status for errors. This is
essentially a warning. The reason for not creating an actual warning type is
that this causes the interaction between the ordering of warnings and errors to
be problematic. Currently the error buffer is almost always filled because of
the way operands are matched during assembly. An earlier template may have put
an error there that would only be displayed if no other template matches or
generates a higher priority error. But by definition a warning is lower
priority than a warning, so the error (which is incorrect if another template
matched) will supersede the warning. By treating warnings as errors and only
later relaxing the severity this relationship keeps working and the existing
reporting infrastructure can be re-used.
binutils/
PR binutils/21446
* doc/binutils.texi (-M): Document AArch64 options.
* NEWS: Document notes and warnings.
gas/
PR binutils/21446
* config/tc-aarch64.c (print_operands): Indicate no notes.
(output_operand_error_record): Support non-fatal errors.
(output_operand_error_report, warn_unpredictable_ldst, md_assemble):
Likewise.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_operand_error): Add non_fatal.
(aarch64_print_operand): Support notes.
opcodes/
PR binutils/21446
* aarch64-dis.c (no_notes: New.
(parse_aarch64_dis_option): Support notes.
(aarch64_decode_insn, print_operands): Likewise.
(print_aarch64_disassembler_options): Document notes.
* aarch64-opc.c (aarch64_print_operand): Support notes.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
