On aarch64-linux, with gcc 7.5.0, we run into:
...
(gdb) frame^M
#0 callee.increment (val=99.0, val@entry=9.18340949e-41, msg=...) at \
callee.adb:21^M
21 if Val > 200.0 then^M
(gdb) FAIL: gdb.ada/O2_float_param.exp: scenario=all: frame
...
The problem is a GCC bug, filed as "PR98148 - [AArch64] Wrong location
expression for function entry values" (
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98148 ).
Xfail the test for aarch64 and gcc 7.
Tested on x86_64-linux and aarch64-linux.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29418
On aarch64-linux, I run into:
...
Breakpoint 2, pck.inspect (obj=0x430eb0 \
<system.pool_global.global_pool_object>, <objL>=0) at pck.adb:17^M
17 procedure Inspect (Obj: access Top_T'Class) is^M
(gdb) FAIL: gdb.ada/access_tagged_param.exp: continue
...
while on x86_64-linux, I see:
...
Breakpoint 2, pck.inspect (obj=0x62b2a0, <objL>=2) at pck.adb:19^M
19 null;^M
(gdb) PASS: gdb.ada/access_tagged_param.exp: continue
...
Note the different line numbers, 17 vs 19.
The difference comes from the gdbarch_skip_prologue implementation.
The amd64_skip_prologue implementation doesn't use gcc line numbers, and falls
back to the architecture-specific prologue analyzer, which correctly skips
past the prologue, to address 0x4022f7:
...
00000000004022ec <pck__inspect>:
4022ec: 55 push %rbp
4022ed: 48 89 e5 mov %rsp,%rbp
4022f0: 48 89 7d f8 mov %rdi,-0x8(%rbp)
4022f4: 89 75 f4 mov %esi,-0xc(%rbp)
4022f7: 90 nop
4022f8: 90 nop
4022f9: 5d pop %rbp
4022fa: c3 ret
...
The aarch64_skip_prologue implementation does use gcc line numbers, which are:
...
File name Line number Starting address View Stmt
pck.adb 17 0x402580 x
pck.adb 17 0x402580 1 x
pck.adb 19 0x40258c x
pck.adb 20 0x402590 x
...
and which are represented like this internally in gdb:
...
INDEX LINE ADDRESS IS-STMT PROLOGUE-END
0 17 0x0000000000402580 Y
1 17 0x0000000000402580 Y
2 19 0x000000000040258c Y
3 20 0x0000000000402590 Y
4 END 0x00000000004025a0 Y
...
The second entry is interpreted as end-of-prologue, so 0x402580 is used, while
the actual end of the prologue is at 0x40258c:
...
0000000000402580 <pck__inspect>:
402580: d10043ff sub sp, sp, #0x10
402584: f90007e0 str x0, [sp, #8]
402588: b90007e1 str w1, [sp, #4]
40258c: d503201f nop
402590: d503201f nop
402594: 910043ff add sp, sp, #0x10
402598: d65f03c0 ret
40259c: d503201f nop
...
Note that the architecture-specific prologue analyzer would have gotten this
right:
...
(gdb) p /x aarch64_analyze_prologue (gdbarch, pc, pc + 128, 0)
$2 = 0x40258c
...
Fix the FAIL by making the test-case more robust against problems in prologue
skipping, by setting the breakpoint on line 19 instead.
Likewise in a few similar test-cases.
Tested on x86_64-linux and aarch64-linux.
v2:
- Add 32-bit Arm instruction selftest
- Refactored abstract memory reader into abstract instruction reader
- Adjusted code to use templated type and to use host endianness as
opposed to target endianness.
The arm record tests handle 16-bit and 32-bit thumb instructions, but the
code is laid out in a way that handles the 32-bit thumb instructions as
two 16-bit parts.
This is fine, but it is prone to host-endianness issues given how the two
16-bit parts are stored and how they are accessed later on. Arm is
little-endian by default, so running this test with a GDB built with
--enable-targets=all and on a big endian host will run into the following:
Running selftest arm-record.
Process record and replay target doesn't support syscall number -2036195
Process record does not support instruction 0x7f70ee1d at address 0x0.
Self test failed: self-test failed at ../../binutils-gdb/gdb/arm-tdep.c:14482
It turns out the abstract memory reader class is more generic than it needs to
be, and we can simplify the code a bit by assuming we have a simple instruction
reader that only reads up to 4 bytes, which is the length of a 32-bit
instruction.
Instead of returning a bool, we return instead the instruction that has been
read. This way we avoid having to deal with the endianness conversion, and use
the host endianness instead. The Arm selftests can be executed on non-Arm
hosts.
While at it, Tom suggested adding a 32-bit Arm instruction selftest to increase
the coverage of the selftests.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29432
Co-authored-by: Tom de Vries <tdevries@suse.de>
On openSUSE Tumbleweed (using glibc 2.36), I run into:
...
(gdb) print /d (int) munmap (4198400, 4096)^M
Invalid cast.^M
(gdb) FAIL: gdb.base/break-main-file-remove-fail.exp: cmdline: \
get integer valueof "(int) munmap (4198400, 4096)"
...
The problem is that after starting the executable, the symbol has type
"void (*) (void)":
...
(gdb) p munmap
$1 = {<text variable, no debug info>} 0x401030 <munmap@plt>
(gdb) start
...
(gdb) p munmap
$2 = {void (void)} 0x7ffff7feb9a0 <__GI_munmap>
...
which causes the "Invalid cast" error.
Looking at the debug info for glibc for symbol __GI_munmap:
...
<0><189683>: Abbrev Number: 1 (DW_TAG_compile_unit)
<189691> DW_AT_name : ../sysdeps/unix/syscall-template.S
<189699> DW_AT_producer : GNU AS 2.39.0
<1><1896ae>: Abbrev Number: 2 (DW_TAG_subprogram)
<1896af> DW_AT_name : __GI___munmap
<1896b3> DW_AT_external : 1
<1896b4> DW_AT_low_pc : 0x10cad0
<1896bc> DW_AT_high_pc : 37
...
that's probably caused by this bit (or similar bits for other munmap aliases).
This is fixed in gas on trunk by commit 5578fbf672 ("GAS: Add a return type
tag to DWARF DIEs generated for function symbols").
Work around this (for say gas 2.39) by explicitly specifying the prototype for
munmap.
Likewise for getpid in a couple of other test-cases.
Tested on x86_64-linux.
Currently objdump -S is not able to make use files downloaded from debuginfod.
This is due to bfd_find_nearest_line_discriminator being unable to locate any
separate debuginfo files in the debuginfod cache. Additionally objdump lacked
a call to debuginfod_find_source in order to download missing source files.
Fix this by using bfd_find_nearest_line_with_alt instead of
bfd_find_nearest_line_discriminator. Also add a call to
debuginfod_find_source in order to download missing source files.
Co-authored-by: Nick Clifton <nickc@redhat.com>
bfd_find_nearest_line_with_alt functions like bfd_find_nearest_line with
the addition of a parameter for specifying the filename of a supplementary
debug file such as one referenced by .gnu_debugaltlink or .debug_sup.
This patch focuses on implementing bfd_find_nearest_line_with_alt
support for ELF/DWARF2 .gnu_debugaltlink. For other targets this
function simply sets the invalid_operation bfd_error.
This is paired with "opcodes: Add non-enum disassembler options".
There is a portable mechanism for disassembler options and used on some
architectures:
- ARC
- Arm
- MIPS
- PowerPC
- RISC-V
- S/390
However, it only supports following forms:
- [NAME]
- [NAME]=[ENUM_VALUE]
Valid values for [ENUM_VALUE] must be predefined in
disasm_option_arg_t.values. For instance, for -M cpu=[CPU] in ARC
architecture, opcodes/arc-dis.c builds valid CPU model list from
include/elf/arc-cpu.def.
In this commit, it adds following format:
- [NAME]=[ARBITRARY_VALUE] (cannot contain "," though)
This is identified by NULL value of disasm_option_arg_t.values
(normally, this is a non-NULL pointer to a NULL-terminated list).
gdb/ChangeLog:
* gdb/disasm.c (set_disassembler_options): Add support for
non-enum disassembler options.
(show_disassembler_options_sfunc): Likewise.
When running test-case gdb.cp/cpexprs-debug-types.exp on target board
cc-with-debug-names/gdb:debug_flags=-gdwarf-5, we get an executable with
a .debug_names section, but no .debug_types section. For dwarf-5, the TUs
are no longer put in a separate unit, but instead they're put in the
.debug_info section.
When loading the executable, the .debug_names section is silently ignored
because of this check in dwarf2_read_debug_names:
...
if (map->tu_count != 0)
{
/* We can only handle a single .debug_types when we have an
index. */
if (per_bfd->types.size () != 1)
return false;
...
which triggers because per_bfd->types.size () == 0.
The intention of the check is to make sure we don't have more that one
.debug_types section, as can happen in a object file (see PR12984):
...
$ grep "\.debug_types" 11.s
.section .debug_types,"G",@progbits,wt.75c042c23a9a07ee,comdat
.section .debug_types,"G",@progbits,wt.c59c413bf50a4607,comdat
...
Fix this by:
- changing the check condition to "per_bfd->types.size () > 1", and
- handling per_bfd->types.size () == 0.
Tested on x86_64-linux.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29385
Add test-case gdb.dwarf2/debug-names-bad-cu-index.exp, a regression test for
commit 2fe9a3c41f ("[gdb/symtab] Fix bad compile unit index complaint").
Tested on x86_64-linux.
Add a test-case gdb.dwarf2/debug-names-tu.exp, that uses the dwarf assembler
to specify a .debug_names index with the TU list referring to a TU from the
.debug_types section.
This is intended to produce something similar to:
...
$ gcc -g -fdebug-types-section ~/hello.c -gdwarf-4
$ gdb-add-index -dwarf-5 a.out
...
Tested on x86_64-linux.
This is paired with "gdb: Add non-enum disassembler options".
There is a portable mechanism for disassembler options and used on some
architectures:
- ARC
- Arm
- MIPS
- PowerPC
- RISC-V
- S/390
However, it only supports following forms:
- [NAME]
- [NAME]=[ENUM_VALUE]
Valid values for [ENUM_VALUE] must be predefined in
disasm_option_arg_t.values. For instance, for -M cpu=[CPU] in ARC
architecture, opcodes/arc-dis.c builds valid CPU model list from
include/elf/arc-cpu.def.
In this commit, it adds following format:
- [NAME]=[ARBITRARY_VALUE] (cannot contain "," though)
This is identified by NULL value of disasm_option_arg_t.values
(normally, this is a non-NULL pointer to a NULL-terminated list).
include/ChangeLog:
* dis-asm.h (disasm_option_arg_t): Update comment of values
to allow non-enum disassembler options.
opcodes/ChangeLog:
* riscv-dis.c (print_riscv_disassembler_options): Support
non-enum disassembler options on printing disassembler help.
* arc-dis.c (print_arc_disassembler_options): Likewise.
* mips-dis.c (print_mips_disassembler_options): Likewise.
This commit removes SBREAK-related references on the simulator as it's
renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1).
sim/ChangeLog:
* riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak".
In commit:
commit 7b01c1cc1d
Date: Mon Apr 4 22:38:04 2022 +0100
sim: fixes for libopcodes styled disassembler
changes were made to the simulator source to handle the new libopcodes
disassembler styling API.
Unfortunately, these changes broke building GDB with the erc32 (sparc)
simulator, like this:
../src/configure --target=sparc-linux
make all-gdb
....
/usr/bin/ld: ../sim/erc32/libsim.a(interf.o): in function `sim_open':
/tmp/build/sim/../../src/sim/erc32/interf.c:247: undefined reference to `fprintf_styled'
collect2: error: ld returned 1 exit status
The problem is that in commit 7b01c1cc1d the fprintf_styled function
was added into sis.c. This file is only used when building the 'run'
binary, that is, the standalone simulator, and is not included in the
libsim.a library.
Now, the obvious fix would be to move fprintf_styled into libsim.a,
however, that turns out to be tricky.
The erc32 simulator currently has two copies of the function run_sim,
one in sis.c, and one in interf.c, both of these copies are global.
Currently, the 'run' binary links fine, though I suspect this might be
pure luck. When I tried moving fprintf_styled into interf.c, I ran
into multiple-definition (of run_sim) errors. I suspect that by
requiring the linker to pull in fprintf_styled from libsim.a I was
changing the order in which symbols were loaded, and the linker was
now seeing both copies of run_sim, while currently we only see one
copy.
The ideal solution of course, would be to merge the two similar, but
slightly different copies of run_sim, and just use the one copy. Then
we could safely move fprintf_styled into interf.c too, and all would
be good.
But I don't have time right now to start debugging the erc32
simulator, so I wanted a solution that fixes the build without
introducing multiple definition errors.
The easiest solution I think is to just have two copies of
fprintf_styled, one in sis.c, and one in interf.c. Unlike run_sim,
these two copies are both static, so we will not run into multiple
definition issues with this function. The functions themselves are
not very big, so it's not a huge amount of duplicate code.
I am very aware that this is not an ideal solution, and I would
welcome anyone who wants to take on fixing the run_sim problem
properly, and then cleanup the fprintf_styled duplication.
When generating TLS dynamic relocations the existing xtensa BFD code
treats linking to a PIE exactly as linking to a shared object, resulting
in generation of wrong relocations for TLS entries. Fix that and add
tests.
bfd/
* elf32-xtensa.c (elf_xtensa_check_relocs): Use bfd_link_dll
instead of bfd_link_pic. Add elf_xtensa_dynamic_symbol_p test
when generating GOT entries.
(elf_xtensa_relocate_section): Use bfd_link_dll instead of
bfd_link_pic.
ld/
* testsuite/ld-xtensa/tlspie.dd: New file.
* testsuite/ld-xtensa/tlspie.rd: New file.
* testsuite/ld-xtensa/tlspie.sd: New file.
* testsuite/ld-xtensa/tlspie.td: New file.
* testsuite/ld-xtensa/xtensa-linux.exp (TLS PIE transitions):
New test.
objdump output for l32r opcode was changed in commit b3ea76397a
("opcodes: xtensa: display loaded literal value"), but xtensa linker TLS
relaxation tests weren't adjusted accordingly.
readelf output was changed in commit 2335639744 ("Adjust readelf's
output so that section symbols without a name as shown with their
section name."), but xtensa linker TLS relaxation tests weren't adjusted
accordingly.
Fix expected output changes in xtensa ld TLS relaxation tests.
ld/
* testsuite/ld-xtensa/tlsbin.dd: Adjust expected output for l32r
opcodes.
* testsuite/ld-xtensa/tlsbin.rd: Adjust expected output to allow
for named section symbols.
* testsuite/ld-xtensa/tlspic.dd: Adjust expected output for l32r
opcodes.
* testsuite/ld-xtensa/tlspic.rd: Adjust expected output to allow
for named section symbols.
This patch makes possible to print the highest address (-1) and the addresses
related to gp which value is -1. This is particularly useful if the highest
address space is used for I/O registers and corresponding symbols are defined.
Besides, despite that it is very rare to have GP the highest address, it would
be nice because we enabled highest address printing on regular cases.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-topaddr.s: New test for the top
address (-1) printing.
* testsuite/gas/riscv/dis-addr-topaddr-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-64.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp.s: New test for
GP-relative addressing when GP is the highest address (-1).
* testsuite/gas/riscv/dis-addr-topaddr-gp-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-topaddr-gp-64.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (struct riscv_private_data): Add `to_print_addr' to
enable printing the highest address.
(maybe_print_address): Utilize `to_print_addr'.
(riscv_disassemble_insn): Likewise.
If either the base register is `zero', `tp' or `gp' and XLEN is 32, an
incorrectly sign-extended address is produced when printing. This commit
fixes this by fitting an address into a 32-bit value on RV32.
Besides, H. Peter Anvin discovered that we have wrong address computation
for JALR instruction (the initial bug is back in 2018). This commit also
fixes that based on the idea of Palmer Dabbelt.
gas/
pr29342
* testsuite/gas/riscv/lla32.d: Reflect RV32 address computation fix.
* testsuite/gas/riscv/dis-addr-overflow.s: New testcase.
* testsuite/gas/riscv/dis-addr-overflow-32.d: Likewise.
* testsuite/gas/riscv/dis-addr-overflow-64.d: Likewise.
opcodes/
pr29342
* riscv-dis.c (maybe_print_address): Fit address into 32-bit on RV32.
(print_insn_args): Fix JALR address by adding EXTRACT_ITYPE_IMM.
Address sequences involving ADDIW/C.ADDIW instructions require special
handling to sign-extend lower 32-bits of the original result.
This commit tests whether this sign-extension works.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw.s: New to test the address
computation with sign extension as used in ADDIW/C.ADDIW.
* testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0.
* testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1.
gas/ChangeLog:
* testsuite/gas/riscv/dis-addr-addiw-a.d: New test.
* testsuite/gas/riscv/dis-addr-addiw-b.d: New test.
* testsuite/gas/riscv/dis-addr-addiw.s: New test.
The commit bf11021653 "* MAINTAINERS: Perform some obvious fixups."
back in 2009 changed the mailing list address gdb-patches@sources.redhat.com
to gdb-patches@sourceware.org.
This commit does the same to sim/MAINTAINERS.
sim/ChangeLog:
* MAINTAINERS: Update mailing list address.
Change-Id: I56c6bf21a4bddfb35ffc3336ffcba7ff9b39926e
When running the gdb/configure script on ubuntu 22.04 with
python-3.10.4, I see:
checking for python... no
checking for python3... /usr/bin/python3
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils package is deprecated and slated for removal in Python 3.12. Use setuptools or check PEP 632 for potential alternatives
from distutils import sysconfig
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils.sysconfig module is deprecated, use sysconfig instead
from distutils import sysconfig
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils package is deprecated and slated for removal in Python 3.12. Use setuptools or check PEP 632 for potential alternatives
from distutils import sysconfig
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils.sysconfig module is deprecated, use sysconfig instead
from distutils import sysconfig
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils package is deprecated and slated for removal in Python 3.12. Use setuptools or check PEP 632 for potential alternatives
from distutils import sysconfig
[...]/gdb/python/python-config.py:7: DeprecationWarning: The distutils.sysconfig module is deprecated, use sysconfig instead
from distutils import sysconfig
checking for python... yes
The distutils module is deprecated as per the PEP 632[1] and will be
removed in python-3.12.
This patch migrates gdb/python/python-config.py from distutils.sysconfig
to the sysconfig module[2].
The sysconfig module has has been introduced in the standard library in
python 3.2. Given that support for python < 3.2 has been removed by
edae3fd660: "gdb/python: remove Python 2 support", this patch does not
need to support both implementations for backward compatibility.
Tested on ubuntu-22.04 and ubuntu 20.04.
[1] https://peps.python.org/pep-0632/
[2] https://docs.python.org/3/library/sysconfig.html
Change-Id: Id0df2baf3ee6ce68bd01c236b829ab4c0a4526f6
PR mi/10347 points out that using interpreter-exec inside of a
"define" command will crash gdb. The bug here is that
gdb_setup_readline doesn't check for the case where instream==nullptr.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=10347
PR mi/15811 points out that "source"ing a file that uses
interpreter-exec will put gdb in a weird state, where the CLI stops
working. The bug is that tui_interp::suspend does not unregister the
event file descriptor.
The test case is from Andrew Burgess.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=15811
gdb_setup_readline makes new streams and assigns to the various stream
members of struct ui. However, these assignments cause the previous
values to leak. As far as I can, this code is simply unnecessary and
can be removed -- with the exception of the assignment to gdb_stdtarg,
which is not initialized anywhere else.
A few spots setting some gdb output stream variables have a "for
moment" comment. These comments aren't useful and I think the moment
has passed -- these are permanent now.
This changes gdb so that, if ui::input_fd is set to -1, then it will
not be registered with the event loop. This is useful for the DAP
support code I wrote, but as it turns out to also be useful to
Insight, it seems best to check it in separately.
First, some background on the RISC-V registers fflags, frm, and fcsr.
These three registers all relate to the floating-point status and
control mechanism on RISC-V. The fcsr is the floatint-point control
status register, and consists of two parts, the flags (bits 0 to 4)
and the rounding-mode (bits 5 to 7).
The fcsr register is just one of many control/status registers (or
CSRs) available on RISC-V. The fflags and frm registers are also
CSRs. These CSRs are aliases for the relevant parts of the fcsr
register. So fflags is an alias for bits 0 to 4 of fcsr, and frm is
an alias for bits 5 to 7 of fcsr.
This means that a user can change the floating-point rounding mode
either, by writing a complete new value into fcsr, or by writing just
the rounding mode into frm.
How this impacts on GDB is like this: a target description could,
legitimately include all three registers, fcsr, fflags, and frm. The
QEMU target currently does this, and this makes sense. The target is
emulating the complete system, and has all three CSRs available, so
why not tell GDB about this.
In contrast, the RISC-V native Linux target only has access to the
fcsr. This is because the ptrace data structure that the kernel uses
for reading and writing floating point state only contains a copy of
the fcsr, after all, this one field really contains both the fflags
and frm fields, so why carry around duplicate data.
So, we might expect that the target description for the RISC-V native
Linux GDB would only contain the fcsr register. Unfortunately, this
is not the case. The RISC-V native Linux target uses GDB's builtin
target descriptions by calling riscv_lookup_target_description, this
will then add an fpu feature from gdb/features/riscv, either
32bit-fpu.xml or 64bit-fpu.xml. The problem, is that these features
include an entry for fcsr, fflags, and frm. This means that GDB
expects the target to handle reading and writing these registers. And
the RISC-V native Linux target currently doesn't.
In riscv_linux_nat_target::store_registers and
riscv_linux_nat_target::fetch_registers only the fcsr register is
handled, this means that, for RISC-V native Linux, the fflags and frm
registers always show up as <unavailable> - they are present in the
target description, but the target doesn't know how to access the
registers.
A final complication relating to these floating pointer CSRs is which
target description feature the registers appear in.
These registers are CSRs, so it would seem sensible that these
registers should appear in the CSR target description feature.
However, when I first added RISC-V target description support, I was
using a RISC-V simulator that didn't support any CSRs other than the
floating point related ones. This simulator bundled all the float
related CSRs into the fpu target feature. This didn't feel completely
unreasonable to me, and so I had GDB check for these registers in
either target feature.
In this commit I make some changes relating to how GDB handles the
three floating point CSR:
1. Remove fflags and frm from 32bit-fpu.xml and 64bit-fpu.xml. This
means that the default RISC-V target description (which RISC-V native
FreeBSD), and the target descriptions created for RISC-V native Linux,
will not include these registers. There's nothing stopping some other
target (e.g. QEMU) from continuing to include all three of these CSRs,
the code in riscv-tdep.c continues to check for all three of these
registers, and will handle them correctly if they are present.
2. If a target supplied fcsr, but does not supply fflags and/or frm,
then RISC-V GDB will now create two pseudo registers in order to
emulate the two missing CSRs. These new pseudo-registers do the
obvious thing of just reading and writing the fcsr register.
3. With the new pseudo-registers we can no longer make use of the GDB
register numbers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM.
These will be the numbers used if the target supplies the registers in
its target description, but, if GDB falls back to using
pseudo-registers, then new, unique numbers will be used. To handle
this I've added riscv_gdbarch_tdep::fflags_regnum and
riscv_gdbarch_tdep::frm_regnum, I've then updated the RISC-V code to
compare against these fields.
When adding the pseudo-register support, it is important that the
pseudo-register numbers are calculated after the call to
tdesc_use_registers. This is because we don't know the total number
of physical registers until after this call, and the psuedo-register
numbers must follow on from the real (target supplied) registers.
I've updated some tests to include more testing of the fflags and frm
registers, as well as adding a new test.
This commit adds a new function to the target description API within
GDB. This new function is not used in this commit, but will be used
in the next commit, I'm splitting it out into a separate patch for
easier review.
What I want to do in the next commit is check to see if a target
description supplied a particular register, however, the register in
question could appear in one of two possible features.
The new function allows me to ask the tdesc_arch_data whether a
register was found and assigned a particular GDB register number once
all of the features have been checked. I think this is a much simpler
solution than adding code such that, while checking each feature, I
spot if the register I'm processing is the one I care about.
No tests here as the new code is not used, but this code will be
exercised in the next commit.
