instructions. Add missing test in do_mov1.
* gas/mn10300/mov1.s: Add missing test.
We should now assemble just about anything without any
immediate operands.
* config/tc-m68k.c (select_control_regs): New function, extracted
out of m68k_init_after_args.
(m68k_init_after_args): Use it.
(mri_chip): Use it here as well to update set of allowed control
regs for movec.
(obj_elf_section): Add the section symbol to the symbol table.
* config/obj-elf.h (obj_begin): Define.
(elf_begin): Declare.
* as.c (perform_an_assembly_pass): Call obj_begin if it is
defined.
* obj-evax.h: move openvms definitions from here to tc-alpha.c.
* tc-alpha.c: add support for vms_case_hack like in vax/vms.
(load_expression): track clobbering of base reg before jmp/jsr.
(s_alpha_file): pass case_hack flags and source filename via
symbol table to bfd.
* tc-alpha.h (TC_CONS_FIX_NEW): define
pseudo-op.
(s_space): In m68k MRI mode, align to a word boundary.
* macro.c (define_macro): Add namep parameter. Change all
callers.
* macro.h (define_macro): Update declaration.
(parse_args): Change version printing to match current GNU
standards.
* gasp.c (show_usage): Print bug report address.
(main): Change version printing to match current GNU standards.
* config/tc-arm.c (md_apply_fix3): Update two thumb instruction
slots when processing BL fixups.
* config/tc-arm.c (output_inst): Ensure Thumb BL fixup is marked
on the first half of the instruction.
Thu Sep 12 10:28:44 1996 James G. Smith <jsmith@cygnus.co.uk>
* gas/arm/thumb.s (back): Check assembly of Thumb BL.
mips_cpu is 5000, set interlocks and cop_interlocks.
(mips_ip): Give a better error message if the ISA level is wrong.
(md_parse_option): Recognize -mcpu=[v][r]5000.
* config/tc-d10v.c (d10v_dot_word): New function to support
"@word" with the word pseudo-op.
(md_apply_fix3): Cleanup and changes to support correct sizes
for 16 and 18-bit relocs.
* config/tc-mips.c (load_register): Remove unnecessary code that
was causing the high 32bits of 64bit constants to be lost.
Fixes PR10503. The compiler was producing the assembler code:
dli $3,0xfffffffffffff
when constructing the softfloat library. Unfortunately it was being
incorrectly assembled.
(v850_reloc_prefix): Provide prototype.
(postfix, get_reloc, build_insn): Remove prototypes for nonexistant
functions.
(md_begin, md_assemble, md_apply_fix3): Remove unused variables.
(md_assemble): Add default to case statement.
Minor cleanups.
routines to fetch/store the updated instruction from/to memory.
(v850_insert_operand): If the operand has a specialized insert
routine, call it.
Getting fixups closer. At least br <target> works now.
be like identical function found in tc-ppc.c.
(get_reloc): Removed.
(v850_reloc_prefix): New function, parse lo(), hi() and hi0().
(md_assemble): emit fixups.
(md_pcrel_from): renamed from md_pcrel_from_section, emit proper
displacement.
(md_apply_fix3): handle fixups/relocs.
* config/tc-v850.h (MD_PCREL_FROM_SECTION): Removed definition.
* configure.in (sh-*-elf*): New target.
* config/tc-sh.h (TARGET_ARCH): Define.
(WORKING_DOT_WORD): Define.
(TC_COFF_FIX2RTYPE): Only define if OBJ_COFF.
(BFD_ARCH, COFF_MAGIC, TC_COUNT_RELOC): Likewise.
(TC_RELOC_MANGLE, tc_coff_symbol_emit_hook): Likewise.
(DO_NOT_STRIP, NEED_FX_R_TYPE, TC_KEEP_FX_OFFSET): Likewise.
(TC_COFF_SIZEMACHDEP, tc_frob_file): Likewise.
(SUB_SEGMENT_ALIGN): Likewise.
(RELOC_32): Don't define.
(tc_frob_file_before_adjust): Define if BFD_ASSEMBLER.
(target_big_endian): Declare if OBJ_ELF.
(TARGET_FORMAT): Define if OBJ_ELF.
* config/tc-sh.c: Use BFD reloc codes instead of SH COFF reloc
numbers throughout.
(tc_crawl_symbol_chain): Only define if OBJ_COFF.
(tc_headers_hook, tc_coff_sizemachdep): Likewise.
(struct sh_count_relocs): Define.
(sh_count_relocs): New static function, broken out of
sh_frob_file. Add BFD_ASSEMBLER code.
(sh_frob_section): Likewise.
(sh_frob_file): Call sh_frob_section.
(md_convert_frag): If BFD_ASSEMBLER, change type of headers, and
call section_symbol rather than seg_info (seg)->dot.
(md_section_align): Add OBJ_ELF version.
(SWITCH_TABLE_CONS): Define.
(SWITCH_TABLE): Use SWITCH_TABLE_CONS.
(md_apply_fix): Change parameter types if BFD_ASSEMBLER. Only
handle fx_r_type == 0 if not BFD_ASSEMBLER. Return 0 if
BFD_ASSEMBLER.
(struct reloc_map): Define if not BFD_ASSEMBLER.
(coff_reloc_map): Likewise.
(sh_coff_reloc_mangle): Use coff_reloc_map to convert fx_r_type.
(tc_gen_reloc): New function if BFD_ASSEMBLER.
* write.c (write_relocs): Ifdef out fx_where test which triggers
inappropriately for SH ELF.
(write_object_file): Call tc_frob_file_before_adjust and
obj_frob_file_before_adjust if they are defined.
* write.c (write_object_file): Use BFD_RELOC_16, not
BFD_RELOC_NONE, when calling fix_new_exp for a broken word.
* config/tc-d10v.c (find_opcode): Fix a bug which could generate
the wrong opcode for cases like st2w where there are many forms
of the same instruction.
calling symbol_find_or_make.
* config/tc-ppc.h (md_parse_name): Define.
(ppc_parse_name): Declare.
* config/tc-ppc.c (reg_name_search): Add regs and regcount
parameters.
(register_name): Update call to reg_name_search.
(cr_operand): New static variable.
(cr_names): New static const array.
(ppc_parse_name): New function.
(md_assemble): If PPC_OPERAND_CR is set in the operand flags, set
cr_operand before calling expression.
PR 10460.
* config/tc-d10v.c: Fixed ".word". Fixed problem with range checking
on addresses. Improved error messages.
* doc/c-d10v.texi: Added docs for register pairs.
(add_file): Restore old file merging code, but only merge files if
fMerge is set.
(ecoff_directive_loc): Clear fMerge field of current file.
(ecoff_generate_asm_lineno): Likewise.
any given register table.
(register_name): Pass appropriate table and size to reg_name_search.
(system_register_name): New function.
(SYSREG_NAME_CNT): Define.
(md_assemble): Handle operands which are system registers.
Still working on the parser..
opcode doesn't want a register, then we don't have a match.
(md_assemble): Get size of the instruction from the opcode table.
So we choose the right opcode and so that we get the sizes right.
Add support for openVMS/Alpha.
* as.h (PRINTF_LIKE): Don't define if VMS, for now.
* config/obj-evax.c: New file.
* config/obj-evax.h: New file.
* config/tc-alpha.c: Add support for EVAX format if OBJ_EVAX is
defined.
* config/tc-alpha.h: Add support for EVAX format if OBJ_EVAX is
defined. Add case for bfd_target_evax_flavour.
* config/vms-a-conf.h: New file.
* conf-a-gas.com: New file.
* configure.in: Add target alpha-*-*vms*.
* configure: Rebuild.
* makefile.vms: New file.
* read.c (s_lcomm): Align bss_seg on 8 byte boundary if OBJ_EVAX.
Don't call ffs on openVMS/Alpha.
by a constant before entering the main switch. Reject attempts to
apply an arithmetic function to non-absolute symbols, except for
the special case of subtraction of two symbols in the same
section.
* configure.in: Make GAS_CHECK_DECL_NEEDED include <string.h> or
<strings.h> if they exist. Call GAS_CHECK_DECL_NEEDED on strstr
and sbrk.
* acconfig.h (NEED_DECLARATION_STRSTR): New macro.
(NEED_DECLARATION_SBRK): New macro.
* configure, conf.in: Rebuild.
* as.h: Only include <strings.h> if HAVE_STRINGS_H.
(strstr): Declare if NEED_DECLARATION_STRSTR.
* as.c: If HAVE_SBRK and NEED_DECLARATION_SBRK, declare sbrk.
#ifndef OBJ_ELF lines. From Eric Valette <valette@crf.canon.fr>.
(tc_gen_reloc): If out of memory call as_fatal rather than
assert. If no howto found, call as_bad_where rather than
as_fatal. Change the error message slightly. Set howto to a
non-NULL value in order to keep going.
from ".b", ".w" and ".l" extensions. All callers changed. If
the base instruction has no operands, then use the size to
determine which specific instruction to use.
Fixing eepmov instructions.
* config/tc-arm.c: Changed INSN_SIZE to variable insn_size, as
pre-cursor to adding Thumb support. Also added cpu_variant flag
information to each of the asm_flg structures.
(md_parse_option): Updated ARM7 parsing to allow 't' for
thumb/halfword support, aswell as 'm' for long multiply.
(md_show_usage): Updated help message.
(md_assemble): Check that instruction flags are applicated to the
current cpu variant.
(md_apply_fix3, tc_gen_reloc): Add BFD_RELOC_ARM_OFFSET_IMM8 and
BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
signextension instructions.
(do_ldst): Generate halfword and signextension variants if
mnemonic flags match.
(ldst_extend): Do not allow shifts in the offset field of halfword
or signextension instructions.
(validate_offset_imm): Provide check on halfword and signextension
immediate range.
(add_to_lit_pool): Merge identical literal pool values.
Wed Jul 31 15:55:12 1996 James G. Smith <jsmith@cygnus.co.uk>
* gas/arm/arm7t.s: Added.
* gas/arm/arm7t.d: Added.
* gas/arm/arm.exp: Updated to run the new test.
(cons_fix_new_hppa): Don't coke on e_esel.
(tc_gen_reloc, SOM version): Handle R_COMP2 when used
to help generate exception handling tables.
(md_apply_fix): Don't try to apply fixups with an e_esel
selector.
(hppa_fix_adjustable): Fixups with e_esel selectors
are not adjustable.
Another stab at EH on the PA.
* tc-d10v.c: Fix packaging bug. Added range checking.
Added kludge for divs instruction. Fixed minor problem with
multiple text sections.
* tc-d10v.h (d10v_cleanup): Change prototype.
* config/tc-d10v.c: Fix packaging bug. Added range checking.
Added kludge for divs instruction. Fixed minor problem with
multiple text sections.
* config/tc-d10v.h (d10v_cleanup): Change prototype.
Tue Jul 23 10:49:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c (md_apply_fix3): Fix all instruction
addresses to be right-shifted by 2.
end-sanitize-d10v
Mon Jul 22 11:32:36 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c: Many changes to get relocs working.
(register_name): No longer creates a symbol for register names.
(pre_defined_registers): moved to opcodes/d10v-opc.c.
(d10v_insert_operand): Now works correctly for either container.
* config/tc-d10v.h (d10v_cleanup): Declare.
end-sanitize-d10v
* tc-alpha.c: Patches to track current minimum alignment to reduce
the number of fragments created with frag_align.
(alpha_current_align): New static variable.
(s_alpha_text): Reset alignment to 0.
(s_alpha_data, s_alpha_rdata, s_alpha_sdata): Likewise.
(s_alpha_stringer, s_alpha_space): New functions.
(s_alpha_cons, alpha_flush_pending_output): Remove functions.
(alpha_cons_align): New function to replace both of them.
(emit_insn): Only align if alpha_current_align is less than 2;
reset alpha_current_align to 2.
(s_alpha_gprel32): Likewise.
(s_alpha_section): New function. Basically duplicate the other
alpha section change hooks. Only define for ELF.
(s_alpha_float_cons): Simplify alignment handling.
(md_pseudo_table): Only define "rdata" and "sdata" if OBJ_ECOFF.
If OBJ_ELF, define "section", "section.s", "sect", and "sect.s".
Don't define the s_alpha_cons pseudo-ops. Do define
s_alpha_stringer and s_alpha_space pseudo-ops.
(alpha_align): Skip if less than current default alignment. Set
default alignment.
* tc-alpha.h (md_flush_pending_output): Remove.
(md_cons_align): Add.
* tc-alpha.c: Add oodles of function description comments.
(md_bignum_to_chars): Remove; there are no callers.
(md_show_usage): Mention some more variants.
uaxword to use s_uacons.
(sparc_no_align_cons): New static variable.
(s_uacons): New static function.
(sparc_cons_align): If sparc_no_align_cons is set, just clear it
and return.
Wed Jul 17 14:25:13 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* config/tc-d10v.c: New file.
* config/tc-d10v.h: New file.
* configure (d10v-*-elf): New target.
* configure.in (d10v-*-elf): New target.
end-sanitize-d10v
