Commit Graph

689 Commits

Author SHA1 Message Date
Alexander Fedotov-B55613
83eef88358 Missing relocation R_PPC_VLE_ADDR20 and add VLE flag to details in readelf
include/
	* elf/ppc.h (R_PPC_VLE_ADDR20): New relocation.
bfd/
	* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_VLE_ADDR20.
	(ppc_elf_check_relocs): Handle it.
	(ppc_elf_vle_split20): New function.
	(ppc_elf_relocate_section): Handle R_PPC_VLE_ADDR20.
binutils/
	* readelf.c (get_elf_section_flags): Add VLE.
	(process_section_headers): Add VLE key to details.
gas/
	* config/tc-ppc.c (md_parse_option): Handle "mno-vle" flag.
	(ppc_elf_section_letter): New function.
	* config/tc-ppc.h (md_elf_section_letter): New.
	* testsuite/gas/elf/section10.d: Adjust for VLE.
2017-09-05 08:42:27 +09:30
Gustavo Romero
66c3b5f87c Add new NT_PPC_* available since Linux 4.8
Add new note types available since Linux 4.8 to elf/common.h and
make the 'readelf' tool aware of it.

include/
	* elf/common.h (NT_PPC_TAR): New macro.
	(NT_PPC_PPR): Likewise.
	(NT_PPC_DSCR): Likewise.
	(NT_PPC_EBB): Likewise.
	(NT_PPC_PMU): Likewise.
	(NT_PPC_TM_CGPR): Likewise.
	(NT_PPC_TM_CFPR): Likewise.
	(NT_PPC_TM_CVMX): Likewise.
	(NT_PPC_TM_CVSX): Likewise.
	(NT_PPC_TM_SPR): Likewise.
	(NT_PPC_TM_CTAR): Likewise.
	(NT_PPC_TM_CPPR): Likewise.
	(NT_PPC_TM_CDSCR): Likewise.
binutils/
	* readelf.c (get_note_type): Handle PPC note types available
	since Linux 4.8.
2017-08-16 07:45:28 +09:30
John Eric Martin
684d5a10b1 [ARC] Add JLI support.
The following relocation types were added to GCC/binutils:

ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by
GCC as well to adjust the index of function calls to functions with
attribute jli_call_always.

bfd/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
	    John Eric Martin  <John.Martin@emmicro-us.com>

	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf32-arc.c (JLI): Define.
	* reloc.c: Add JLI relocations.

gas/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/jli-1.d: New file.
	* testsuite/gas/arc/jli-1.s: Likewise.
	* testsuite/gas/arc/taux.d: Update for jli_base.

include/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
	    John Eric Martin  <John.Martin@emmicro-us.com>

	* elf/arc-reloc.def: Add JLI relocs howto.
	* opcode/arc-func.h (replace_jli): New function.

ld/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
	    John Eric Martin  <John.Martin@emmicro-us.com>

	* emulparams/arcelf.sh (JLI_START_TABLE): Define.
	* scripttempl/elfarc.sc: Handle jlitab section.
	* scripttempl/elfarcv2.sc: Likewise.
	* testsuite/ld-arc/arc.exp: Add JLI test.
	* testsuite/ld-arc/jli-script.ld: New file.
	* testsuite/ld-arc/jli-simple.dd: Likewise.
	* testsuite/ld-arc/jli-simple.rd: Likewise.
	* testsuite/ld-arc/jli-simple.s: Likewise.
	* testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise.
	* testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise.
	* testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise.

opcode/
2017-07-19  Claudiu Zissulescu  <claziss@synopsys.com>
	    John Eric Martin  <John.Martin@emmicro-us.com>

	* arc-opc.c (UIMM10_6_S_JLIOFF): Define.
	(UIMM3_23): Adjust accordingly.
	* arc-regs.h: Add/correct jli_base register.
	* arc-tbl.h (jli_s): Likewise.
2017-07-19 09:56:55 +02:00
Yuri Chornovian
de194d8575 Fix spelling typos. 2017-07-18 16:58:14 +01:00
John Baldwin
0b9305edf1 Recognize the recently-added FreeBSD core dump note for LWP info.
This core dump note contains the same information returned by the
ptrace PT_LWPINFO operation for each LWP belonging to a process.

binutils/ChangeLog:

	* readelf.c (get_freebsd_elfcore_note_type): Handle
	NT_FREEBSD_PTLWPINFO.

include/ChangeLog:

	* elf/common.h (NT_FREEBSD_PTLWPINFO): Define.
2017-07-07 16:10:47 -07:00
Andreas Arnez
88ab90e860 S390: Support guarded-storage core note sections
Newer Linux kernel versions offer two new register sets in support of the
z/Architecture's guarded storage facility: NT_S390_GS_CB, the
"guarded-storage registers", and NT_S390_GS_BC, the "guarded-storage
broadcast control block".  This patch adds support for the respective core
notes sections to binutils.

bfd/ChangeLog:
	* elf-bfd.h (elfcore_write_s390_gs_cb): Add prototype.
	(elfcore_write_s390_gs_bc): Likewise.
	* elf.c (elfcore_grok_s390_gs_cb): New function.
	(elfcore_grok_s390_gs_bc): New function.
	(elfcore_grok_note): Call them.
	(elfcore_write_s390_gs_cb): New function.
	(elfcore_write_s390_gs_bc): New function.
	(elfcore_write_register_note): Call them.

binutils/ChangeLog:
	* readelf.c (get_note_type): Add NT_S390_GS_CB and NT_S390_GS_BC.

include/ChangeLog:
	* elf/common.h (NT_S390_GS_CB): New macro.
	(NT_S390_GS_BC): Likewise.
2017-06-29 10:30:09 +02:00
Maciej W. Rozycki
38bf472a15 MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
Add support for the Imagination interAptiv MR2 MIPS32r3 processor with
the MIPS16e2 ASE as per documentation, including in particular:

1. Support for implementation-specific interAptiv MR2 COPYW and UCOPYW
   MIPS16e2 instructions[1], for assembly and disassembly,

2. Support for implementation-specific interAptiv MR2 SAVE and RESTORE
   regular MIPS instructions[2], for assembly and disassembly,

3. ELF binary file annotation for the interAptiv MR2 MIPS architecture
   extension.

4. Support for interAptiv MR2 architecture selection for assembly, in
   the form of the `-march=interaptiv-mr2' command-line option and its
   corresponding `arch=interaptiv-mr2' setting for the `.set' and
   `.module' pseudo-ops.

5. Support for interAptiv MR2 architecture selection for disassembly,
   in the form of the `mips:interaptiv-mr2' target architecture, for
   use e.g. with the `-m' command-line option for `objdump'.

Parts of this change by Matthew Fortune and Andrew Bennett.

References:

[1] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
    Imagination Technologies Ltd., Document Number: MD00904, Revision
    02.01, June 15, 2016, Section 24.3 "MIPS16e2 Implementation Specific
    Instructions", pp. 878-883

[2] same, Chapter 25 "Implementation-specific Instructions", pp. 911-917

	include/
	* elf/mips.h (E_MIPS_MACH_IAMR2): New macro.
	(AFL_EXT_INTERAPTIV_MR2): Likewise.
	* opcode/mips.h: Document new operand codes defined.
	(INSN_INTERAPTIV_MR2): New macro.
	(INSN_CHIP_MASK): Adjust accordingly.
	(CPU_INTERAPTIV_MR2): New macro.
	(cpu_is_member) <CPU_INTERAPTIV_MR2>: New case.
	(MIPS16_ALL_ARGS): Rename to...
	(MIPS_SVRS_ALL_ARGS): ... this.
	(MIPS16_ALL_STATICS): Rename to...
	(MIPS_SVRS_ALL_STATICS): ... this.

	bfd/
	* archures.c (bfd_mach_mips_interaptiv_mr2): New macro.
	* cpu-mips.c (I_interaptiv_mr2): New enum value.
	(arch_info_struct): Add "mips:interaptiv-mr2" entry.
	* elfxx-mips.c (_bfd_elf_mips_mach) <E_MIPS_MACH_IAMR2>: New
	case.
	(mips_set_isa_flags) <bfd_mach_mips_interaptiv_mr2>: Likewise.
	(bfd_mips_isa_ext) <bfd_mach_mips_interaptiv_mr2>: Likewise.
	(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
	(mips_mach_extensions): Add `bfd_mach_mipsisa32r3' and
	`bfd_mach_mips_interaptiv_mr2' entries.
	* bfd-in2.h: Regenerate.

	opcodes/
	* mips-formats.h (INT_BIAS): New macro.
	(INT_ADJ): Redefine in INT_BIAS terms.
	* mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
	(mips_print_save_restore): New function.
	(print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
	(validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
	call.
	(print_insn_args): Handle OP_SAVE_RESTORE_LIST.
	(print_mips16_insn_arg): Call `mips_print_save_restore' for
	OP_SAVE_RESTORE_LIST handling, factored out from here.
	* mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
	(RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
	(mips_builtin_opcodes): Add "restore" and "save" entries.
	* mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
	(IAMR2): New macro.
	(mips16_opcodes): Add "copyw" and "ucopyw" entries.

	binutils/
	* readelf.c (get_machine_flags) <E_MIPS_MACH_IAMR2>: New case.
	(print_mips_isa_ext) <AFL_EXT_INTERAPTIV_MR2>: Likewise.
	* NEWS: Mention Imagination interAptiv MR2 processor support.

	gas/
	* config/tc-mips.c (validate_mips_insn): Handle
	OP_SAVE_RESTORE_LIST specially.
	(mips_encode_save_restore, mips16_encode_save_restore): New
	functions.
	(match_save_restore_list_operand): Factor out SAVE/RESTORE
	operand insertion into the instruction word or halfword to these
	new functions.
	(mips_cpu_info_table): Add "interaptiv-mr2" entry.

	* doc/c-mips.texi (MIPS Options): Add `interaptiv-mr2' to the
	`-march=' argument list.
2017-06-28 02:07:36 +01:00
Kuan-Lin Chen
a6cbf936e3 RISC-V: Use pc-relative relocation for FDE initial location
The symbol address in .eh_frame may be adjusted in
_bfd_elf_discard_section_eh_frame, and the content of .eh_frame will be
adjusted in _bfd_elf_write_section_eh_frame. Therefore, we cannot insert
a relocation whose addend symbol is in .eh_frame. Othrewise, the value
may be adjusted twice.

bfd/ChangeLog
2017-06-26  Kuan-Lin Chen  <rufus@andestech.com>

	* elfnn-riscv.c (perform_relocation): Support the new
	R_RISCV_32_PCREL relocation.
	(riscv_elf_relocate_section): Likewise.
	* elfxx-riscv.c (howto_table): Likewise.
	(riscv_reloc_map): Likewise.
	* bfd-in2.h (BFD_RELOC_RISCV_32_PCREL): New relocation.
	* libbfd.h: Regenerate.

gas/ChangeLog
2017-06-26  Kuan-Lin Chen  <rufus@andestech.com>

	* config/tc-riscv.c (md_apply_fix) [BFD_RELOC_32]: Convert to a
	R_RISCV_32_PCREL relocation.

include/ChangeLog
2017-06-26  Kuan-Lin Chen  <rufus@andestech.com>

	* elf/riscv.h (R_RISCV_32_PCREL): New.
2017-06-26 18:26:40 -07:00
Thomas Preud'homme
ced40572e4 [ARM] Add support for ARMv8-R in assembler and readelf
=== Context ===

This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in GAS:
instructions, build attributes and readelf.

=== Patch description ===

Although some differences exist for system registers, from GAS point of
view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state
and a subset of its extensions. This patch therefore introduce a new
feature bit to distinguish the availability of the pan, ras and rdma
extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd
extensions to be used by ARMv8-R.

Most of the changes are then in the testsuite to (i) rename source files
and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename
files with expected output for ARMv8-A build attributes and (iii) add
new files with expected output for ARMv8-R build attributes.

2017-06-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

binutils/
	* readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R.

gas/
	* NEWS: Mention support for ARMv8-R architecture.
	* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
	(arm_extensions): Restrict pan, ras and rdma extension to
	ARMv8-A and make crypto, fp and simd extensions available to
	ARMv8-R.
	(cpu_arch_ver): Add entry for ARMv8-R.
	(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
	logic.
	* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
	* testsuite/gas/arm/armv8-ar+fp.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
	architecture to assemble for.
	* testsuite/gas/arm/armv8-r+fp.d: New.
	* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
	* testsuite/gas/arm/armv8-ar+simd.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
	architecture to assemble for.
	* testsuite/gas/arm/armv8-r+simd.d: New.
	* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
	* testsuite/gas/arm/armv8-ar-bad.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
	* testsuite/gas/arm/armv8-ar-bad.l: This.  Decrement line number by 1.
	* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
	architecture to assemble for and adjust error output file.
	* testsuite/gas/arm/armv8-r-bad.d: New.
	* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
	* testsuite/gas/arm/armv8-ar-barrier.s: This.
	* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
	* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
	* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
	* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
	* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
	* testsuite/gas/arm/armv8-ar-it-bad.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
	* testsuite/gas/arm/armv8-ar-it-bad.l: This.  Decrement line number
	by 1.
	* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
	architecture to assemble for and adjust error output file.
	* testsuite/gas/arm/armv8-r-it-bad.d: New.
	* testsuite/gas/arm/armv8-a.s: Rename into ...
	* testsuite/gas/arm/armv8-ar.s: This.  Remove .arch directive.
	* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
	architecture to assemble for.
	* testsuite/gas/arm/armv8-r.d: New.
	* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
	* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
	* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
	* testsuite/gas/arm/attr-march-armv8-r.d: New.
	* testsuite/gas/arm/crc32.s: Rename into ...
	* testsuite/gas/arm/crc32-armv8-ar.s: This.
	* testsuite/gas/arm/crc32.d: Rename into ...
	* testsuite/gas/arm/crc32-armv8-a.d: This.  Specify source to assemble.
	* testsuite/gas/arm/crc32-armv8-r.d: New.
	* testsuite/gas/arm/crc32-bad.s: Rename into ...
	* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
	* testsuite/gas/arm/crc32-bad.d: Rename into ...
	* testsuite/gas/arm/crc32-armv8-a-bad.d: This.  Specify source to
	assemble.
	* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
	* testsuite/gas/arm/mask_1.s: Rename into ...
	* testsuite/gas/arm/mask_1-armv8-ar.s: This.
	* testsuite/gas/arm/mask_1.d: Rename into ...
	* testsuite/gas/arm/mask_1-armv8-a.d: This.  Specify source to
	assemble.
	* testsuite/gas/arm/mask_1-armv8-r.d: new.

include/
	* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
	* opcode/arm.h (ARM_EXT2_V8A): New macro.
	(ARM_AEXT2_V8A): Rename into ...
	(ARM_AEXT2_V8AR): This.
	(ARM_AEXT2_V8A): New macro.
	(ARM_AEXT_V8R): New macro.
	(ARM_AEXT2_V8R): New macro.
	(ARM_ARCH_V8R): New macro.
2017-06-24 10:37:47 +01:00
Andreas Krebbel
b4cbbe8f72 S/390: Add support for pgste marker
This patch adds a new S/390 specific segment type: PT_S390_PGSTE.  For
binaries marked with that segment the kernel will allocate 4k page
tables.  The only user so far will be qemu.

ld/ChangeLog:

2017-06-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* Makefile.in: Add s390.em as build dependency.
	* emulparams/elf64_s390.sh (EXTRA_EM_FILE): Add s390.em.
	* emultempl/s390.em: New file.
	* gen-doc.texi: Add documentation for --s390-pgste option.
	* ld.texinfo: Likewise.

include/ChangeLog:

2017-06-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* elf/s390.h (PT_S390_PGSTE): Define macro.

binutils/ChangeLog:

2017-06-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* readelf.c (get_s390_segment_type): Add support for the new
	segment type PT_S390_PGSTE.
	(get_segment_type): Call get_s390_segment_type.

elfcpp/ChangeLog:

2017-06-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* elfcpp.h (enum PT): Add PT_S390_PGSTE to enum.

bfd/ChangeLog:

2017-06-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* elf-s390.h: New file.
	* elf64-s390.c (struct elf_s390_link_hash_table): Add params
	field.
	(elf_s390_additional_program_headers): New function.
	(elf_s390_modify_segment_map): New function.
	(bfd_elf_s390_set_options): New function.
	(elf_backend_additional_program_headers)
	(elf_backend_modify_segment_map): Add macro definitions.
2017-06-23 08:00:46 +02:00
H.J. Lu
48580982ef x86: Support Intel Shadow Stack with SHSTK property
To support Intel Shadow Stack (SHSTK) in Intel Control-flow Enforcement
Technology (CET) instructions:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

 #define GNU_PROPERTY_X86_FEATURE_1_SHSTK (1U << 1)

is added to GNU program properties to indicate that all executable sections
are compatible with SHSTK where return address popped from shadow stack
always matches return address popped from normal stack.

GNU_PROPERTY_X86_FEATURE_1_SHSTK is set on output only if it is set on all
relocatable inputs.

bfd/

	* elf32-i386.c (elf_i386_merge_gnu_properties): If info->shstk
	is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK.
	(elf_i386_link_setup_gnu_properties): If info->shstk is set,
	turn on GNU_PROPERTY_X86_FEATURE_1_IBT.
	* elf64-x86-64.c (elf_x86_64_merge_gnu_properties): If
	info->shstk is set, turn on GNU_PROPERTY_X86_FEATURE_1_SHSTK.
	(elf_x86_64_link_setup_gnu_properties): If info->shstk is set,
	turn on GNU_PROPERTY_X86_FEATURE_1_IBT.

binutils/

	* readelf.c (decode_x86_feature): Decode
	GNU_PROPERTY_X86_FEATURE_1_SHSTK.
	* testsuite/binutils-all/i386/shstk.d: New file.
	* testsuite/binutils-all/i386/shstk.s: Likewise.
	* testsuite/binutils-all/x86-64/shstk-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/shstk.d: Likewise.
	* testsuite/binutils-all/x86-64/shstk.s: Likewise.

include/

	* bfdlink.h (bfd_link_info): Add shstk.
	* elf/common.h (GNU_PROPERTY_X86_FEATURE_1_SHSTK): New.

ld/

	* NEWS: Mention -z shstk and GNU_PROPERTY_X86_FEATURE_1_SHSTK.
	* emulparams/cet.sh (PARSE_AND_LIST_OPTIONS_CET): Add "-z shstk".
	(PARSE_AND_LIST_ARGS_CASE_Z_CET): Support "-z shstk".
	* ld.texinfo: Document -z shstk.
	* testsuite/ld-i386/i386.exp: Run SHSTK tests.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* testsuite/ld-i386/property-x86-shstk.s: New file.
	* testsuite/ld-i386/property-x86-shstk1a.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk1b.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk2.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk3a.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk3b.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk4.d: Likewise.
	* testsuite/ld-i386/property-x86-shstk5.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk.s: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk1b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk2-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk2.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk3b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk4-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk4.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk5-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-shstk5.d: Likewise.
2017-06-22 05:50:31 -07:00
H.J. Lu
ee2fdd6f36 x86: Support Intel IBT with IBT property and IBT-enable PLT
To support IBT in Intel Control-flow Enforcement Technology (CET)
instructions:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

 #define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002

 #define GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0)

are added to GNU program properties to indicate that all executable
sections are compatible with IBT when ENDBR instruction starts each
valid target where an indirect branch instruction can land.

GNU_PROPERTY_X86_FEATURE_1_IBT is set on output only if it is set on
all relocatable inputs.

The followings changes are made to the Procedure Linkage Table (PLT):

1. For 64-bit x86-64,  PLT is changed to

PLT0:  push       GOT[1]
       bnd jmp    *GOT[2]
       nop
...
PLTn:  endbr64
       push       namen_reloc_index
       bnd jmp    PLT0

together with the second PLT section:

PLTn:  endbr64
       bnd jmp   *GOT[namen_index]
       nop

BND prefix is also added so that IBT-enabled PLT is compatible with MPX.

2. For 32-bit x86-64 (x32) and i386,  PLT is changed to

PLT0:  push       GOT[1]
       jmp        *GOT[2]
       nop
...
PLTn:  endbr64                                 # endbr32 for i386.
       push       namen_reloc_index
       jmp        PLT0

together with the second PLT section:

PLTn:  endbr64                                 # endbr32 for i386.
       jmp       *GOT[namen_index]
       nop

BND prefix isn't used since MPX isn't supported on x32 and BND registers
aren't used in parameter passing on i386.

GOT is an array of addresses.  Initially, GOT[namen_index] is filled
with the address of the ENDBR instruction of the corresponding entry
in the first PLT section.  The function, namen, is called via the
ENDBR instruction in the second PLT entry.  GOT[namen_index] is updated
to the actual address of the function, namen, at run-time.

2 linker command line options are added:

1. -z ibtplt: Generate IBT-enabled PLT.
2. -z ibt: Generate GNU_PROPERTY_X86_FEATURE_1_IBT in GNU program
properties as well as IBT-enabled PLT.

bfd/

	* elf32-i386.c (elf_i386_lazy_ibt_plt0_entry): New.
	(elf_i386_lazy_ibt_plt_entry): Likewise.
	(elf_i386_pic_lazy_ibt_plt0_entry): Likewise.
	(elf_i386_non_lazy_ibt_plt_entry): Likewise.
	(elf_i386_pic_non_lazy_ibt_plt_entry): Likewise.
	(elf_i386_eh_frame_lazy_ibt_plt): Likewise.
	(elf_i386_lazy_plt_layout): Likewise.
	(elf_i386_non_lazy_plt_layout): Likewise.
	(elf_i386_link_hash_entry): Add plt_second.
	(elf_i386_link_hash_table): Add plt_second and
	plt_second_eh_frame.
	(elf_i386_allocate_dynrelocs): Use the second PLT if needed.
	(elf_i386_size_dynamic_sections): Use .plt.got unwind info for
	the second PLT.  Check the second PLT.
	(elf_i386_relocate_section): Use the second PLT to resolve
	PLT reference if needed.
	(elf_i386_finish_dynamic_symbol): Fill and use the second PLT if
	needed.
	(elf_i386_finish_dynamic_sections): Set sh_entsize on the
	second PLT.  Generate unwind info for the second PLT.
	(elf_i386_plt_type): Add plt_second.
	(elf_i386_get_synthetic_symtab): Support the second PLT.
	(elf_i386_parse_gnu_properties): Support
	GNU_PROPERTY_X86_FEATURE_1_AND.
	(elf_i386_merge_gnu_properties): Support
	GNU_PROPERTY_X86_FEATURE_1_AND.  If info->ibt is set, turn
	on GNU_PROPERTY_X86_FEATURE_1_IBT
	(elf_i386_link_setup_gnu_properties): If info->ibt is set,
	turn on GNU_PROPERTY_X86_FEATURE_1_IBT.  Use IBT-enabled PLT
	for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT
	is set on all relocatable inputs.
	* elf64-x86-64.c (elf_x86_64_lazy_ibt_plt_entry): New.
	(elf_x32_lazy_ibt_plt_entry): Likewise.
	(elf_x86_64_non_lazy_ibt_plt_entry): Likewise.
	(elf_x32_non_lazy_ibt_plt_entry): Likewise.
	(elf_x86_64_eh_frame_lazy_ibt_plt): Likewise.
	(elf_x32_eh_frame_lazy_ibt_plt): Likewise.
	(elf_x86_64_lazy_ibt_plt): Likewise.
	(elf_x32_lazy_ibt_plt): Likewise.
	(elf_x86_64_non_lazy_ibt_plt): Likewise.
	(elf_x32_non_lazy_ibt_plt): Likewise.
	(elf_x86_64_get_synthetic_symtab): Support the second PLT.
	(elf_x86_64_parse_gnu_properties): Support
	GNU_PROPERTY_X86_FEATURE_1_AND.
	(elf_x86_64_merge_gnu_properties): Support
	GNU_PROPERTY_X86_FEATURE_1_AND.  If info->ibt is set, turn
	on GNU_PROPERTY_X86_FEATURE_1_IBT
	(elf_x86_64_link_setup_gnu_properties): If info->ibt is set,
	turn on GNU_PROPERTY_X86_FEATURE_1_IBT.  Use IBT-enabled PLT
	for info->ibtplt, info->ibt or GNU_PROPERTY_X86_FEATURE_1_IBT
	is set on all relocatable inputs.

binutils/

	* readelf.c (decode_x86_feature): New.
	(print_gnu_property_note): Call decode_x86_feature on
	GNU_PROPERTY_X86_FEATURE_1_AND.
	* testsuite/binutils-all/i386/empty.d: New file.
	* testsuite/binutils-all/i386/empty.s: Likewise.
	* testsuite/binutils-all/i386/ibt.d: Likewise.
	* testsuite/binutils-all/i386/ibt.s: Likewise.
	* testsuite/binutils-all/x86-64/empty-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/empty.d: Likewise.
	* testsuite/binutils-all/x86-64/empty.s: Likewise.
	* testsuite/binutils-all/x86-64/ibt-x32.d: Likewise.
	* testsuite/binutils-all/x86-64/ibt.d: Likewise.
	* testsuite/binutils-all/x86-64/ibt.s: Likewise.

include/

	* bfdlink.h (bfd_link_info): Add ibtplt and ibt.
	* elf/common.h (GNU_PROPERTY_X86_FEATURE_1_AND): New.
	(GNU_PROPERTY_X86_FEATURE_1_IBT): Likewise.

ld/

	* Makefile.am (ELF_X86_DEPS): Add $(srcdir)/emulparams/cet.sh.
	* Makefile.in: Regenerated.
	* NEWS: Mention GNU_PROPERTY_X86_FEATURE_1_IBT, -z ibtplt
	and -z ibt.
	* emulparams/cet.sh: New file.
	* testsuite/ld-i386/ibt-plt-1.d: Likewise.
	* testsuite/ld-i386/ibt-plt-1.s: Likewise.
	* testsuite/ld-i386/ibt-plt-2.s: Likewise.
	* testsuite/ld-i386/ibt-plt-2a.d: Likewise.
	* testsuite/ld-i386/ibt-plt-2b.d: Likewise.
	* testsuite/ld-i386/ibt-plt-2c.d: Likewise.
	* testsuite/ld-i386/ibt-plt-2d.d: Likewise.
	* testsuite/ld-i386/ibt-plt-3.s: Likewise.
	* testsuite/ld-i386/ibt-plt-3a.d: Likewise.
	* testsuite/ld-i386/ibt-plt-3b.d: Likewise.
	* testsuite/ld-i386/ibt-plt-3c.d: Likewise.
	* testsuite/ld-i386/ibt-plt-3d.d: Likewise.
	* testsuite/ld-i386/plt-main-ibt.dd: Likewise.
	* testsuite/ld-i386/plt-pie-ibt.dd: Likewise.
	* testsuite/ld-i386/property-x86-empty.s: Likewise.
	* testsuite/ld-i386/property-x86-ibt.s: Likewise.
	* testsuite/ld-i386/property-x86-ibt1a.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt1b.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt2.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt3a.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt3b.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt4.d: Likewise.
	* testsuite/ld-i386/property-x86-ibt5.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-1-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-1.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-1.s: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2.s: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2a-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2a.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2b-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2b.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2c-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2c.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2d-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-2d.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3.s: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3a-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3a.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3b-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3b.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3c-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3c.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3d-x32.d: Likewise.
	* testsuite/ld-x86-64/ibt-plt-3d.d: Likewise.
	* testsuite/ld-x86-64/plt-main-ibt-now.rd: Likewise.
	* testsuite/ld-x86-64/plt-main-ibt-x32.dd: Likewise.
	* testsuite/ld-x86-64/plt-main-ibt.dd: Likewise.
	* testsuite/ld-x86-64/property-x86-empty.s: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt.s: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt1b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt2-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt2.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3a-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3a.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3b-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt3b.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt4-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt4.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt5-x32.d: Likewise.
	* testsuite/ld-x86-64/property-x86-ibt5.d: Likewise.
	* emulparams/elf32_x86_64.sh: Source emulparams/cet.sh.
	(TINY_READONLY_SECTION): Add .plt.sec.
	* emulparams/elf_i386.sh: Likewise.
	* emulparams/elf_x86_64.sh: Source emulparams/cet.sh.
	* ld.texinfo: Document -z ibtplt and -z ibt.
	* testsuite/ld-i386/i386.exp: Run IBT and IBT PLT tests.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* testsuite/ld-x86-64/pr21481b.S (check): Updated for x32.
2017-06-22 05:44:53 -07:00
Alan Modra
f378ab099d PPC64_OPT_LOCALENTRY
ELFv2 functions with localentry:0 are those with a single entry point,
ie. global entry == local entry, and that have no requirement on r2 or
r12, and guarantee r2 is unchanged on return.  Such an external
function can be called via the PLT without saving r2 or restoring it
on return, avoiding a common load-hit-store for small functions.   The
optimization is attractive.  The TOC pointer load-hit-store is a major
reason why calls to small functions that need no register saves, or
with shrink-wrap, no register saves on a fast path, are slow on
powerpc64le.

To be safe, this optimization needs ld.so support to check that the
run-time matches link-time function implementation.  If a function
in a shared library with st_other localentry non-zero is called
without saving and restoring r2, r2 will be trashed on return, leading
to segfaults.  For that reason the optimization does not happen for
weak functions since a weak definition is a fairly solid hint that the
function will likely be overridden.  I'm also not enabling the
optimization by default unless glibc-2.26 is detected, which should
have the ld.so checks implemented.

bfd/
	* elf64-ppc.c (struct ppc_link_hash_table): Add has_plt_localentry0.
	(ppc64_elf_merge_symbol_attribute): Merge localentry bits from
	dynamic objects.
	(is_elfv2_localentry0): New function.
	(ppc64_elf_tls_setup): Default params->plt_localentry0.
	(plt_stub_size): Adjust size for tls_get_addr_opt stub.
	(build_tls_get_addr_stub): Use a simpler stub when r2 is not saved.
	(ppc64_elf_size_stubs): Leave stub_type as ppc_stub_plt_call for
	optimized localentry:0 stubs.
	(ppc64_elf_build_stubs): Save r2 in ELFv2 __glink_PLTresolve.
	(ppc64_elf_relocate_section): Leave nop unchanged for optimized
	localentry:0 stubs.
	(ppc64_elf_finish_dynamic_sections): Set PPC64_OPT_LOCALENTRY in
	DT_PPC64_OPT.
	* elf64-ppc.h (struct ppc64_elf_params): Add plt_localentry0.
include/
	* elf/ppc64.h (PPC64_OPT_LOCALENTRY): Define.
ld/
	* emultempl/ppc64elf.em (params): Init plt_localentry0 field.
	(enum ppc64_opt): New, replacing OPTION_* defines.  Add
	OPTION_PLT_LOCALENTRY, and OPTION_NO_PLT_LOCALENTRY.
	(PARSE_AND_LIST_*): Support --plt-localentry and --no-plt-localentry.
	* testsuite/ld-powerpc/elfv2so.d: Update.
	* testsuite/ld-powerpc/powerpc.exp (TLS opt 5): Use --no-plt-localentry.
	* testsuite/ld-powerpc/tlsopt5.d: Update.
2017-06-01 22:47:32 +09:30
Anton Kolesov
940171d086 [ARC] Add arc-cpu.def with processor definitions
This patch extracts ARC CPU definitions from gas/config/tc-arc.c (cpu_types)
into a separate file arc-cpu.def.  This will allow reuse of CPU type definition
in multiple places where it might be needed, for example in disassembler.  This
will help ensure that gas and disassembker use same option values for CPUs.

arc-cpu.def file relies on preprocessor macroses which are defined somewhere
else.  This for example multiple C files to include arc-cpu.def, but define
different macroses, therefore creating different structures.

include/ChangeLog:
yyyy-mm-dd  Anton Kolesov  <anton.kolesov@synopsys.com>

	* elf/arc-cpu.def: New file.

gas/ChangeLog:
yyyy-mm-dd  Anton Kolesov  <anton.kolesov@synopsys.com>

	* config/tc-arc.c (cpu_types): Include arc-cpu.def

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
2017-05-30 16:52:28 +03:00
Jose E. Marchesi
6451799480 binutils: support for the SPARC M8 processor
This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.

New instructions:

- Dictionary Unpack

  + dictunpack

- Partitioned Compare with shifted result

  + Signed variants:   fpcmp{le,gt,eq,ne}{8,16,32}shl
  + Unsigned variants: fpcmpu{le,gt}{8,16,32}shl

- Partitioned Dual-Equal compared, with shifted result

  + fpcmpde{8,16,32}shl

- Partitioned Unsigned Range Compare, with shifted result

  + fpcmpur{8,16,32}shl

- 64-bit shifts on Floating-Point registers

  + fps{ll,ra,rl}64x

- Misaligned loads and stores

  + ldm{sh,uh,sw,uw,x,ux}
  + ldm{sh,uh,sw,uw,x,ux}a
  + ldmf{s,d}
  + ldmf{s,d}a

  + stm{h,w,x}
  + stm{h,w,x}a
  + stmf{s,d}
  + stmf{s,d}a

- Oracle Numbers

  + on{add,sub,mul,div}

- Reverse Bytes/Bits

  + revbitsb
  + revbytes{h,w,x}

- Run-Length instructions

  + rle_burst
  + rle_length

- New crypto instructions

  + sha3

- Instruction to read the new register %entropy

  + rd %entropy

New Alternate Address Identifiers:

- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT

The new assembler command-line options for selecting the M8 architecture
are:

-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.

The corresponding disassembler command-line options are:

-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.

Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux

bfd/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* archures.c (bfd_mach_sparc_v9m8): Define.
	(bfd_mach_sparc_v8plusm8): Likewise.
	(bfd_mach_sparc_v9_p): Adjust to M8.
	(bfd_mach_sparc_64bit_p): Likewise.
	* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
	bfd_mach_sparc_v8plusm8.
	* bfd-in2.h: Regenerated.
	* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
	sparc:v8plusm8.
	* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
	bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
	capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
	SHA3.
	* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
	bfd_mach_sparc_v8plusm8.

binutils/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* NEWS: Mention the SPARC M8 support.

gas/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
	`v9m8' and `v8plusm8'.
	(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
	(get_hwcap_name): Support the M8 hardware capabilities.
	(sparc_ip): Handle new operand types.
	* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
	-Asparc6, and the corresponding -xarch aliases.
	* testsuite/gas/sparc/sparc6.s: New file.
	* testsuite/gas/sparc/sparc6.d: Likewise.
	* testsuite/gas/sparc/sparc6-diag.s: Likewise.
	* testsuite/gas/sparc/sparc6-diag.l: Likewise.
	* testsuite/gas/sparc/fpcmpshl.s: Likewise.
	* testsuite/gas/sparc/fpcmpshl.d: Likewise.
	* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
	* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
	* testsuite/gas/sparc/ldm-stm.s: Likewise.
	* testsuite/gas/sparc/ldm-stm.d: Likewise.
	* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
	* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
	* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
	* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
	* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
	* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
	* testsuite/gas/sparc/on.s: Likewise.
	* testsuite/gas/sparc/on.d: Likewise.
	* testsuite/gas/sparc/on-diag.s: Likewise.
	* testsuite/gas/sparc/on-diag.l: Likewise.
	* testsuite/gas/sparc/rle.s: Likewise.
	* testsuite/gas/sparc/rle.d: Likewise.
	* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
	* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
	* testsuite/gas/sparc/rdasr.d: Likewise.

include/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
	(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
	(ELF_SPARC_HWCAP2_ONMUL): Likewise.
	(ELF_SPARC_HWCAP2_ONDIV): Likewise.
	(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
	(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
	(ELF_SPARC_HWCAP2_RLE): Likewise.
	(ELF_SPARC_HWCAP2_SHA3): Likewise.
	* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
	and adjust SPARC_OPCODE_ARCH_MAX.
	(HWCAP2_SPARC6): Define.
	(HWCAP2_ONADDSUB): Likewise.
	(HWCAP2_ONMUL): Likewise.
	(HWCAP2_ONDIV): Likewise.
	(HWCAP2_DICTUNP): Likewise.
	(HWCAP2_FPCMPSHL): Likewise.
	(HWCAP2_RLE): Likewise.
	(HWCAP2_SHA3): Likewise.
	(OPM): Likewise.
	(OPMI): Likewise.
	(ONFCN): Likewise.
	(REVFCN): Likewise.
	(SIMM10): Likewise.

opcodes/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
	(X_IMM2): Define.
	(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
	bfd_mach_sparc_v9m8.
	(print_insn_sparc): Handle new operand types.
	* sparc-opc.c (MASK_M8): Define.
	(v6): Add MASK_M8.
	(v6notlet): Likewise.
	(v7): Likewise.
	(v8): Likewise.
	(v9): Likewise.
	(v9a): Likewise.
	(v9b): Likewise.
	(v9c): Likewise.
	(v9d): Likewise.
	(v9e): Likewise.
	(v9v): Likewise.
	(v9m): Likewise.
	(v9andleon): Likewise.
	(m8): Define.
	(HWS_VM8): Define.
	(HWS2_VM8): Likewise.
	(sparc_opcode_archs): Add entry for "m8".
	(sparc_opcodes): Add OSA2017 and M8 instructions
	dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
	fpx{ll,ra,rl}64x,
	ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
	ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
	revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
	stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
	(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
	ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
	ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
	ASI_CORE_SELECT_COMMIT_NHT.
2017-05-19 09:27:08 -07:00
Maciej W. Rozycki
25499ac7ee MIPS16e2: Add MIPS16e2 ASE support
Add MIPS16e2 ASE support as per the architecture specification[1],
including in particular:

1. A new ELF ASE flag to mark MIPS16e2 binaries.

2. MIPS16e2 instruction assembly support, including a relaxation update
   to use LUI rather than an LI/SLL instruction pair for loading the
   high part of 32-bit addresses.

3. MIPS16e2 instruction disassembly support, including updated rules for
   extended forms of instructions that are now subdecoded and therefore
   do not alias to the original MIPS16 ISA revision instructions even
   for encodings that are not valid in the MIPS16e2 instruction set.

Add `-mmips16e2' and `-mno-mips16e2' GAS command-line options and their
corresponding `mips16e2' and `no-mips16e2' settings for the `.set' and
`.module' pseudo-ops.  Control the availability of the MT ASE subset of
the MIPS16e2 instruction set with a combination of these controls and
the preexisting MT ASE controls.

Parts of this change by Matthew Fortune and Andrew Bennett.

References:

[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
    Extension Technical Reference Manual", Imagination Technologies
    Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016

	include/
	* elf/mips.h (AFL_ASE_MIPS16E2): New macro.
	(AFL_ASE_MASK): Adjust accordingly.
	* opcode/mips.h: Document new operand codes defined.
	(mips_operand_type): Add OP_REG28 enum value.
	(INSN2_SHORT_ONLY): Update description.
	(ASE_MIPS16E2, ASE_MIPS16E2_MT): New macros.

	bfd/
	* elfxx-mips.c (print_mips_ases): Handle MIPS16e2 ASE.

	opcodes/
	* mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
	ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
	(mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
	(print_insn_arg) <OP_REG28>: Add handler.
	(validate_insn_args) <OP_REG28>: Handle.
	(print_mips16_insn_arg): Handle MIPS16 instructions that require
	32-bit encoding and 9-bit immediates.
	(print_insn_mips16): Handle MIPS16 instructions that require
	32-bit encoding and MFC0/MTC0 operand decoding.
	* mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
	<'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
	(RD_C0, WR_C0, E2, E2MT): New macros.
	(mips16_opcodes): Add entries for MIPS16e2 instructions:
	GP-relative "addiu" and its "addu" spelling, "andi", "cache",
	"di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
	"lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
	"movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
	"pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
	instructions, "swl", "swr", "sync" and its "sync_acquire",
	"sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
	"xori", "dmt", "dvpe", "emt" and "evpe".  Add split
	regular/extended entries for original MIPS16 ISA revision
	instructions whose extended forms are subdecoded in the MIPS16e2
	ISA revision: "li", "sll" and "srl".

	binutils/
	* readelf.c (print_mips_ases): Handle MIPS16e2 ASE.
	* NEWS: Mention MIPS16e2 ASE support.

	gas/
	* config/tc-mips.c (RELAX_MIPS16_ENCODE): Add `e2' flag.
	(RELAX_MIPS16_E2): New macro.
	(RELAX_MIPS16_PIC, RELAX_MIPS16_SYM32, RELAX_MIPS16_NOMACRO)
	(RELAX_MIPS16_USER_SMALL, RELAX_MIPS16_USER_EXT)
	(RELAX_MIPS16_DSLOT, RELAX_MIPS16_JAL_DSLOT)
	(RELAX_MIPS16_EXTENDED, RELAX_MIPS16_MARK_EXTENDED)
	(RELAX_MIPS16_CLEAR_EXTENDED, RELAX_MIPS16_ALWAYS_EXTENDED)
	(RELAX_MIPS16_MARK_ALWAYS_EXTENDED)
	(RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED, RELAX_MIPS16_MACRO)
	(RELAX_MIPS16_MARK_MACRO, RELAX_MIPS16_CLEAR_MACRO): Shift bits.
	(mips16_immed_extend): New prototype.
	(options): Add OPTION_MIPS16E2 and OPTION_NO_MIPS16E2 enum
	values.
	(md_longopts): Add "mmips16e2" and "mno-mips16e2" options.
	(mips_ases): Add "mips16e2" entry.
	(mips_set_ase): Handle MIPS16e2 ASE.
	(insn_insert_operand): Explicitly handle immediates with MIPS16
	instructions that require 32-bit encoding.
	(is_opcode_valid_16): Pass enabled ASE bitmask on to
	`opcode_is_member'.
	(validate_mips_insn): Explicitly handle immediates with MIPS16
	instructions that require 32-bit encoding.
	(operand_reg_mask) <OP_REG28>: Add handler.
	(match_reg28_operand): New function.
	(match_operand) <OP_REG28>: Add handler.
	(append_insn): Pass ASE_MIPS16E2 setting to RELAX_MIPS16_ENCODE.
	(match_mips16_insn): Handle MIPS16 instructions that require
	32-bit encoding and `V' and `u' operand codes.
	(mips16_ip): Allow any characters except from `.' in opcodes.
	(mips16_immed_extend): Handle 9-bit immediates.  Do not shuffle
	immediates whose width is not one of these listed.
	(md_estimate_size_before_relax): Handle MIPS16e2 relaxation.
	(mips_relax_frag): Likewise.
	(md_convert_frag): Likewise.
	(mips_convert_ase_flags): Handle MIPS16e2 ASE.

	* doc/as.texinfo (Target MIPS options): Add `-mmips16e2' and
	`-mno-mips16e2' options.
	(-mmips16e2, -mno-mips16e2): New options.
	* doc/c-mips.texi (MIPS Options): Add `-mmips16e2' and
	`-mno-mips16e2' options.
	(MIPS ASE Instruction Generation Overrides): Add `.set mips16e2'
	and `.set nomips16e2'.
2017-05-15 13:57:10 +01:00
Claudiu Zissulescu
53a346d823 [ARC] Object attributes.
gas/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/attr-arc600.d: New file.
	* testsuite/gas/arc/attr-arc600_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc600_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc601.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul32x16.d: Likewise.
	* testsuite/gas/arc/attr-arc601_mul64.d: Likewise.
	* testsuite/gas/arc/attr-arc601_norm.d: Likewise.
	* testsuite/gas/arc/attr-arc700.d: Likewise.
	* testsuite/gas/arc/attr-arcem.d: Likewise.
	* testsuite/gas/arc/attr-archs.d: Likewise.
	* testsuite/gas/arc/attr-autodetect-1.d: Likewise.
	* testsuite/gas/arc/attr-autodetect-1.s: Likewise.
	* testsuite/gas/arc/attr-cpu-a601.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a601.s: Likewise.
	* testsuite/gas/arc/attr-cpu-a700.d: Likewise.
	* testsuite/gas/arc/attr-cpu-a700.s: Likewise.
	* testsuite/gas/arc/attr-cpu-em.d: Likewise.
	* testsuite/gas/arc/attr-cpu-em.s: Likewise.
	* testsuite/gas/arc/attr-cpu-hs.d: Likewise.
	* testsuite/gas/arc/attr-cpu-hs.s: Likewise.
	* testsuite/gas/arc/attr-em.d: Likewise.
	* testsuite/gas/arc/attr-em4.d: Likewise.
	* testsuite/gas/arc/attr-em4_dmips.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpuda.d: Likewise.
	* testsuite/gas/arc/attr-em4_fpus.d: Likewise.
	* testsuite/gas/arc/attr-hs.d: Likewise.
	* testsuite/gas/arc/attr-hs34.d: Likewise.
	* testsuite/gas/arc/attr-hs38.d: Likewise.
	* testsuite/gas/arc/attr-hs38_linux.d: Likewise.
	* testsuite/gas/arc/attr-mul64.d: Likewise.
	* testsuite/gas/arc/attr-name.d: Likewise.
	* testsuite/gas/arc/attr-name.s: Likewise.
	* testsuite/gas/arc/attr-nps400.d: Likewise.
	* testsuite/gas/arc/attr-override-mcpu.d: Likewise.
	* testsuite/gas/arc/attr-override-mcpu.s
	* testsuite/gas/arc/attr-quarkse_em.d: Likewise.
	* testsuite/gas/arc/blank.s: Likewise.
	* testsuite/gas/elf/section2.e-arc: Likewise.
	* testsuite/gas/arc/cpu-pseudop-1.d: Update test.
	* testsuite/gas/arc/cpu-pseudop-2.d: Likewise.
	* testsuite/gas/arc/nps400-0.d: Likewise.
	* testsuite/gas/elf/elf.exp: Set target_machine for ARC.
	* config/tc-arc.c (opcode/arc-attrs.h): Include.
	(ARC_GET_FLAG, ARC_SET_FLAG, streq): Define.
	(arc_attribute): Declare new function.
	(md_pseudo_table): Add arc_attribute.
	(cpu_types): Rename default cpu features.
	(selected_cpu): Set the default OSABI flag.
	(mpy_option): New variable.
	(pic_option): Likewise.
	(sda_option): Likewise.
	(tls_option): Likewise.
	(feature_type, feature_list): Remove.
	(arc_initial_eflag): Likewise.
	(attributes_set_explicitly): New variable.
	(arc_check_feature): Check also for the conflicting features.
	(arc_select_cpu): Refactor assignment of selected_cpu.eflags.
	(arc_option): Remove setting of private flags and architecture.
	(check_cpu_feature): Refactor feature names.
	(autodetect_attributes): New function.
	(assemble_tokens): Use above function.
	(md_parse_option): Refactor feature names.
	(arc_attribute): New function.
	(arc_set_attribute_int): Likewise.
	(arc_set_attribute_string): Likewise.
	(arc_stralloc): Likewise.
	(arc_set_public_attributes): Likewise.
	(arc_md_end): Likewise.
	(arc_copy_symbol_attributes): Likewise.
	(rc_convert_symbolic_attribute): Likewise.
	* config/tc-arc.h (md_end): Define.
	(CONVERT_SYMBOLIC_ATTRIBUTE): Likewise.
	(TC_COPY_SYMBOL_ATTRIBUTES): Likewise.
	* doc/c-arc.texi: Document ARC object attributes.

binutils/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* readelf.c (decode_ARC_machine_flags): Recognize OSABI v4.
	(get_arc_section_type_name): New function.
	(get_section_type_name): Use the above function.
	(display_arc_attribute): New function.
	(process_arc_specific): Likewise.
	(process_arch_specific): Handle ARC specific information.
	* testsuite/binutils-all/strip-3.d: Consider ARC.attributes
	section.

include/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf/arc.h (SHT_ARC_ATTRIBUTES): Define.
	(Tag_ARC_*): Define.
	(E_ARC_OSABI_V4): Define.
	(E_ARC_OSABI_CURRENT): Reassign it.
	(TAG_CPU_*): Define.
	* opcode/arc-attrs.h: New file.
	* opcode/arc.h (insn_subclass_t): Assign enum values.
	(insn_subclass_t): Update enum with QUARKSE1, QUARKSE2, and LL64.
	(ARC_EA, ARC_CD, ARC_LLOCK, ARC_ATOMIC, ARC_MPY, ARC_MULT)
	(ARC_NPS400, ARC_DPFP, ARC_SPFP, ARC_FPU, ARC_FPUDA, ARC_SWAP)
	(ARC_NORM, ARC_BSCAN, ARC_UIX, ARC_TSTAMP, ARC_VBFDW)
	(ARC_BARREL, ARC_DSPA, ARC_SHIFT, ARC_INTR, ARC_DIV, ARC_XMAC)
	(ARC_CRC): Delete.

bfd/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf32-arc.c (FEATURE_LIST_NAME): Define.
	(CONFLICT_LIST): Likewise.
	(opcode/arc-attrs.h): Include.
	(arc_elf_print_private_bfd_data): Print OSABI v4 flag.
	(arc_extract_features): New file.
	(arc_stralloc): Likewise.
	(arc_elf_merge_attributes): Likewise.
	(arc_elf_merge_private_bfd_data): Use object attributes.
	(bfd_arc_get_mach_from_attributes): New function.
	(arc_elf_object_p): Use object attributes.
	(arc_elf_final_write_processing): Likewise.
	(elf32_arc_obj_attrs_arg_type): New function.
	(elf32_arc_obj_attrs_handle_unknown): Likewise.
	(elf32_arc_section_from_shdr): Likewise.
	(elf_backend_obj_attrs_vendor): Define.
	(elf_backend_obj_attrs_section): Likewise.
	(elf_backend_obj_attrs_arg_type): Likewise.
	(elf_backend_obj_attrs_section_type): Likewise.
	(elf_backend_obj_attrs_handle_unknown): Likewise.
	(elf_backend_section_from_shdr): Likewise.

ld/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/ld-arc/attr-merge-0.d: New file.
	* testsuite/ld-arc/attr-merge-0.s: Likewise.
	* testsuite/ld-arc/attr-merge-0e.s: Likewise.
	* testsuite/ld-arc/attr-merge-1.d: Likewise.
	* testsuite/ld-arc/attr-merge-1.s: Likewise.
	* testsuite/ld-arc/attr-merge-1e.s: Likewise.
	* testsuite/ld-arc/attr-merge-2.d: Likewise.
	* testsuite/ld-arc/attr-merge-2.s: Likewise.
	* testsuite/ld-arc/attr-merge-3.d: Likewise.
	* testsuite/ld-arc/attr-merge-3.s: Likewise.
	* testsuite/ld-arc/attr-merge-3e.s: Likewise.
	* testsuite/ld-arc/attr-merge-4.s: Likewise.
	* testsuite/ld-arc/attr-merge-5.d: Likewise.
	* testsuite/ld-arc/attr-merge-5a.s: Likewise.
	* testsuite/ld-arc/attr-merge-5b.s: Likewise.
	* testsuite/ld-arc/attr-merge-conflict-isa.d: Likewise.
	* testsuite/ld-arc/attr-merge-err-isa.d: Likewise.
	* testsuite/ld-arc/attr-merge-incompatible-cpu.d: Likewise.
	* testsuite/ld-arc/got-01.d: Update test.
	* testsuite/ld-arc/attr-merge-err-quarkse.d: New file.
	* testsuite/ld-arc/attr-quarkse.s: Likewise.
	* testsuite/ld-arc/attr-quarkse2.s: Likewise.

opcodes/
2017-05-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (parse_option): Update quarkse_em option..
	* arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
	QUARKSE1.
	(dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
2017-05-10 14:42:22 +02:00
H.J. Lu
a91e1603af Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND.  Its sh_info field indicates the special memory
type.  GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker.  All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section.  In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value.  Each GNU_MBIND segment is
aligned at page boundary.

The assembler syntax:

    .section .mbind.foo,"adx",%progbits
                          ^             0: Special memory type.
                          |
                         'd' for SHF_GNU_MBIND.

    .section .mbind.foo,"adx",%progbits,0x1
                          ^             1: Special memory type.
                          |
                         'd' for SHF_GNU_MBIND.

    .section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
                          ^                               2: Special memory type.
                          |
                         'd' for SHF_GNU_MBIND.

bfd/

	* elf.c (get_program_header_size): Add a GNU_MBIND segment for
	each GNU_MBIND section and align GNU_MBIND section to page size.
	(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
	segment for each GNU_MBIND section.
	(_bfd_elf_init_private_section_data): Copy sh_info from input
	for GNU_MBIND section.

binutils/

	* NEWS: Mention support for ELF SHF_GNU_MBIND and
	PT_GNU_MBIND_XXX.
	* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
	(get_elf_section_flags): Handle SHF_GNU_MBIND.
	(process_section_headers): Likewise.
	* testsuite/binutils-all/mbind1.s: New file.
	* testsuite/binutils-all/objcopy.exp: Run readelf test on
	mbind1.s.

gas/

	* NEWS: Mention support for ELF SHF_GNU_MBIND.
	* config/obj-elf.c (section_match): New.
	(get_section): Match both sh_info and group name.
	(obj_elf_change_section): Add argument for sh_info.  Pass both
	sh_info and group name to get_section. Issue an error for
	SHF_GNU_MBIND section without SHF_ALLOC.  Set sh_info.
	(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
	(obj_elf_section): Support SHF_GNU_MBIND section info.
	* config/obj-elf.h (obj_elf_change_section): Add argument for
	sh_info.
	* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
	obj_elf_change_section.
	* config/tc-ia64.c (obj_elf_vms_common): Likewise.
	* config/tc-microblaze.c (microblaze_s_data): Likewise.
	(microblaze_s_sdata): Likewise.
	(microblaze_s_rdata): Likewise.
	(microblaze_s_bss): Likewise.
	* config/tc-mips.c (s_change_section): Likewise.
	* config/tc-msp430.c (msp430_profiler): Likewise.
	* config/tc-rx.c (parse_rx_section): Likewise.
	* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
	* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
	* testsuite/gas/elf/elf.exp: Run section12a, section12b and
	section13.
	* testsuite/gas/elf/section10.d: Updated.
	* testsuite/gas/elf/section10.s: Likewise.
	* testsuite/gas/elf/section12.s: New file.
	* testsuite/gas/elf/section12a.d: Likewise.
	* testsuite/gas/elf/section12b.d: Likewise.
	* testsuite/gas/elf/section13.l: Likewise.
	* testsuite/gas/elf/section13.d: Likewise.
	* testsuite/gas/elf/section13.s: Likewise.

include/

	* elf/common.h (PT_GNU_MBIND_NUM): New.
	(PT_GNU_MBIND_LO): Likewise.
	(PT_GNU_MBIND_HI): Likewise.
	(SHF_GNU_MBIND): Likewise.

ld/

	* NEWS: Mention support for ELF SHF_GNU_MBIND and
	PT_GNU_MBIND_XXX.
	* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
	input GNU_MBIND sections with the same type, attributes and
	sh_info field into a single output GNU_MBIND section.
	* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
	* testsuite/ld-elf/mbind1.s: New file.
	* testsuite/ld-elf/mbind1a.d: Likewise.
	* testsuite/ld-elf/mbind1b.d: Likewise.
	* testsuite/ld-elf/mbind1c.d: Likewise.
	* testsuite/ld-elf/mbind2a.s: Likewise.
	* testsuite/ld-elf/mbind2b.c: Likewise.
2017-04-04 09:06:04 -07:00
Palmer Dabbelt
b52920324f RISC-V: Resurrect GP-relative disassembly hints
We missed a "_gp" when changing the GP symbol.  To make sure that
doesn't happen again, we now use the same definition everywhere (thanks,
Nick).

include/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * elf/riscv.h (RISCV_GP_SYMBOL): New define.

bfd/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * elfnn-riscv.c (GP_NAME): Delete.
        (riscv_global_pointer_value): Change GP_NAME to RISCV_GP_SYMBOL.
        (_bfd_riscv_relax_lui): Likewise.

opcodes/ChangeLog:

2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>

        * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
        RISCV_GP_SYMBOL.
2017-04-04 08:29:16 -07:00
Pip Cet
f96bd6c2d7 Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils.
binutils * readelf.c: Add support for wasm32 ELF format WebAssembly files.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_none_reloc_): Likewise.
	* NEWS: Mention the new support.
	* testsuite/lib/binutils-common.exp (is_elf_format): Mark wasm32
	as ELF target.
	(supports_gnu_unique): Mark wasm32 as supporting STB_GNU_UNIQUE.
	* testsuite/binutils-all/nm.exp: Mark wasm32 as requiring .size annotations.
	* testsuite/binutils-all/wasm32: New directory.
	* testsuite/binutils-all/wasm32/create-wasm.d: New file.
	* testsuite/binutils-all/wasm32/create-wasm.s: Likewise.
	* testsuite/binutils-all/wasm32/custom-section.d: Likewise.
	* testsuite/binutils-all/wasm32/custom-section.s: Likewise.
	* testsuite/binutils-all/wasm32/invalid-wasm-1.d: Likewise.
	* testsuite/binutils-all/wasm32/invalid-wasm-1.s: Likewise.
	* testsuite/binutils-all/wasm32/long-sections.d: Likewise.
	* testsuite/binutils-all/wasm32/long-sections.s: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm.d: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm.s: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm-2.d: Likewise.
	* testsuite/binutils-all/wasm32/parse-wasm-2.s: Likewise.
	* testsuite/binutils-all/wasm32/prepared-section.d: Likewise.
	* testsuite/binutils-all/wasm32/prepared-section.s: Likewise.
	* testsuite/binutils-all/wasm32/wasm32.exp: New file, run tests.

gas	* config/tc-wasm32.h: New file: Add WebAssembly assembler target.
	* config/tc-wasm32.c: New file: Add WebAssembly assembler target.
	* Makefile.am: Add WebAssembly assembler target.
	* configure.tgt: Add WebAssembly assembler target.
	* doc/c-wasm32.texi: New file: Start documenting WebAssembly
	assembler.
	* doc/all.texi: Define WASM32.
	* doc/as.texinfo: Add WebAssembly entries.
	* NEWS: Mention the new support.
	* Makefile.in: Regenerate.
	* po/gas.pot: Regenerate.
	* po/POTFILES.in: Regenerate.
	* testsuite/gas/wasm32: New directory.
	* testsuite/gas/wasm32/allinsn.d: New file.
	* testsuite/gas/wasm32/allinsn.s: New file.
	* testsuite/gas/wasm32/illegal.l: New file.
	* testsuite/gas/wasm32/illegal.s: New file.
	* testsuite/gas/wasm32/illegal-2.l: New file.
	* testsuite/gas/wasm32/illegal-2.s: New file.
	* testsuite/gas/wasm32/illegal-3.l: New file.
	* testsuite/gas/wasm32/illegal-3.s: New file.
	* testsuite/gas/wasm32/illegal-4.l: New file.
	* testsuite/gas/wasm32/illegal-4.s: New file.
	* testsuite/gas/wasm32/illegal-5.l: New file.
	* testsuite/gas/wasm32/illegal-5.s: New file.
	* testsuite/gas/wasm32/illegal-6.l: New file.
	* testsuite/gas/wasm32/illegal-6.s: New file.
	* testsuite/gas/wasm32/illegal-7.l: New file.
	* testsuite/gas/wasm32/illegal-7.s: New file.
	* testsuite/gas/wasm32/illegal-8.l: New file.
	* testsuite/gas/wasm32/illegal-8.s: New file.
	* testsuite/gas/wasm32/illegal-9.l: New file.
	* testsuite/gas/wasm32/illegal-9.s: New file.
	* testsuite/gas/wasm32/illegal-10.l: New file.
	* testsuite/gas/wasm32/illegal-10.s: New file.
	* testsuite/gas/wasm32/illegal-11.l: New file.
	* testsuite/gas/wasm32/illegal-11.s: New file.
	* testsuite/gas/wasm32/illegal-12.l: New file.
	* testsuite/gas/wasm32/illegal-12.s: New file.
	* testsuite/gas/wasm32/illegal-13.l: New file.
	* testsuite/gas/wasm32/illegal-13.s: New file.
	* testsuite/gas/wasm32/illegal-14.l: New file.
	* testsuite/gas/wasm32/illegal-14.s: New file.
	* testsuite/gas/wasm32/illegal-15.l: New file.
	* testsuite/gas/wasm32/illegal-15.s: New file.
	* testsuite/gas/wasm32/illegal-16.l: New file.
	* testsuite/gas/wasm32/illegal-16.s: New file.
	* testsuite/gas/wasm32/illegal-17.l: New file.
	* testsuite/gas/wasm32/illegal-17.s: New file.
	* testsuite/gas/wasm32/illegal-18.l: New file.
	* testsuite/gas/wasm32/illegal-18.s: New file.
	* testsuite/gas/wasm32/illegal-19.l: New file.
	* testsuite/gas/wasm32/illegal-19.s: New file.
	* testsuite/gas/wasm32/illegal-20.l: New file.
	* testsuite/gas/wasm32/illegal-20.s: New file.
	* testsuite/gas/wasm32/illegal-21.l: New file.
	* testsuite/gas/wasm32/illegal-21.s: New file.
	* testsuite/gas/wasm32/illegal-22.l: New file.
	* testsuite/gas/wasm32/illegal-22.s: New file.
	* testsuite/gas/wasm32/illegal-24.l: New file.
	* testsuite/gas/wasm32/illegal-24.s: New file.
	* testsuite/gas/wasm32/illegal-25.l: New file.
	* testsuite/gas/wasm32/illegal-25.s: New file.
	* testsuite/gas/wasm32/reloc.d: New file.
	* testsuite/gas/wasm32/reloc.s: New file.
	* testsuite/gas/wasm32/wasm32.exp: New tests for WebAssembly
	architecture.

opcodes * configure.ac: Add (empty) bfd_wasm32_arch target.
	* configure: Regenerate
	* po/opcodes.pot: Regenerate.

include	* opcode/wasm.h: New file to support wasm32 architecture.
	* elf/wasm32.h: Add R_WASM32_32 relocation.

bfd	* elf32-wasm32.c: Add relocation code, two relocs.
	* reloc.c: Add wasm32 relocations.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
	* bfd/po/bfd.pot: Regenerate.
2017-03-30 10:57:21 +01:00
Pip Cet
8fb740dd30 Add minimal support for WebAssembly backend to the BFD library.
include * elf/wasm32.h: New file to support wasm32 architecture.

bfd * cpu-wasm32.c: New file to support wasm32 architecture.
    * elf32-wasm32.c: New file to support wasm32 architecture.
    * Makefile.am: Add wasm32 architecture.
    * archures.c: Likewise.
    * config.bfd: Likewise.
    * configure.ac: Likewise.
    * targets.c: Likewise.
2017-03-27 11:39:50 +01:00
Nick Clifton
a8be5506b6 Add support for a GNU BUILD note type to record the enum size.
include	* elf/common.h (GNU_BUILD_ATTRIBUTE_SHORT_ENUM): New GNU BUILD
	note type.

binutils * readelf.c (print_gnu_build_attribute_name): Add support for
	GNU_BUILD_ATTRIBUTE_SHORT_ENUM.
2017-03-16 16:44:55 +00:00
Nick Clifton
f955cccff3 Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AARCH64_TLSDESC_ADD_LO12_NC to R_AARCH64_TLSDESC_ADD_LO12.
PR binutils/21202
include	* elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to
	R_AARCH64_TLSDESC_LD64_LO12.
	(R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to
	R_AARCH64_TLSDESC_ADD_LO12_NC.

bfd	* reloc.c (BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC): Rename to
	BFD_RELOC_AARCH64_TLSDESC_LD64_LO12.
	(BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC): Rename to
	BFD_RELOC_AARCH64_TLSDESC_ADD_LO12.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elfnn-aarch64.c (IS_AARCH64_TLS_RELAX_RELOC): Update reloc
	names.
	(IS_AARCH64_TLSDESC_RELOC): Likewise.
	(elfNN_aarch64_howto_table): Likewise.
	(aarch64_tls_transition_without_check): Likewise.
	(aarch64_reloc_got_type): Likewise.
	(elfNN_aarch64_final_link_relocate): Likewise.
	(elfNN_aarch64_tls_relax): Likewise.
	(elfNN_aarch64_relocate_section): Likewise.
	(elfNN_aarch64_gc_sweep_hook): Likewise.
	(elfNN_aarch64_check_relocs): Likewise.
	* elfxx-aarch64.c (_bfd_aarch64_elf_put_addend): Likewise.
	(_bfd_aarch64_elf_resolve_relocation): Likewise.

gas	* config/tc-aarch64.c (reloc_table): Rename
	BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC to
	BFD_RELOC_AARCH64_TLSDESC_LD64_LO12.  Rname
	BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC to
	BFD_RELOC_AARCH64_TLSDESC_ADD_LO12.
	(md_apply_fix): Likewise.
	(aarch64_force_relocation): Likewise.
	* testsuite/gas/aarch64/tls.d: Update regexp.

ld	* testsuite/ld-aarch64/ifunc-5r-local.d: Update regexp.
2017-03-13 09:58:04 +00:00
Nick Clifton
55e22ca83a Add basic recognition of new EM_ ELF machine numbers.
include	* elf/common.h (EM_LANAI): New machine number.
	(EM_BPF): Likewise.
	(EM_WEBASSEMBLY): Likewise.
	Move low value, deprecated, numbers to their numerical
	equivalents.

binutils * readelf.c (get_machine_name): Rearrange switch table in order of
	increasing machine number.  Add missing entries.
2017-03-10 10:50:34 +00:00
H.J. Lu
1fc87489b4 Properly dump NT_GNU_PROPERTY_TYPE_0
Property type and datasz are always 4 bytes for both 32-bit and 64-bit
objects.  Property values for GNU_PROPERTY_X86_ISA_1_USED and
GNU_PROPERTY_X86_ISA_1_NEEDED are 4 bytes for both i386 and x86-64
objects.  We should also check GNU_PROPERTY_LOPROC and
GNU_PROPERTY_LOUSER.

binutils/

	PR binutils/21231
	* readelf.c (decode_x86_isa): Change argument to unsigned int.
	(print_gnu_property_note): Retrieve property type and datasz as
	4-byte integer.  Consolidate property datasz check.  Check
	GNU_PROPERTY_LOPROC and GNU_PROPERTY_LOUSER.
	* testsuite/binutils-all/i386/pr21231a.d: New file.
	* testsuite/binutils-all/i386/pr21231a.s: Likewise.
	* testsuite/binutils-all/i386/pr21231b.d: Likewise.
	* testsuite/binutils-all/i386/pr21231b.s: Likewise.
	* testsuite/binutils-all/x86-64/pr21231a.d: Likewise.
	* testsuite/binutils-all/x86-64/pr21231a.s: Likewise.
	* testsuite/binutils-all/x86-64/pr21231b.d: Likewise.
	* testsuite/binutils-all/x86-64/pr21231b.s: Likewise.

include/

	PR binutils/21231
	* elf/common.h (GNU_PROPERTY_LOPROC): New.
	(GNU_PROPERTY_HIPROC): Likewise.
	(GNU_PROPERTY_LOUSER): Likewise.
	(GNU_PROPERTY_HIUSER): Likewise.
2017-03-08 07:44:17 -08:00
Nick Clifton
9ef920e933 Add support for displaying and merging GNU_BUILD_NOTEs.
include	* elf/common.h (SHF_GNU_BUILD_NOTE): Define.
	(NT_GNU_PROPERTY_TYPE_0): Define.
	(NT_GNU_BUILD_ATTRIBUTE_OPEN): Define.
	(NT_GNU_BUILD_ATTRIBUTE_FUN): Define.
	(GNU_BUILD_ATTRIBUTE_TYPE_NUMERIC): Define.
	(GNU_BUILD_ATTRIBUTE_TYPE_STRING): Define.
	(GNU_BUILD_ATTRIBUTE_TYPE_BOOL_TRUE): Define.
	(GNU_BUILD_ATTRIBUTE_TYPE_BOOL_FALSE): Define.
	(GNU_BUILD_ATTRIBUTE_VERSION): Define.
	(GNU_BUILD_ATTRIBUTE_STACK_PROT): Define.
	(GNU_BUILD_ATTRIBUTE_RELRO): Define.
	(GNU_BUILD_ATTRIBUTE_STACK_SIZE): Define.
	(GNU_BUILD_ATTRIBUTE_TOOL): Define.
	(GNU_BUILD_ATTRIBUTE_ABI): Define.
	(GNU_BUILD_ATTRIBUTE_PIC): Define.
	(NOTE_GNU_PROPERTY_SECTION_NAME): Define.
	(GNU_BUILD_ATTRS_SECTION_NAME): Define.
	(GNU_PROPERTY_STACK_SIZE): Define.
	(GNU_PROPERTY_NO_COPY_ON_PROTECTED): Define.
	(GNU_PROPERTY_X86_ISA_1_USED): Define.
	(GNU_PROPERTY_X86_ISA_1_NEEDED): Define.
	(GNU_PROPERTY_X86_ISA_1_486): Define.
	(GNU_PROPERTY_X86_ISA_1_586): Define.
	(GNU_PROPERTY_X86_ISA_1_686): Define.
	(GNU_PROPERTY_X86_ISA_1_SSE): Define.
	(GNU_PROPERTY_X86_ISA_1_SSE2): Define.
	(GNU_PROPERTY_X86_ISA_1_SSE3): Define.
	(GNU_PROPERTY_X86_ISA_1_SSSE3): Define.
	(GNU_PROPERTY_X86_ISA_1_SSE4_1): Define.
	(GNU_PROPERTY_X86_ISA_1_SSE4_2): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX2): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512F): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512CD): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512ER): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512PF): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512VL): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512DQ): Define.
	(GNU_PROPERTY_X86_ISA_1_AVX512BW): Define.

binutils* readelf.c (get_note_type): Add support for GNU_BUILD_NOTEs.
	(get_gnu_elf_note_type): Add support for GNU_PROPERTY_NOTEs.
	(decode_x86_isa): New function.
	(print_gnu_property_note): New function.
	(print_gnu_note): Handle GNU_PROPERTY_NOTEs.
	(print_gnu_build_attribute_description): New function.
	(print_gnu_build_attribute_name): New function.
	(process_note): Add support for GNU_BUILD_NOTEs.
	* objcopy.c (--merge-notes): New command line option.
	(copy_options): Add merge-notes.
	(copy_usage): Likewise.
	(is_merge_note_section): New function.
	(merge_gnu_build_notes): New function.
	(copy_object): Merge note sections if asked to do so.
	(skip_section): Add skip_copy parameter.  Add support for skipping
	merged note sections.
	(copy_relocations_in_section): Update call to skip_section.
	(copy_section): Likewise.
	(copy_main): Add support for merge-notes option.
	* doc/binutils.texi: Document the new option to objcopy.
	* NEWS: Mention the new feature.
	* testsuite/binutils-all/note-2-32.d: New test.  Checks note
	merging on 32-bit targets.
	* testsuite/binutils-all/note-2-32.s: New test source file.
	* testsuite/binutils-all/note-2-64.d: New test.  Like note-2-32.d
	but for 64-bit targets.
	* testsuite/binutils-all/note-2-64.s: New test source file.
	* testsuite/binutils-all/objcopy.exp: Run the new test.
2017-03-01 11:09:46 +00:00
Alan Modra
7ba71655a4 PowerPC addpcis fix
This came up because I was looking at ld/tmpdir/addpcis.o and noticed
the odd addends on REL16DX_HA.  They ought to both be -4.  The error
crept in due REL16DX_HA howto being pc-relative (as indeed it should
be), and code at gas/write.c:1001 after this comment
	      /* Make it pc-relative.  If the back-end code has not
		 selected a pc-relative reloc, cancel the adjustment
		 we do later on all pc-relative relocs.  */
*not* cancelling the pc-relative adjustment.  So I've made a dummy
non-relative split reloc so that the generic code handles this, rather
than attempting to add hacks later in md_apply_fix which would not be
very robust.  Having the new internal reloc also makes it easy to
support

 addpcis rx,sym@ha

as an equivalent to

 addpcis rx,(sym-0f)@ha
0:

The patch also fixes overflow checking, which must test whether the
addi will overflow too since @l relocs don't have any overflow check.

Lastly, since I was poking at md_apply_fix, I arranged to have the
generic gas/write.c code emit errors for subtraction expressions where
we lack reloc support.

include/
	* elf/ppc64.h (R_PPC64_16DX_HA): New.  Expand fake reloc comment.
	* elf/ppc.h (R_PPC_16DX_HA): Likewise.
bfd/
	* reloc.c (BFD_RELOC_PPC_16DX_HA): New.
	* elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto.
	(ppc64_elf_reloc_type_lookup): Translate new bfd reloc.
	(ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA.
	(ppc64_elf_relocate_section): Likewise.
	* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto.
	(ppc_elf_reloc_type_lookup): Translate new bfd reloc.
	(ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
gas/
	* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
	(md_apply_fix): Remove fx_subsy check.  Move code converting to
	pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA.  Remove code
	emiiting errors on seeing fx_pcrel set on unexpected relocs, as
	that is done now by the generic code via..
	* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
	(TC_VALIDATE_FIX_SUB): Define.
ld/
	* testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at
	limits of addpcis range.
2017-02-28 11:59:47 +10:30
Alan Hayward
fae1616f5f [PATCH] Add NT_ARM_SVE
* elf/common.h (NT_ARM_SVE): Define.
2017-01-24 10:38:24 +00:00
Alan Modra
2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Dimitar Dimitrov
889294f6ff PRU BFD support
include/
	* elf/common.h: Add PRU ELF.
	* elf/pru.h: New file.
	* opcode/pru.h: New file.
	* dis-asm.h (print_insn_pru): Declare.
bfd/
	* archures.c: Add bfd_arch_pru.
	* Makefile.am: Add PRU target.
	* config.bfd: Ditto.
	* configure.ac: Ditto.
	* elf-bfd.h (enum elf_target_id): Add PRU_ELF_DATA.
	* targets.c: Add pru_elf32_vec.
	* reloc.c: Add PRU relocations.
	* cpu-pru.c: New file.
	* elf32-pru.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
	* bfd-in2.h: Regenerate
	* libbfd.h: Regenerate.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2016-12-31 12:02:09 +10:30
Andrew Waterman
2922d21da1 Re-work RISC-V gas flags: now we just support -mabi and -march
We've decided to standardize on two flags for RISC-V: "-march" sets the
target architecture (which determines which instructions can be
generated), and "-mabi" sets the target ABI.  We needed to rework this
because the old flag set didn't support soft-float or single-float ABIs,
and didn't support an x32-style ABI on RISC-V.

Additionally, we've changed the behavior of the -march flag: it's now a
lot stricter and only parses things we can actually understand.
Additionally, it's now lowercase-only: the rationale is that while the
RISC-V ISA manual specifies that ISA strings are case-insensitive, in
Linux-land things are usually case-sensitive.  Since this flag can be
used to determine library paths, we didn't want to bake some
case-insensitivity in there that would case trouble later.

This patch implements these two new flags and removes the old flags that
could conflict with these.  There wasn't a RISC-V release before, so we
want to just support a clean flag set.

include/
	* elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
	(EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
	(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
	(EF_RISCV_FLOAT_ABI_QUAD): Define.
bfd/
	* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use
	EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT.
binutils/
	* readelf.c (get_machine_flags): Use
	EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of
	EF_RISCV_{SOFT,HARD}_FLOAT.
gas/
	* config/tc-riscv.h (xlen): Delete.
	* config/tc-riscv.c (xlen): Make static.
	(abi_xlen): New variable.
	(options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC}
	with OPTION_MABI.
	(md_longopts): Likewise.
	(md_parse_option): Likewise.
	(riscv_elf_final_processing): Likewise.
	* doc/as.texinfo (Target RISC-V options): Likewise.
	* doc/c-riscv.texi (OPTIONS): Likewise.
	* config/tc-riscv.c (float_mode): Removed.
	(float_abi): New type, specifies the floating-point ABI.
	(riscv_set_abi): New function.
	(riscv_add_subset): Only allow lower-case ISA names and require
	them to start with "rv".
	(riscv_after_parse_args): Likewise.
opcodes/
	* riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
	XLEN when none is provided.
2016-12-20 12:26:34 +10:30
Andrew Waterman
45f764234a Rework RISC-V relocations
Before this commit we didn't cleanly support CFI directives because the
internal offsets used to get relaxed which broke them.  This patch
significantly reworks how we handle linker relaxations:

 * DWARF is now properly supported

 * There is a ".option norelax" to disable relaxations, for when users
   write assembly that can't be relaxed (if it's to be later patched up,
   for example).

 * There is an additional _RELAX relocation that specifies when previous
   relocations can be relaxed.

We're in the process of documenting the RISC-V ELF ABI, which will
include documentation of our relocations

  https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

but we expect that this relocation set will remain ABI compatible in the
future (ie, it's safe to release).

Thanks to Kuan-Lin Chen for figuring out how to correctly relax the
debug info!

include/
	* elf/riscv.h: Add R_RISCV_TPREL_I through R_RISCV_SET32.
bfd/
	* reloc.c (BFD_RELOC_RISCV_TPREL_I): New relocation.
	(BFD_RELOC_RISCV_TPREL_S): Likewise.
	(BFD_RELOC_RISCV_RELAX): Likewise.
	(BFD_RELOC_RISCV_CFA): Likewise.
	(BFD_RELOC_RISCV_SUB6): Likewise.
	(BFD_RELOC_RISCV_SET8): Likewise.
	(BFD_RELOC_RISCV_SET8): Likewise.
	(BFD_RELOC_RISCV_SET16): Likewise.
	(BFD_RELOC_RISCV_SET32): Likewise.
	* elfnn-riscv.c (perform_relocation): Handle the new
	relocations.
	(_bfd_riscv_relax_tls_le): Likewise.
	(_bfd_riscv_relax_align): Likewise.
	(_bfd_riscv_relax_section): Likewise.
	(howto_table): Likewise.
	(riscv_reloc_map): Likewise.
	(relax_func_t): New type.
	(_bfd_riscv_relax_call): Add reserve_size argument, which
	controls the maximal offset pessimism.  Correct type of max_alignment.
	(_bfd_riscv_relax_lui): Likewise.
	(_bfd_riscv_relax_tls_le): Likewise.
	(_bfd_riscv_relax_align): Likewise.
	(_bfd_riscv_relax_section): Compute the required reserve size
	when relocating and use it to when calling relax_func.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.
gas/
	* config/tc-riscv.c (riscv_set_options): Add relax.
	(riscv_opts): Likewise.
	(s_riscv_option): Add relax and norelax.
	(riscv_apply_const_reloc): New function.
	(append_insn): Move constant relocation handling to
	riscv_apply_const_reloc.
	(md_pcrel_from): Likewise.
	(parse_relocation): Skip BFD_RELOC_UNUSED.
	(md_pcrel_from): Handle BFD_RELOC_RISCV_SUB6,
	BFD_RELOC_RISCV_RELAX, BFD_RELOC_RISCV_CFA.
	(md_apply_fix): Likewise.
	(riscv_pre_output_hook): New function.
	* config/tc-riscv.h (md_pre_output_hook): Define.
	(riscv_pre_output_hook): Declare.
	(DWARF_CIE_DATA_ALIGNMENT): Always -4.
2016-12-20 12:26:33 +10:30
Maciej W. Rozycki
5e7fc731f8 MIPS/opcodes: Also set disassembler's ASE flags from ELF structures
Respect any ASE flags recorded in ELF file structures for the purpose of
selecting instructions to be disassembled, preventing code from being
hex-dumped even though having been clearly indicated as valid at the
assembly time.  Use date from the MIPS ABI flags structure if present,
and otherwise there may be an MDMX ASE flag set in the ELF file header.
For backwards compatibility only set extra flags and do not clear any,
preserving all previously set by the architecture selected to be
disassembled for.

	include/
	* elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
	typedef as `elf_internal_abiflags_v0'.

	bfd/
	* bfd-in.h (elf_internal_abiflags_v0): New struct declaration.
	(bfd_mips_elf_get_abiflags): New prototype.
	* elfxx-mips.c (bfd_mips_elf_get_abiflags): New function.
	* bfd-in2.h: Regenerate.

	opcodes/
	* mips-dis.c (mips_convert_abiflags_ases): New function.
	(set_default_mips_dis_options): Also infer ASE flags from ELF
	file structures.

	binutils/
	* testsuite/binutils-all/mips/mips-ase-1.d: New test.
	* testsuite/binutils-all/mips/mips-ase-2.d: New test.
	* testsuite/binutils-all/mips/mips-ase-3.d: New test.
	* testsuite/binutils-all/mips/mips-ase-1.s: New test source.
	* testsuite/binutils-all/mips/mips-ase-2.s: New test source.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.
2016-12-14 22:12:21 +00:00
Nick Clifton
e23eba971d Add support for RISC-V architecture.
bfd	* Makefile.am: Add entries for riscv32-elf and riscv64-elf.
	* config.bdf: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* archures.c: Add bfd_riscv_arch.
	* reloc.c: Add riscv relocs.
	* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
	* elfnn-riscv.c: New file.
	* elfxx-riscv.c: New file.
	* elfxx-riscv.h: New file.

binutils* readelf.c (guess_is_rela): Add EM_RISCV.
	(get_machine_name): Likewise.
	(dump_relocations): Add support for riscv relocations.
	(get_machine_flags): Add support for riscv flags.
	(is_32bit_abs_reloc): Add R_RISCV_32.
	(is_64bit_abs_reloc): Add R_RISCV_64.
	(is_none_reloc): Add R_RISCV_NONE.
	* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
	Expect the debug_ranges test to fail.

gas	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this architecture.
	* configure.in: Define a default architecture.
	* configure: Regenerate.
	* configure.tgt: Add entries for riscv.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
	* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
	* config/tc-riscv.c: New file.
	* config/tc-riscv.h: New file.
	* doc/c-riscv.texi: New file.
	* testsuite/gas/riscv: New directory.
	* testsuite/gas/riscv/riscv.exp: New file.
	* testsuite/gas/riscv/t_insns.d: New file.
	* testsuite/gas/riscv/t_insns.s: New file.

ld	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this target.
	* configure.tgt: Add riscv entries.
	* emulparams/elf32lriscv-defs.sh: New file.
	* emulparams/elf32lriscv.sh: New file.
	* emulparams/elf64lriscv-defs.sh: New file.
	* emulparams/elf64lriscv.sh: New file.
	* emultempl/riscvelf.em: New file.

opcodes	* configure.ac: Add entry for bfd_riscv_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add support for riscv.
	(disassembler_usage): Likewise.
	* riscv-dis.c: New file.
	* riscv-opc.c: New file.

include	* dis-asm.h: Add prototypes for print_insn_riscv and
	print_riscv_disassembler_options.
	* elf/riscv.h: New file.
	* opcode/riscv-opc.h: New file.
	* opcode/riscv.h: New file.
2016-11-01 16:45:57 +00:00
Nick Clifton
6d91379408 Update list of ELF machine numbers.
include	* elf/common.h (DT_SYMTAB_SHNDX): Define.
	(EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define.
	(EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define.
	(EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define.
	(EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define.
	(EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define.
	(ELFOSABI_OPENVOS): Define.
	(GRP_MASKOS, GRP_MASKPROC): Define.

binutils	* readelf.c (get_dynamic_type): Add DT_SYMTAB_SHNDX.
	(get_machine_type): Add EM_CLOUDSHIELD, EM_COREA_1ST,
	EM_COREA_2ND, EM_OPEN8, EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2,
	EM_XCORE, EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8,
	EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC, EM_CSR_KALIMBA,
	EM_Z80, EM_AMDGPU, EM_RISCV.
	(get_osabi_name): Add ELFOSABI_CLOUDABI and ELFOSABI_OPENVS.
	(get_group_flags): Update to handle flags in the
	GRP_MASKOS and GRP_MASKPROC ranges.
2016-10-17 11:46:32 +01:00
Alan Modra
005d79fd61 PowerPC .gnu.attributes
This patch extends Tag_GNU_Power_ABI_FP to cover long double ABIs,
makes the assembler warn about undefined tag values, and removes
similar warnings from the linker.  I think it is better to not
warn in the linker about undefined tag values as future extensions to
the tags then won't result in likely bogus warnings.  This is
consistent with the fact that an older linker won't warn on an
entirely new tag.

include/
	* elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment.
bfd/
	* elf-bfd.h (_bfd_elf_ppc_merge_fp_attributes): Declare.
	* elf32-ppc.c (_bfd_elf_ppc_merge_fp_attributes): New function.
	(ppc_elf_merge_obj_attributes): Use it.  Don't copy first file
	attributes, merge them.  Don't warn about undefined tag bits,
	or copy unknown values to output.
	* elf64-ppc.c (ppc64_elf_merge_private_bfd_data): Call
	_bfd_elf_ppc_merge_fp_attributes.
binutils/
	* readelf.c (display_power_gnu_attribute): Catch truncated section
	for all powerpc attributes.  Display long double ABI.  Don't
	capitalize words, except for names.  Show known bits of tag values
	when some unknown bits are present.  Whitespace fixes.
gas/
	* config/tc-ppc.c (ppc_elf_gnu_attribute): New function.
	(md_pseudo_table <ELF>): Handle "gnu_attribute".
ld/
	* testsuite/ld-powerpc/attr-gnu-4-4.s: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-14.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-24.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-34.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-41.d: Delete.
	* testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning.
	* testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output.
	* testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise.
	* testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise.
	* testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests.
2016-09-26 18:04:57 +09:30
Cupertino Miranda
a87aa054a6 Fixes to legacy ARC relocations.
Added support for ARC_SDA_12 reloc.
Fixed ARC_N32_ME.
Added ME (middle-endian) to ARC_SDA_12 reloc.

bfd/ChangeLog:

Cupertino Miranda  <cmiranda@synopsys.com>
	* reloc.c: Fixed type in ARC_SECTOFF relocations. Added ARC_SDA_12
	relocation.
	* bfd-in2.h: Regenerated from the previous changes.
	* libbfd.h: Regenerated from the previous changes.

include/ChangeLog:

Cupertino Miranda  <cmiranda@synopsys.com>
	* elf/arc-reloc.def: Fixed relocation formula for N*, SDA, SDA_12,
	SDA_16_LD*, S13_PCREL, N32_ME, SECTOFF_* relocations.
	* opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12 relocation.
2016-08-26 12:09:17 +02:00
Thomas Preud'homme
4ba2ef8fbe 2016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
	* elf32-arm.c (CMSE_PREFIX): Define macro.
	(elf32_arm_stub_cmse_branch_thumb_only): Define stub sequence.
	(cmse_branch_thumb_only): Declare stub.
	(struct elf32_arm_link_hash_table): Define cmse_stub_sec field.
	(elf32_arm_get_plt_info): Add globals parameter.  Use it to return
	FALSE if there is no PLT.
	(arm_type_of_stub): Adapt to new elf32_arm_get_plt_info signature.
	(elf32_arm_final_link_relocate): Likewise.
	(elf32_arm_gc_sweep_hook): Likewise.
	(elf32_arm_gc_mark_extra_sections): Mark sections holding ARMv8-M
	secure entry functions.
	(arm_stub_is_thumb): Add case for arm_stub_cmse_branch_thumb_only.
	(arm_dedicated_stub_output_section_required): Change to a switch case
	and add a case for arm_stub_cmse_branch_thumb_only.
	(arm_dedicated_stub_output_section_required_alignment): Likewise.
	(arm_stub_dedicated_output_section_name): Likewise.
	(arm_stub_dedicated_input_section_ptr): Likewise and remove
	ATTRIBUTE_UNUSED for htab parameter.
	(arm_stub_required_alignment): Likewise.
	(arm_stub_sym_claimed): Likewise.
	(arm_dedicated_stub_section_padding): Likewise.
	(cmse_scan): New function.
	(elf32_arm_size_stubs): Call cmse_scan for ARM M profile targets.
	Set stub_changed to TRUE if such veneers were created.
	(elf32_arm_swap_symbol_in): Add detection code for CMSE special
	symbols.

include/
	* arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro.
	(ARM_SET_SYM_CMSE_SPCL): Likewise.

ld/
	* ld.texinfo (Placement of SG veneers): New concept entry.
	* testsuite/ld-arm/arm-elf.exp
	(Secure gateway veneers: no .gnu.sgstubs section): New test.
	(Secure gateway veneers: wrong entry functions): Likewise.
	(Secure gateway veneers (ARMv8-M Baseline)): Likewise.
	(Secure gateway veneers (ARMv8-M Mainline)): Likewise.
	* testsuite/ld-arm/cmse-veneers.s: New file.
	* testsuite/ld-arm/cmse-veneers.d: Likewise.
	* testsuite/ld-arm/cmse-veneers.rd: Likewise.
	* testsuite/ld-arm/cmse-veneers.sd: Likewise.
	* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out: Likewise.
	* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out: Likewise.
2016-08-04 15:36:52 +01:00
Claudiu Zissulescu
fa1c017017 [ARC] Fix/improve small data support.
The R_ARC_SDA32 is wrongly described as a ME relocation, fix it.  Offset the
__SDATA_BEGIN__ to take advantage of the signed 9-bit field of the
load/store instructions.

include/
2016-07-08  Claudiu Zissulescu  <claziss@synopsys.com>

	* elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation.

ld/
2016-07-08  Claudiu Zissulescu  <claziss@synopsys.com>

	* emulparams/arcelf.sh (SDATA_START_SYMBOLS): Add offset.
	* testsuite/ld-arc/sda-relocs.dd: New file.
	* testsuite/ld-arc/sda-relocs.ld: Likewise.
	* testsuite/ld-arc/sda-relocs.rd: Likewise.
	* testsuite/ld-arc/sda-relocs.s: Likewise.
	* testsuite/ld-arc/arc.exp: Add SDA tests.
2016-07-14 10:08:57 +02:00
Cupertino Miranda
08759e0fc8 Fixes done to TLS.
TLS relocations did not support multiple TLS modes for the same
symbol in a single object file.
Refactored how GOT and TLS is implemented. Removed code duplications between
local and global symbols conditioning.

bfd/ChangeLog:

2016-06-14  Cupertino Miranda  <cmiranda@synopsys.com>
  * arc-got.h: Moved got related structures from elf32-arc.c to
    this file. More precisely, tls_type_e, tls_got_entries, got_entry.
  * (arc_get_local_got_ents,
     got_entry_for_type,
     new_got_entry_to_list,
     tls_type_for_reloc,
     symbol_has_entry_of_type,
     get_got_entry_list_for_symbol,
     arc_got_entry_type_for_reloc,
     ADD_SYMBOL_REF_SEC_AND_RELOC,
     arc_fill_got_info_for_reloc,
     relocate_fix_got_relocs_for_got_info,
     create_got_dynrelocs_for_single_entry,
     create_got_dynrelocs_for_got_info): Added to file.
  * elf32-arc.c: Removed GOT & TLS related structs and functions to
                     arc-got.h.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-07-11 15:24:35 +02:00
Andre Vieria
f0728ee368 [ARM] Change noread to purecode.
bfd/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * bfd-in2.h (SEC_ELF_NOREAD): Rename to ...
          (SEC_ELF_PURECODE): ... this.
        * elf32-arm.c (elf32_arm_post_process_headers): Rename SEC_ELF_NOREAD
          to SEC_ELF_NOREAD.
          (elf32_arm_fake_sections): Likewise.
          (elf_32_arm_section_flags): Likewise.
          (elf_32_arm_lookup_section_flags): Likewise.
        * section.c (SEC_ELF_NOREAD): Rename to ...
          (SEC_ELF_PURECODE): ... this.

binutils/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * objdump.c (dump_section_header): Rename SEC_ELF_NOREAD
          to SEC_ELF_NOREAD.
        * readelf.c (get_elf_section_flags): Rename ARM_NOREAD to
          ARM_PURECODE and SHF_ARM_NOREAD to SHF_ARM_PURECODE.
          (process_section_headers): Rename noread to purecode.

        * section.c (SEC_ELF_NOREAD): Rename to ...
          (SEC_ELF_PURECODE): ... this.

include/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * elf/arm.h (SHF_ARM_NOREAD): Rename to ...
          (SHF_ARM_PURECODE): ... this.

ld/ChangeLog
2016-07-05  Andre Vieria  <andre.simoesdiasvieira@arm.com>

        * testsuite/ld-arm/arm_noread.ld: Renamed to ...
          testsuite/ld-arm/arm_purecode.ld: ... this, and replaced
          all noread's by purecode.
2016-07-05 11:28:46 +01:00
Maciej W. Rozycki
c9775dde32 MIPS16: Add R_MIPS16_PC16_S1 branch relocation support
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1'
and the usual MIPS16 bit shuffling applies to relocated field handling,
as per the encoding of the branch target in the extended form of the
MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions.

	include/
	* elf/mips.h (R_MIPS16_PC16_S1): New relocation.

	bfd/
	* elf32-mips.c (elf_mips16_howto_table_rel): Add
	R_MIPS16_PC16_S1.
	(mips16_reloc_map): Likewise.
	* elf64-mips.c (mips16_elf64_howto_table_rel): Likewise.
	(mips16_elf64_howto_table_rela): Likewise.
	(mips16_reloc_map): Likewise.
	* elfn32-mips.c (elf_mips16_howto_table_rel): Likewise.
	(elf_mips16_howto_table_rela): Likewise.
	(mips16_reloc_map): Likewise.
	* elfxx-mips.c (mips16_branch_reloc_p): New function.
	(mips16_reloc_p): Handle R_MIPS16_PC16_S1.
	(b_reloc_p): Likewise.
	(mips_elf_calculate_relocation): Likewise.
	(_bfd_mips_elf_check_relocs): Likewise.
	* reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

	gas/
	* config/tc-mips.c (mips16_reloc_p): Handle
	BFD_RELOC_MIPS16_16_PCREL_S1.
	(b_reloc_p): Likewise.
	(limited_pcrel_reloc_p): Likewise.
	(md_pcrel_from): Likewise.
	(md_apply_fix): Likewise.
	(tc_gen_reloc): Likewise.
	(md_convert_frag): Likewise.
	(mips_fix_adjustable): Update comment.
	* testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-addend-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-addend-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-absolute.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file.
	* testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-2.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-3.l: Remove file.
	* testsuite/gas/mips/mips16-branch-absolute.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-2.s: Add padding.
	* testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid
	implicit instruction padding, avoid MIPS16 JR->JRC conversion.
	* testsuite/gas/mips/branch-weak-6.d: New test.
	* testsuite/gas/mips/branch-weak-7.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/mips16-branch-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-3.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test.
	* testsuite/ld-mips-elf/mips16-branch.s: New test source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-28 01:29:56 +01:00
Trevor Saunders
7c2c4aa12f xtensa: prototype xtensa_make_property_section in elf/xtensa.h
There's no reason to have multiple prototypes for the same function.

include/ChangeLog:

2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* elf/xtensa.h (xtensa_make_property_section): New prototype.

gas/ChangeLog:

2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-xtensa.c (xtensa_make_property_section): Remove prototype.

bfd/ChangeLog:

2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* elf32-xtensa.c (xtensa_make_property_section): Remove prototype.
2016-06-25 11:50:33 -04:00
John Baldwin
b00f86d072 Add constants for FreeBSD-specific auxiliary vector entry types.
include/ChangeLog:

	* elf/common.h (AT_FREEBSD_EXECPATH, AT_FREEBSD_CANARY)
	(AT_FREEBSD_CANARYLEN, AT_FREEBSD_OSRELDATE, AT_FREEBSD_NCPUS)
	(AT_FREEBSD_PAGESIZES, AT_FREEBSD_PAGESIZESLEN)
	(AT_FREEBSD_TIMEKEEP, AT_FREEBSD_STACKPROT): Define.
2016-06-24 10:30:45 -07:00
Trevor Saunders
6b4778968b addmore extern C
opcodes/ChangeLog:

2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* arc-ext.h: Wrap in extern C.

include/ChangeLog:

2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* elf/dlx.h: Wrap in extern C.
	* elf/xtensa.h: Likewise.
	* opcode/arc.h: Likewise.
2016-06-22 12:59:58 -04:00
Graham Markall
bdd582dbf1 Arc assembler: Convert nps400 from a machine type to an extension.
gas	* config/tc-arc.c (check_cpu_feature, md_parse_option):
	Add nps400 option and feature. Add check for nps400
	feature. Refactor existing checks to check subclass before
	feature enablement.
	(md_show_usage): Document flags for NPS-400 and add some other
	undocumented flags.
	(cpu_type): Remove nps400 CPU type entry
	(check_zol): Remove bfd_mach_arc_nps400 case.
	(md_show_usage): Add help on -mcpu=nps400.
	(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
	set.
	* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
	-fpuda flags.  Document -mcpu=nps400.
	* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
	expected flags to match ARC700 instead of NPS400.
	* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
	* testsuite/gas/arc/nps-400-2.d: Likewise.
	* testsuite/gas/arc/nps-400-3.d: Likewise.
	* testsuite/gas/arc/nps-400-4.d: Likewise.
	* testsuite/gas/arc/nps-400-5.d: Likewise.
	* testsuite/gas/arc/nps-400-6.d: Likewise.
	* testsuite/gas/arc/nps-400-7.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
	avoid clash with cbba instruction.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
	-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.

binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
	case.

ld	* testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
	* testsuite/ld-arc/nps-1b.d: Likewise.

include	* opcode/arc.h: Add nps400 extension and instruction
	subclass.
	Remove ARC_OPCODE_NPS400
	* elf/arc.h: Remove E_ARC_MACH_NPS400

opcodes	* arc-dis.c (arc_insn_length): Add comment on instruction length.
	Use same method for determining	instruction length on ARC700 and
	NPS-400.
	(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
	* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
	with the NPS400 subclass.
	* arc-opc.c: Likewise.

bfd	* archures.c: Remove bfd_mach_arc_nps400.
	* bfd-in2.h: Likewise.
	* cpu-arc.c (arch_info_struct): Likewise.
	* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
	Likewise.
2016-06-21 14:03:08 +01:00
Alan Modra
14b57c7c6a PowerPC VLE
VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE.  For
example
{"evaddw",  VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe.  Also, we don't check
user assembly against the processor type as well as we could.

Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31.  Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.

This patch fixes those problems in the opcode table, and removes
PPCNONE.  I find a plain 0 distracts less from other values.

In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects.  It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.

include/
	* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
	PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
	PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
	PPC_APUINFO_VLE: Define.
opcodes/
	* ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
	cpu for "vle" to e500.
	* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
	(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
	(PPCNONE): Delete, substitute throughout.
	(powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
	except for major opcode 4 and 31.
	(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
	* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
	to match other 32-bit archs.
	* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
	(ppc_elf_object_p): Call it.
	(ppc_elf_special_sections): Use APUINFO_SECTION_NAME.  Fix
	overlong line.
	(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
	* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
	* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
	_bfd_elf_ppc_at_tprel_transform): Move to..
	* elf-bfd.h: ..here.
	(_bfd_elf_ppc_set_arch): Declare.
	* bfd-in2.h: Regenerate.
gas/
	* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
	PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
	PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
	(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
	by vle_opcodes, and that vle flag doesn't enable opcodes.  Don't
	add vle_opcodes twice.
	(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
	* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
	* testsuite/ld-powerpc/apuinfo-vle2.s: New.
	* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
2016-06-07 22:04:38 +09:30
Trevor Saunders
1fe0971e41 add more extern C
opcodes/ChangeLog:

2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* nds32-asm.h: Add extern "C".
	* sh-opc.h: Likewise.

bfd/ChangeLog:

2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* elf32-hppa.h: Add extern "C".
	* elf32-nds32.h: Likewise.
	* elf32-tic6x.h: Likewise.

include/ChangeLog:

2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* elf/mips.h: Likewise.
	* elf/sh.h: Likewise.
	* opcode/d10v.h: Likewise.
	* opcode/d30v.h: Likewise.
	* opcode/ia64.h: Likewise.
	* opcode/mips.h: Likewise.
	* opcode/ppc.h: Likewise.
	* opcode/sparc.h: Likewise.
	* opcode/tic6x.h: Likewise.
	* opcode/v850.h: Likewise.
2016-06-01 21:26:32 -04:00
Matthew Fortune
8f4f9071ad Add MIPS32 DSPr3 support.
bfd/

	* elfxx-mips.c (print_mips_ases): Add DSPR3.

binutils/

	* readelf.c (print_mips_ases): Add DSPR3.

gas/

	* config/tc-mips.c (options): Add OPTION_DSPR3 and
	OPTION_NO_DSPR3.
	(md_longopts): Likewise.
	(md_show_usage): Add help for -mdspr3 and -mno-dspr3.
	(mips_ases): Define availability for DSPr3.
	(mips_ase_groups): Add ASE_DSPR3 to the DSP group.
	(mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3.
	* doc/as.texinfo: Document -mdspr3, -mno-dspr3.  Fix -mdspr2
	formatting.
	* doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and
	.set nodspr3.  Fix -mdspr2 formatting.
	* testsuite/gas/mips/mips32-dspr3.d: New file.
	* testsuite/gas/mips/mips32-dspr3.s: Likewise.
	* testsuite/gas/mips/mips.exp: Run mips32-dspr3 test.

include/

	* elf/mips.h (AFL_ASE_DSPR3): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
	* opcode/mips.h (ASE_DSPR3): New macro.

opcodes/

	* mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
	mips64r6.
	* mips-opc.c (D34): New macro.
	(mips_builtin_opcodes): Define bposge32c for DSPr3.
2016-05-11 17:06:13 +01:00
Thomas Preud'homme
39d911fc3c Use getters/setters to access ARM branch type
2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
	* elf32-arm.c (elf32_arm_size_stubs): Use new macros
	ARM_GET_SYM_BRANCH_TYPE and ARM_SET_SYM_BRANCH_TYPE to respectively get
	and set branch type of a symbol.
	(bfd_elf32_arm_process_before_allocation): Likewise.
	(elf32_arm_relocate_section): Likewise and fix identation along the
	way.
	(allocate_dynrelocs_for_symbol): Likewise.
	(elf32_arm_finish_dynamic_symbol): Likewise.
	(elf32_arm_swap_symbol_in): Likewise.
	(elf32_arm_swap_symbol_out): Likewise.

gas/
	* config/tc-arm.c (arm_adjust_symtab): Use ARM_SET_SYM_BRANCH_TYPE to
	set branch type of a symbol.

gdb/
	* arm-tdep.c (arm_elf_make_msymbol_special): Use
	ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.

include/
	* arm.h (enum arm_st_branch_type): Add new ST_BRANCH_ENUM_SIZE
	enumerator.
	(NUM_ENUM_ARM_ST_BRANCH_TYPE_BITS): New macro.
	(ENUM_ARM_ST_BRANCH_TYPE_BITMASK): Likewise.
	(ARM_SYM_BRANCH_TYPE): Replace by ...
	(ARM_GET_SYM_BRANCH_TYPE): This and ...
	(ARM_SET_SYM_BRANCH_TYPE): This in two versions depending on whether
	BFD_ASSERT is defined or not.

ld/
	* emultempl/armelf.em (gld${EMULATION_NAME}_finish): Use
	ARM_GET_SYM_BRANCH_TYPE to get branch type of a symbol.

opcodes/
	* arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
	branch type of a symbol.
	(print_insn): Likewise.
2016-05-10 16:17:04 +01:00