Unlike in 64-bit mode, where values wrap at the 64-bit boundary anyway,
there's no wrapping at the 32-bit boundary here, and hence overflow
detection shouldn't be suppressed just because rela relocations are
going to be used.
The extra check against NO_RELOC is actually a result of an ilp32 test
otherwise failing. But thinking about it, reporting overflows for
not-really-relocations (typically because of earlier errors) makes
little sense in general. Perhaps this should even be extended to non-
64-bit modes.
PR 28791
* config/tc-z80.c (emit_data_val): Do not warn about overlarge
constants generated by bit manipulation operators.
* testsuite/gas/z80/pr28791.s: New test source file.
* testsuite/gas/z80/pr28791.d: New test driver file.
The change in read_a_source_file prevents the particular testcase in
the PR from triggering the assertion in demand_empty_rest_of_line.
I've also removed the assertion. Nothing much goes wrong with gas if
something else triggers it, so it's not worthy of an abort.
I've also changed my previous patch to ignore_rest_of_line to allow
that function to increment input_line_pointer past buffer_limit, like
demand_empty_rest_of_line: The two functions ought to behave the
same in that respect. Finally, demand_empty_rest_of_line gets a
little hardening to prevent accesses past buffer_limit plus one.
PR 28979
* read.c (read_a_source_file): Calculate known size for sbuf
rather than calling strlen.
(demand_empty_rest_of_line): Remove "know" check. Expand comment.
Don't dereference input_line_pointer when past buffer_limit.
(ignore_rest_of_line): Allow input_line_pointer to increment to
buffer_limit plus one. Expand comment.
The dwarf2_emit_insn() can create debuginfo of line. But it is called
too late in append_fixp_and_insn. It causes extra offs when debuginfo
of line sets address.
gas/config/
* tc-loongarch.c
Replace the magic numbers in gas(tc-loongarch.c) and
bfd(elfnn-loongarch.c) with the functions defined in
the howto table(elfxx-loongarch.c).
gas/
* config/tc-loongarch.c: use functions.
bfd/
* elfnn-loongarch.c: use functions.
* elfxx-loongarch.c: define functions.
* elfxx-loongarch.h
By slightly relaxing the checking in operand_type_register_match() we
can fold the vector shift insns with an XMM source as well. While
strictly speaking an overlap in just one size (see the code comment) is
not enough (both operands could have multiple sizes with just a single
common one), this is good enough for all templates we have, or which
could sensibly / usefully appear (within the scope of the present
operand matching model).
Tightening this a little would be possible, but would require broadcast
related information to be passed into the function.
To avoid a completely useless fuzzing ubsan "bug" report, I decided to
make logical_input_line unsigned.
* input-scrub.c (logical_input_line): Make unsigned.
(struct input_save): Here too.
(input_scrub_reinit, input_scrub_close, bump_line_counters),
(as_where): Adjust to suit.
operand() is not a place that should be calling ignore_rest_of_line.
ignore_rest_of_line shouldn't increment input_line_pointer if already
at buffer limit.
* expr.c (operand): Don't call ignore_rest_of_line.
* read.c (s_mri_common): Likewise.
(ignore_rest_of_line): Don't increment input_line_pointer if
already at buffer_limit.
The -march= intentions are quite clear: A base architecture may be
followed by any number of extensions. Accepting a base architecture in
place of an extension will at best result in confusion, as the first of
the two (or more) items specified simply would not take effect, due to
being overridden by the later one(s).
Now that {L,K}1OM support is gone, and with it the brokenness in
check_cpu_arch_compatible(), put in place a test making sure that only
extensions can be enabled via .arch for IAMCU, and that the base
architecture cannot be changed.
The checks done by check_cpu_arch_compatible() were halfway sensible
only at the time where only L1OM support was there. The purpose,
however, has always been to prevent bad uses of .arch (turning off the
base CPU "feature" flag) while at the same time permitting extensions to
be enabled / disabled. In order to achieve this (and to prevent
regressions when L1OM and K1OM support are removed)
- set CpuIAMCU in CPU_IAMCU_FLAGS,
- adjust the IAMCU check in the function itself (the other two similarly
broken checks aren't adjusted as they're slated to be removed anyway),
- avoid calling the function for extentions (which would never have the
base "feature" flag set),
- add a new testcase actually exercising ".arch iamcu" (which would also
regress with the planned removal).
Let's hope this stays dead, but it's here as a patch separate from
those that removed use of powerpc_macros just in case it needs to be
resurrected.
include/
* opcode/ppc.h (struct powerpc_macro): Delete declaration.
(powerpc_macros, powerpc_num_macros): Likewise..
opcodes/
* ppc-opc.c (powerpc_macros, powerpc_num_macros): Delete.
gas/
* config/tc-ppc.c (ppc_macro): Delete function.
(ppc_macro_hash): Delete.
(ppc_setup_opcodes, md_assemble): Delete macro support.
This moves VLE insn out of the macro table. "e_slwi" and "e_srwi"
already exist in vle_opcodes as distinct instructions rather than
encodings of e_rlwinm.
opcodes/
* ppc-opc.c (vle_opcodes): Typo fix e_rlwinm operand.
Add "e_inslwi", "e_insrwi", "e_rotlwi", "e_rotrwi", "e_clrlwi",
"e_clrrwi", "e_extlwi", "e_extrwi", and "e_clrlslwi".
(powerpc_macros): Delete same. Delete "e_slwi" and "e_srwi" too.
gas/
* testsuite/gas/ppc/vle-simple-5.d: Update.
The extended instructions implemented in powerpc_macros aren't used by
the disassembler. That means instructions like "sldi r3,r3,2" appear
in disassembly as "rldicr r3,r3,2,61", which is annoying since many
other extended instructions are shown.
Note that some of the instructions moved out of the macro table to the
opcode table won't appear in disassembly, because they are aliases
rather than a subset of the underlying raw instruction. If enabled,
rotrdi, extrdi, extldi, clrlsldi, and insrdi would replace all
occurrences of rotldi, rldicl, rldicr, rldic and rldimi. (Or many
occurrences in the case of clrlsldi if n <= b was added to the extract
functions.)
The patch also fixes a small bug in opcode sanity checking.
include/
* opcode/ppc.h (PPC_OPSHIFT_SH6): Define.
opcodes/
* ppc-opc.c (insert_erdn, extract_erdn, insert_eldn, extract_eldn),
(insert_crdn, extract_crdn, insert_rrdn, extract_rrdn),
(insert_sldn, extract_sldn, insert_srdn, extract_srdn),
(insert_erdb, extract_erdb, insert_csldn, extract_csldb),
(insert_irdb, extract_irdn): New functions.
(ELDn, ERDn, ERDn, RRDn, SRDn, ERDb, CSLDn, CSLDb, IRDn, IRDb):
Define and add associated powerpc_operands entries.
(powerpc_opcodes): Add "rotrdi", "srdi", "extrdi", "clrrdi",
"sldi", "extldi", "clrlsldi", "insrdi" and corresponding record
(ie. dot suffix) forms.
(powerpc_macros): Delete same from here.
gas/
* config/tc-ppc.c (insn_validate): Don't modify value passed
to operand->insert for PPC_OPERAND_PLUS1 when calculating mask.
Handle PPC_OPSHIFT_SH6.
* testsuite/gas/ppc/prefix-reloc.d: Update.
* testsuite/gas/ppc/simpshft.d: Update.
ld/
* testsuite/ld-powerpc/elfv2so.d: Update.
* testsuite/ld-powerpc/notoc.d: Update.
* testsuite/ld-powerpc/notoc3.d: Update.
* testsuite/ld-powerpc/tlsdesc2.d: Update.
* testsuite/ld-powerpc/tlsget.d: Update.
* testsuite/ld-powerpc/tlsget2.d: Update.
* testsuite/ld-powerpc/tlsopt5.d: Update.
* testsuite/ld-powerpc/tlsopt6.d: Update.
The idea here is to replace expressions like v + 1 + 1 + 1 with v + 3.
* dwarf2dbg.c (set_or_check_view): Remove useless assertion.
Resolve multiple view increments.
* testsuite/gas/elf/dwarf2-18.d: Don't xfail mep.
* symbol.c (struct symbol_flags): Add forward_resolved.
(symbol_entry_find): Update needle initialisation.
(symbol_clone_if_forward_ref): Do no work when forward_resolved
is already set. Set forward_resolved.
Presently in this case, due to an undefined behavior shift, at least
with x86 cross builds I'm observing:
Error: value conflicts with instruction length `8,0x0000003f'
Eliminate the UB and extend the respective testcase.
Currently we report errors as "unrecognized opcode `fence.i'" when the
opcode isn't part of the selected extensions.
This patch expands that error message to include the missing extension
information. For example, now the error message would be "unrecognized
opcode `fence.i', extension `zifencei' required".
If the opcode is not a part of any extension, the error message reverts
to "unrecognized opcode `<op statement>'".
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
bfd/
pr 28733
* elfxx-riscv.c (riscv_multi_subset_supports_ext): New function,
used to return the extension string for each INSN_CLASS_*.
* elfxx-riscv.h: Added extern riscv_multi_subset_supports_ext.
gas/
pr 28733
* config/tc-riscv.c (struct riscv_ip_error): New structure,
contains information about errors that occur within the riscv_ip.
(riscv_ip): Use struct riscv_ip_error to report more detailed errors.
* testsuite/gas/riscv/c-fld-fsd-fail.l: Updated.
* testsuite/gas/riscv/march-imply-i2p1-01.: Likewise.
Currently we report errors as "invalid CSR 'fscr' for the current ISA"
when the instruction isn't valid.
This patch expands that error message to include the missing extension
information. For example, now the error message would be "invalid CSR
'fscr' for the current ISA, CSR 'fscr' needs 'f' extension".
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
gas/
pr 28733
* config/tc-riscv.c (riscv_csr_address): Report more details
when the CSR is invalid.
* testsuite/gas/riscv/csr-version-1p10.l: Updated detailed errors.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
Commit b25f942e18 made .machine more strict. Weaken it again.
* config/tc-ppc.c (ppc_machine): Treat an early .machine specially,
keeping sticky options to work around gcc bugs.
* Removed N extension CSRs,
ustatus, uie, utvec, uscratch, uepc, ucause, utval and uip.
* Removed two supervisor CSRs,
sedeleg and sideleg.
* Changed debug CSR address of scontext from 0x7aa to 0x5a8. We cannot support
different versions of debug specs for now, so only supporting the latest one is
the only way to move forward.
* Added debug CSRs,
mscontext (0x7aa), mcontrol6 (0x7a1, tdata1) and tmexttrigger ((0x7a1, tdata1).
* Regarded hcontext as a debug CSR.
include/
* opcode/riscv-opc.h: Updated CSRs to privileged spec v1.12 and
debug spec v1.0.
gas/
* testsuite/gas/riscv/csr.s: Updated CSRs to privileged spec v1.12
and debug spec v1.0.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Likewise.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
This commit reorganizes and adds some CSRs to csr-dw-regnums.[sd] to
make it test the same CSRs as csr.s.
gas/ChangeLog:
* testsuite/gas/riscv/csr-dw-regnums.s: Reorganize and add
defined CSRs tested in csr.s.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
Much of the gas source and older BFD source use "long" for function
parameters and variables, when other types would be more appropriate.
This patch fixes one of those cases. Dollar labels and numeric local
labels do not need large numbers. Small positive itegers are usually
all that is required. Due to allowing longs, it was possible for
fb_label_name and dollar_label_name to overflow their buffers.
* symbols.c: Delete unnecessary forward declarations.
(dollar_labels, dollar_label_instances): Use unsigned int.
(dollar_label_defined, dollar_label_instance): Likewise.
(define_dollar_label): Likewise.
(fb_low_counter, fb_labels, fb_label_instances): Likewise.
(fb_label_instance_inc, fb_label_instance): Likewise.
(fb_label_count, fb_label_max): Make them size_t.
(dollar_label_name, fb_label_name): Rewrite using sprintf.
* symbols.h (dollar_label_defined): Update prototype.
(define_dollar_label, dollar_label_name): Likewise.
(fb_label_instance_inc, fb_label_name): Likewise.
* config/bfin-lex.l (yylex): Remove unnecessary casts.
* expr.c (integer_constant): Likewise.
* read.c (read_a_source_file): Limit numeric label range to int.
There are quite a few ubsan warnings in gas. This one disappears with
a code tidy.
* read.c (s_app_line): Rename 'l' to 'linenum'. Avoid ubsan
warning.
This was needed when gas was using the automake cygnus option, but
this was removed years ago by Simon in d0ac1c4488
("Bump to autoconf 2.69 and automake 1.15.1"). So delete it here.
The info pages are already & still installed by default w/out it.
PR 28793:
The alignment may be removed in linker. We need to create new frag after
alignment to prevent the assembler from computing static offsets.
gas/
* config/tc-riscv.c (riscv_frag_align_code): Create new frag.
