* config/tc-mips.c (mips_ip): Unconditionally parse an expression
for 'A' and assume that the constant has been elided if the result
is an O_register.
gas/testsuite/
* gas/mips/la.s, gas/mips/la.d, gas/mips/la-svr4pic.d,
gas/mips/la-xgot.d: Add tests for bracketed addresses.
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
Rename to...
(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
(M_USD_AB): ...these.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
and SD A(B) macros up.
* micromips-opc.c (micromips_opcodes): Likewise.
gas/
* config/tc-mips.c (gprel16_reloc_p): New function.
(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
BFD_RELOC_UNUSED.
(offset_high_part, small_offset_p): New functions.
(nacro): Use them. Remove *_OB and *_DOB cases. For single-
register load and store macros, handle the 16-bit offset case first.
If a 16-bit offset is not suitable for the instruction we're
generating, load it into the temporary register using
ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the
M_L_DAB code once the address has been constructed. For double load
and store macros, again handle the 16-bit offset case first.
If the second register cannot be accessed from the same high
part as the first, load it into AT using ADDRESS_ADDI_INSN.
Fix the handling of LD in cases where the first register is the
same as the base. Also handle the case where the offset is
not 16 bits and the second register cannot be accessed from the
same high part as the first. For unaligned loads and stores,
fuse the offbits == 12 and old "ab" handling. Apply this handling
whenever the second offset needs a different high part from the first.
Construct the offset using ADDRESS_ADDI_INSN where possible,
for offbits == 16 as well as offbits == 12. Use offset_reloc
when constructing the individual loads and stores.
(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
and offset_reloc before matching against a particular opcode.
Handle elided 'A' constants. Allow 'A' constants to use
relocation operators.
gas/testsuite/
* gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for
truncated constants.
* gas/mips/ldstla-32-shared.d: Likewise.
* gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding
16-bit constants to the base.
* gas/mips/micromips@mcu.d: Likewise.
* gas/mips/micromips@cache.d: Likewise.
* gas/mips/micromips@pref.d: Likewise.
* gas/mips/micromips.d, gas/mips/micromips-insn32.d,
gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise.
Allow the full 16-bit offset range to be used for SB, LB and LBU in
USH and ULH sequences. Fix the expected output for LD and SD when
the two LW and SW offsets need different high parts.
* gas/mips/eva.s: Test PREFE with relocation operators.
* gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit
constants. Update after eva.s change.
* gas/mips/micromips@eva.d: Likewise.
* gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s,
gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d,
gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s,
gas/mips/ulh-reloc.d: New tests.
* gas/mips/mips.exp: Run them.
* mips.h: Remove documentation of "[" and "]". Update documentation
of "k" and the MDMX formats.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
MDMX-like instructions.
* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
printing "Q" operands for INSN_5400 instructions.
gas/
* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
(mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
gas/testsuite/
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test.
* gas/mips/mips.exp: Run it.
* mips.h: Update documentation of "+s" and "+S".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
"+S" for "cins".
* mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
Combine cases.
gas/
* config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
Require the msb to be <= 31 for "+s". Check that the size is <= 31
for both "+s" and "+S".
* mips.h: Document "+i".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
"jalx".
* mips16-opc.c (mips16_opcodes): Likewise.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_mips16_insn_arg)
(print_insn_mips16): Handle "+i".
(print_insn_micromips): Likewise. Conditionally preserve the
ISA bit for "a" but not for "+i".
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
(mips_ip, mips16_ip): Handle "+i".
* mips.h: Remove documentation of "+D" and "+T".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
and "+T" handling. Check for a "0" suffix when deciding whether to
use coprocessor 0 names. In that case, also check for ",H" selectors.
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
(mips_ip): Remove "+D" and "+T" handling.
gas/testsuite/
* gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names
for LWC0 and SWC0.
ARM uses @ as a comment character, but % seems to be usable by all
existing ifunc enabled architectures.
gdb/testsuite/ChangeLog:
2013-07-05 Will Newton <will.newton@linaro.org>
* gdb.base/gnu-ifunc-lib.c: Use %function instead of @function
in asm syntax to allow building on ARM.
bfd/
* elf32-s390.c: Rewrite GOT accesses using larl if possible.
* elf64-s390.c: Likewise.
ld/testsuite/
* ld-s390/gotreloc-1.s: New file.
* ld-s390/gotreloc-1.ver: New file.
* ld-s390/gotreloc_31-1.dd: New file.
* ld-s390/gotreloc_64-1.dd: New file.
* ld-s390/s390.exp: Run the new tests. Run 31 bit tests also on 64
bit.
opcodes/
* s390-opc.c (J12_12, J24_24): New macros.
(INSTR_MII_UPI): Rename to INSTR_MII_UPP.
(MASK_MII_UPI): Rename to MASK_MII_UPP.
* s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
include/elf/
* s390.h: Add new relocs R_390_PC12DBL, R_390_PLT12DBL,
R_390_PC24DBL, and R_390_PLT24DBL.
gas/testsuite/
* gas/s390/zarch-zEC12.s: Change bprp second operand and add
variants requiring relocations.
* gas/s390/zarch-zEC12.d: Likewise.
gas/
* config/tc-s390.c (md_gather_operands, md_apply_fix): Support new
relocs.
bfd/
* elf32-s390.c: Add new relocation definitions R_390_PC12DBL,
R_390_PLT12DBL, R_390_PC24DBL, and R_390_PLT24DBL.
(elf_s390_reloc_type_lookup, elf_s390_check_relocs)
(elf_s390_gc_sweep_hook, elf_s390_relocate_section): Support new
relocations.
* elf64-s390.c: See elf32-s390.c
* bfd-in2.h: Add new relocs to enum bfd_reloc_code_real.
* libbfd.h: Add new reloc strings.
Allocate the value as optimized out from the start rather than allocating
a value with contents, and then marking it optimized out.
gdb/
2013-07-04 Pedro Alves <palves@redhat.com>
* findvar.c (value_of_register): Use allocate_optimized_out_value
if the register has been optimized out, instead of
set_value_optimized_out.
* frame-unwind.c (frame_unwind_got_optimized): Use
allocate_optimized_out_value.
Doing something else, I factored out the bits of the value_bits_valid
function that actually handle the check_validity hook, and
surprisingly found out that the result was misbehaving. Turns out
value_bits_valid has a latent bug. If the value is not lval_computed,
or doesn't have a check_validity hook, then we should assume the value
is entirely valid, not invalid. This is currently masked by the
value->optimized_out check -- I ran the testsuite with a gdb_assert(0)
inserted in place of that return being touched by the patch, and it
never triggers.
Tested on x86_64 Fedora 17.
gdb/
2013-07-04 Pedro Alves <palves@redhat.com>
* value.c (value_bits_valid): If the value is not lval_computed,
or doesn't have a check_validity hook, assume the value is entirely
valid.
gdb/ChangeLog
* stack.c (read_frame_arg): No longer fetch lazy values.
* value.c (value_optimized_out): If the value is not already
marked optimized out, and is lazy then fetch it.
(value_primitive_field): Move optimized out check to later in the
function, after we have loaded any lazy values.
(value_fetch_lazy): Use optimized out flag directly rather than
calling optimized_out method.
gdb/testsuite/ChangeLog
* gdb.dwarf2/dw2-reg-undefined.exp: New file.
* gdb.dwarf2/dw2-reg-undefined.c: Likewise.
* gdb.dwarf2/dw2-reg-undefined.S: Likewise.
* valops.c: Don't include "user-regs.h".
(value_fetch_lazy): Moved to value.c.
* value.c: Include "user-regs.h".
(value_fetch_lazy): Moved from valops.c.
2013-07-04 Yao Qi <yao@codesourcery.com>
Revert:
2013-06-27 Yao Qi <yao@codesourcery.com>
* common/create-version.sh: Update comments. Handle the case
that TARGET_ALIAS is empty.
gdb/gdbserver/
2013-07-04 Yao Qi <yao@codesourcery.com>
* Makefile.in (host_alias): Use @host_noncanonical@.
(target_alias): Use @target_noncanonical@.
* configure.ac: Use ACX_NONCANONICAL_TARGET and
ACX_NONCANONICAL_HOST.
* configure: Regenerated.
Revert:
2013-06-28 Mircea Gherzan <mircea.gherzan@intel.com>
* configure.ac (version_host, version_target): Set and AC_SUBST them.
* configure: Rebuild.
* Makefile.in (version_host, version_target): Get from configure.
(version.c): Use $(version_host) and $(version_target).
This factors --enable-libmcheck related bits from GDB's configure.ac
and makes GDBserver use them too. Specifically, the 'development'
global is moved to a separate script to it can be sourced by both GDB
and GDBserver, and the --enable-libmcheck/--disable-libmcheck bits
proper are moved to a new m4 file.
I started out by defining 'development' in the m4 file, but in the end
decided against it, as a separate script has the advantage that
changing it in release branches does not require regenerating
configure, unlike today.
I had also started out by making the new GDB_AC_LIBMCHECK itself
handle the yes/no default fallback depending on release/developement,
but since I had split out 'development' to a separate script, and, GDB
needs the python checks anyway (hence we'd need to do the python
checks in gdb's configure.ac, and pass in a 'default lmcheck yes/no'
parameter to GDB_AC_LIBMCHECK anyway), I ended up keeping
GDB_AC_LIBMCHECK isolated from the 'development' global. IOW, it's
the caller's business to handle it.
Tested on x86_64 Fedora 17. Built GDB and GDBserver with and without
--enable-libmcheck, and observed --enable-libmcheck overrides the
disablement of -lmcheck caused by python supporting threads, and that
GDBserver links with -lmcheck when expected. Also observed that
changing the 'development' global, and issuing "make" triggers a
relink, and '-lmcheck' is included or not from the link accordingly.
gdb/
2013-07-03 Pedro Alves <palves@redhat.com>
* Makefile.in (config.status): Depend on development.sh.
(aclocal_m4_deps): Add libmcheck.m4.
* acinclude.m4: Include libmcheck.m4.
* configure.ac: Source development.sh instead of setting
'development' here. --enable-libmcheck/--disable-libmcheck code
factored out to GDB_AC_LIBMCHECK. Run it.
* development.sh: New file.
* libmcheck.m4: New file.
* configure: Regenerate.
gdb/gdbserver/
2013-07-03 Pedro Alves <palves@redhat.com>
* Makefile.in (config.status): Depend on development.sh.
* acinclude.m4: Include libmcheck.m4.
* configure: Regenerate.
* elf64-ppc.c (struct ppc_stub_hash_entry): Delete "addend".
(ppc64_elf_size_stubs): Don't set "addend".
(ppc64_elf_relocate_section): Don't allow calls via
toc-adjusting stubs without a following nop even in an
executable, except for self-calls and both libc_start_main
and .libc_start_main.
gold/
* powerpc.cc (Target_powerpc::Relocate::relocate): Update self-call
comment.
The documentation refers to "target nrom", but this target doesn't
appear in the tree. It was zapped here:
2002-12-16 Andrew Cagney <ac131313@redhat.com>
[...]
* remote-nrom.c, remote-os9k.c, remote-vx960.c: Delete.
This patch removes the reference from the documentation.
* gdb.texinfo (Target Commands): Don't mention "target nrom".
2013-06-25 Mircea Gherzan <mircea.gherzan@intel.com>
gdbserver/
* notif.h (notif_event): Add a dummy member to avoid compiler
errors.
Change-Id: I490dbdb70a24f52b3947371f7c0397bf7a18423c
Signed-off-by: Mircea Gherzan <mircea.gherzan@intel.com>
