To better reflect what the testcase is about, and to make room for a
different testcase.
gdb/testsuite/ChangeLog:
2017-03-07 Pedro Alves <palves@redhat.com>
* gdb.base/tui-layout.c: Rename to ...
* gdb.base/tui-disasm-long-lines.c: ... this.
* gdb.base/tui-layout.exp: Rename to ...
* gdb.base/tui-disasm-long-lines.exp: ... this.
This patch initializes the BND registers before executing the inferior
call. BND registers can be in arbitrary values at the moment of the
inferior call. In case the function being called uses as part of the
parameters BND register, e.g. when passing a pointer as parameter, the
current value of the register will be used. This can cause boundary
violations that are not due to a real bug or even desired by the user.
In this sense the best to be done is set the BND registers to allow
access to the whole memory, i.e. initialized state, before pushing the
inferior call.
2017-03-07 Walfred Tedeschi <walfred.tedeschi@intel.com>
gdb/ChangeLog:
* i387-tdep.h (i387_reset_bnd_regs): Add function definition.
* i387-tdep.c (i387_reset_bnd_regs): Add function implementation.
* i386-tdep.c (i386_push_dummy_call): Call i387_reset_bnd_regs.
* amd64-tdep (amd64_push_dummy_call): Call i387_reset_bnd_regs.
gdb/testsuite/ChangeLog:
* i386-mpx-call.c: New file.
* i386-mpx-call.exp: New file.
gdb/doc/ChangeLog:
* Memory Protection Extensions: Add information about inferior
calls.
lang_assignment_statement serves both assignments and asserts.
* ldlang.c (open_input_bfds): Check that lang_assignment_statement
is not an assert before referencing defsym.
ppc64_elf_relocate_section lacked a check which meant that it emitted
dynamic relocs against a hidden undefweak symbol for which no dynamic
relocs had been allocated.
PR 21224
PR 20519
* elf64-ppc.c (ppc64_elf_relocate_section): Add missing
dyn_relocs check.
Assembler displays upper case hex numbers and we need to force a good
alignment to avoid matching NOPs at the end.
* testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment.
* testsuite/gas/i386/x86-64-mpx-inval-2.l: Expect [0-9A-F]+.
* readelf.c (print_gnu_build_attribute_name): Read byte values
from the name string as unsigned bytes.
(process_notes_at): Use memcpy to copy an unterminated name
string.
Certain insns have restrictions on fields. For example, the insn
mentioned in the PR, lqarx, must specify an even general purpose
register as its destination and that register cannot appear in
either of the base or index reg fields. This holds even when the RA0
field is 0 (meaning a zero rather than r0).
PR 21124
* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
(extract_raq, extract_ras, extract_rbx): New functions.
(powerpc_operands): Use opposite corresponding insert function.
(Q_MASK): Define.
(powerpc_opcodes): Apply Q_MASK to all quad insns with even
register restriction.
Add asserts that reloc size matches encoding size, and tidy.
* dw2gencfi.c (encoding_size): Return unsigned int.
(emit_expr_encoded): Assert size matches reloc bitsize.
(output_fde): Use unsigned for offset_size and addr_size. Set
addr_size earlier and use in place of constant 4 and uses of
DWARF2_FDE_RELOC_SIZE. Assert it matches reloc bitsize.
Putting the name, comp_dir and producer strings in the .debug_str section
makes it possible to share them across CUs. This saves a small amount of
space (about ~20K on a glibc libc.so.6 build with debuginfo). And makes
it easier for tools like rpm debugedit to adjust the source paths when
generating separate debuginfo files.
gas/
* dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_strp instead of
DW_FORM_string for DW_AT_name, DW_AT_comp_dir and DW_AT_producer.
(out_debug_info): Accept symbols to name, comp_dir and producer
in the .debug_str section and emit those offsets not full strings.
(out_debug_str): New function that outputs the strings for name,
comp_dir and producer in .debug_str and generates symbols to
those strings.
(out_debug_line): Create a .debug_str section if necessary and
call out_debug_str before calling out_debug_info.
* testsuite/gas/aarch64/dwarf.d: Add extra section symbol to
expected output.
sim/aarch64/
* simulator.c (mul64hi): Shift carry left by 32.
(smulh): Change signum to negate. If negate, invert result, and add
carry bit if low part of multiply result is zero.
sim/testsuite/sim/aarch64/
* sumov.s: Correct compare test values.
* sumulh.s: New.
As reported in PR 21165,
(gdb) info locals^M
gv = /home/yao/SourceCode/gnu/gdb/git/gdb/value.c:372: internal-error: int value_bits_any_optimized_out(const value*, int, int): Assertion `!value->lazy' failed.^M
A problem internal to GDB has been detected,^M
further debugging may prove unreliable.^M
Quit this debugging session? (y or n) FAIL: gdb.ada/info_locals_renaming.exp: info locals (GDB internal error)
Resyncing due to internal error.
This internal error is caused by e8b24d9 (Remove parameter valaddr from
la_val_print). Commit e8b24d9 removes some calls to
value_contents_for_printing, but value_fetch_lazy is not called, so the
internal error above is triggered. This patch adds value_fetch_lazy
call before val_print.
gdb:
2017-03-03 Yao Qi <yao.qi@linaro.org>
PR gdb/21165
* ada-valprint.c (ada_val_print_ref): Call value_fetch_lazy if
value is lazy.
* valprint.c (common_val_print): Likewise.
Fix a commit 6afe8e98a6 ("internal error for backwards .org"),
<https://www.sourceware.org/ml/binutils/2008-06/msg00212.html>,
GAS regression that caused legitimate code to fail assembly with an
"attempt to move .org backwards" error.
For example with the `mips-linux' target we get:
$ cat org.s
.set mips16
la $2, foo
.org 0x1000
.align 2
foo:
.half 0
$ as -o org.o org.s
org.s: Assembler messages:
org.s:3: Error: attempt to move .org backwards
$
where the location pointer is obviously not moved backwards with `.org'.
The cause is positive `stretch' in relaxation due to a PC-relative ADDIU
instruction (produced from the LA macro used) getting expanded from 2 to
4 bytes as `foo' is noticed to be out of range for the short encoding.
This in turn triggers logic in `relax_segment' which concludes in the
processing of an `rs_org' frag produced that the location pointer is
moved backwards while in fact only the amount to space forward to the
location requested has shrunk, resulting in a negative growth of the
frag.
Correct the bad logic then and instead verify that the fixed part of an
`rs_org' frag has not overrun the location requested, as per the comment
already included with the error message:
/* Growth may be negative, but variable part of frag
cannot have fewer than 0 chars. That is, we can't
.org backwards. */
which accurately describes the regression scenario. Move the comment
ahead the conditional noted, for clarity.
Add generic and MIPS test cases for the `.org' pseudo-op, including the
test case discussed though not integrated with the offending commit in
particular, adjusted to work across all targets.
gas/
* write.c (relax_segment) <rs_org>: Only bail out if the fixed
part of the frag has overrun the location requested.
* testsuite/gas/all/org-1.d: New test.
* testsuite/gas/all/org-2.d: New test.
* testsuite/gas/all/org-3.d: New test.
* testsuite/gas/all/org-4.d: New test.
* testsuite/gas/all/org-5.d: New test.
* testsuite/gas/all/org-6.d: New test.
* testsuite/gas/all/org-1.l: New stderr output.
* testsuite/gas/all/org-2.l: New stderr output.
* testsuite/gas/all/org-3.l: New stderr output.
* testsuite/gas/all/org-1.s: New test source.
* testsuite/gas/all/org-2.s: New test source.
* testsuite/gas/all/org-3.s: New test source.
* testsuite/gas/all/org-4.s: New test source.
* testsuite/gas/all/org-5.s: New test source.
* testsuite/gas/all/org-6.s: New test source.
* testsuite/gas/all/gas.exp: Run the new tests.
* testsuite/gas/mips/org-1.d: New test.
* testsuite/gas/mips/org-2.d: New test.
* testsuite/gas/mips/org-3.d: New test.
* testsuite/gas/mips/org-4.d: New test.
* testsuite/gas/mips/org-5.d: New test.
* testsuite/gas/mips/org-6.d: New test.
* testsuite/gas/mips/org-7.d: New test.
* testsuite/gas/mips/org-8.d: New test.
* testsuite/gas/mips/org-9.d: New test.
* testsuite/gas/mips/org-10.d: New test.
* testsuite/gas/mips/org-11.d: New test.
* testsuite/gas/mips/org-12.d: New test.
* testsuite/gas/mips/org-1.l: New stderr output.
* testsuite/gas/mips/org-4.l: New stderr output.
* testsuite/gas/mips/org-5.l: New stderr output.
* testsuite/gas/mips/org-6.l: New stderr output.
* testsuite/gas/mips/org-10.l: New stderr output.
* testsuite/gas/mips/org-1.s: New test source.
* testsuite/gas/mips/org-2.s: New test source.
* testsuite/gas/mips/org-3.s: New test source.
* testsuite/gas/mips/org-4.s: New test source.
* testsuite/gas/mips/org-5.s: New test source.
* testsuite/gas/mips/org-6.s: New test source.
* testsuite/gas/mips/org-7.s: New test source.
* testsuite/gas/mips/org-8.s: New test source.
* testsuite/gas/mips/org-9.s: New test source.
* testsuite/gas/mips/org-10.s: New test source.
* testsuite/gas/mips/org-11.s: New test source.
* testsuite/gas/mips/org-12.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
This commit adds support to GDB so that it can modify the disassembler-options
value that is passed to the disassembler, similar to objdump's -M option.
Currently, the only supported targets are ARM, PowerPC and S/390, but
adding support for a new target(s) is not difficult.
include/
* dis-asm.h (disasm_options_t): New typedef.
(parse_arm_disassembler_option): Remove prototype.
(set_arm_regname_option): Likewise.
(get_arm_regnames): Likewise.
(get_arm_regname_num_options): Likewise.
(disassemble_init_s390): New prototype.
(disassembler_options_powerpc): Likewise.
(disassembler_options_arm): Likewise.
(disassembler_options_s390): Likewise.
(remove_whitespace_and_extra_commas): Likewise.
(disassembler_options_cmp): Likewise.
(next_disassembler_option): New inline function.
(FOR_EACH_DISASSEMBLER_OPTION): New macro.
opcodes/
* disassemble.c Include "safe-ctype.h".
(disassemble_init_for_target): Handle s390 init.
(remove_whitespace_and_extra_commas): New function.
(disassembler_options_cmp): Likewise.
* arm-dis.c: Include "libiberty.h".
(NUM_ELEM): Delete.
(regnames): Use long disassembler style names.
Add force-thumb and no-force-thumb options.
(NUM_ARM_REGNAMES): Rename from this...
(NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
(get_arm_regname_num_options): Delete.
(set_arm_regname_option): Likewise.
(get_arm_regnames): Likewise.
(parse_disassembler_options): Likewise.
(parse_arm_disassembler_option): Rename from this...
(parse_arm_disassembler_options): ...to this. Make static.
Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
(print_insn): Use parse_arm_disassembler_options.
(disassembler_options_arm): New function.
(print_arm_disassembler_options): Handle updated regnames.
* ppc-dis.c: Include "libiberty.h".
(ppc_opts): Add "32" and "64" entries.
(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
(powerpc_init_dialect): Add break to switch statement.
Use new FOR_EACH_DISASSEMBLER_OPTION macro.
(disassembler_options_powerpc): New function.
(print_ppc_disassembler_options): Use ARRAY_SIZE.
Remove printing of "32" and "64".
* s390-dis.c: Include "libiberty.h".
(init_flag): Remove unneeded variable.
(struct s390_options_t): New structure type.
(options): New structure.
(init_disasm): Rename from this...
(disassemble_init_s390): ...to this. Add initializations for
current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
(print_insn_s390): Delete call to init_disasm.
(disassembler_options_s390): New function.
(print_s390_disassembler_options): Print using information from
struct 'options'.
* po/opcodes.pot: Regenerate.
binutils/
* objdump.c (main): Use remove_whitespace_and_extra_commas.
gdb/
* NEWS: Mention new set/show disassembler-options commands.
* doc/gdb.texinfo: Document new set/show disassembler-options commands.
* disasm.c: Include "arch-utils.h", "gdbcmd.h" and "safe-ctype.h".
(prospective_options): New static variable.
(gdb_disassembler::gdb_disassembler): Initialize
m_di.disassembler_options.
(gdb_buffered_insn_length_init_dis): Initilize di->disassembler_options.
(get_disassembler_options): New function.
(set_disassembler_options): Likewise.
(set_disassembler_options_sfunc): Likewise.
(show_disassembler_options_sfunc): Likewise.
(disassembler_options_completer): Likewise.
(_initialize_disasm): Likewise.
* disasm.h (get_disassembler_options): New prototype.
(set_disassembler_options): Likewise.
* gdbarch.sh (gdbarch_disassembler_options): New variable.
(gdbarch_verify_disassembler_options): Likewise.
* gdbarch.c: Regenerate.
* gdbarch.h: Likewise.
* arm-tdep.c (num_disassembly_options): Delete.
(set_disassembly_style): Likewise.
(arm_disassembler_options): New static variable.
(set_disassembly_style_sfunc): Convert short style name into long
option name. Call set_disassembler_options.
(show_disassembly_style_sfunc): New function.
(arm_gdbarch_init): Call set_gdbarch_disassembler_options and
set_gdbarch_verify_disassembler_options.
(_initialize_arm_tdep): Delete regnames variable and update callers.
(arm_disassembler_options): Initialize.
(disasm_options): New variable.
(num_disassembly_options): Rename from this...
(num_disassembly_styles): ...to this. Compute by scanning through
disasm_options.
(valid_disassembly_styles): Initialize using disasm_options.
Remove calls to parse_arm_disassembler_option, get_arm_regnames and
set_arm_regname_option.
Pass show_disassembly_style_sfunc to the "disassembler" setshow command.
* rs6000-tdep.c (powerpc_disassembler_options): New static variable.
(rs6000_gdbarch_init): Call set_gdbarch_disassembler_options and
set_gdbarch_verify_disassembler_options.
* s390-tdep.c (s390_disassembler_options): New static variable.
(s390_gdbarch_init):all set_gdbarch_disassembler_options and
set_gdbarch_verify_disassembler_options.
gdb/testsuite/
* gdb.arch/powerpc-power.exp: Delete test.
* gdb.arch/powerpc-power.s: Likewise.
* gdb.disasm/disassembler-options.exp: New test.
* gdb.arch/powerpc-altivec.exp: Likewise.
* gdb.arch/powerpc-altivec.s: Likewise.
* gdb.arch/powerpc-altivec2.exp: Likewise.
* gdb.arch/powerpc-altivec2.s: Likewise.
* gdb.arch/powerpc-altivec3.exp: Likewise.
* gdb.arch/powerpc-altivec3.s: Likewise.
* gdb.arch/powerpc-power7.exp: Likewise.
* gdb.arch/powerpc-power7.s: Likewise.
* gdb.arch/powerpc-power8.exp: Likewise.
* gdb.arch/powerpc-power8.s: Likewise.
* gdb.arch/powerpc-power9.exp: Likewise.
* gdb.arch/powerpc-power9.s: Likewise.
* gdb.arch/powerpc-vsx.exp: Likewise.
* gdb.arch/powerpc-vsx.s: Likewise.
* gdb.arch/powerpc-vsx2.exp: Likewise.
* gdb.arch/powerpc-vsx2.s: Likewise.
* gdb.arch/powerpc-vsx3.exp: Likewise.
* gdb.arch/powerpc-vsx3.s: Likewise.
* gdb.arch/arm-disassembler-options.exp: Likewise.
* gdb.arch/powerpc-disassembler-options.exp: Likewise.
* gdb.arch/s390-disassembler-options.exp: Likewise.
In the last patch I said "The patch also fixes overflow checking".
In fact, there wasn't anything wrong with the previous code. So,
revert that change. The new checks are OK too, so this is just a
tidy.
* elf64-ppc.c (ppc64_elf_ha_reloc): Revert last change.
(ppc64_elf_relocate_section): Likewise.
Just like REX.W affects operand size of the implicit rAX/rDX inputs to
PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on
the instructions.
Similarly the disassembler needs to be adjusted to no longer require
VEX.W to be zero for the instructions to be valid, and to emit proper
suffixes.
Note, however, that this doesn't address the problem of there being no
way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it
address the problem of the many WIG instructions not getting properly
disassembled when VEX.W=1.
A number of places in elf32-nios.c created dynamic sections but didn't
set the hash table dynobj. That meant we could have duplicate dynamic
sections connected to a number of bfds, so size_dynamic_sections
didn't properly discard or allocate contents.
Also, the entire set of dynamic sections was created in check_relocs
on seeing GOT relocs, when only .got related sections are needed,
probably done to hide segfaults later in finish_dynamic_sections.
The patch fixes these issues and makes the assembler emit errors when
nios2 lacks the necessary pc-relative relocs for subtraction
expressions, rather than silently generating bad code.
eg. ld-elf/merge. I've also tidied uses of elf32_nios2_hash_table and
elf_hash_table.
bfd/
PR 20995
* elf32-nios2.c (nios2_elf32_relocate_section): Use htab
rather than elf32_nios2_hash_table or elf_hash_table.
(create_got_section): Likewise.
(nios2_elf32_finish_dynamic_symbol): Likewise.
(nios2_elf32_adjust_dynamic_symbol): Likewise.
(nios2_elf32_size_dynamic_sections): Likewise.
(nios2_elf32_check_relocs): Delete dynobj, sgot, and srelgot
vars. Use htab equivalents directly instead. Don't create
all dynamic sections on needing just the GOT. Use a goto
rather than a fall-through with reloc test. Ensure
htab->dynobj is set when making dynamic sreloc section.
(nios2_elf32_finish_dynamic_sections): Delete dynobj, use htab
equivalent directly instead. Don't segfault on looking for
.dynamic when dynamic sections have not been created. Don't
segfault on .got.plt being discarded.
(nios2_elf32_size_dynamic_sections): Delete plt and got vars.
Don't set "relocs" on .rela.plt. Do handle .sbss. Delete
fixme and another not so relevant comment.
(nios2_elf_add_symbol_hook): Delete dynobj var. If not
already set, set hash table dynobj on creating .sbss.
gas/
* config/tc-nios2.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
ld/
* testsuite/ld-elf/merge.d: xfail for nios.
This came up because I was looking at ld/tmpdir/addpcis.o and noticed
the odd addends on REL16DX_HA. They ought to both be -4. The error
crept in due REL16DX_HA howto being pc-relative (as indeed it should
be), and code at gas/write.c:1001 after this comment
/* Make it pc-relative. If the back-end code has not
selected a pc-relative reloc, cancel the adjustment
we do later on all pc-relative relocs. */
*not* cancelling the pc-relative adjustment. So I've made a dummy
non-relative split reloc so that the generic code handles this, rather
than attempting to add hacks later in md_apply_fix which would not be
very robust. Having the new internal reloc also makes it easy to
support
addpcis rx,sym@ha
as an equivalent to
addpcis rx,(sym-0f)@ha
0:
The patch also fixes overflow checking, which must test whether the
addi will overflow too since @l relocs don't have any overflow check.
Lastly, since I was poking at md_apply_fix, I arranged to have the
generic gas/write.c code emit errors for subtraction expressions where
we lack reloc support.
include/
* elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment.
* elf/ppc.h (R_PPC_16DX_HA): Likewise.
bfd/
* reloc.c (BFD_RELOC_PPC_16DX_HA): New.
* elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto.
(ppc64_elf_reloc_type_lookup): Translate new bfd reloc.
(ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA.
(ppc64_elf_relocate_section): Likewise.
* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto.
(ppc_elf_reloc_type_lookup): Translate new bfd reloc.
(ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
(md_apply_fix): Remove fx_subsy check. Move code converting to
pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code
emiiting errors on seeing fx_pcrel set on unexpected relocs, as
that is done now by the generic code via..
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
(TC_VALIDATE_FIX_SUB): Define.
ld/
* testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at
limits of addpcis range.
I'd made this dynamic section read-only so a flag test distinguished
it from .dynbss, but like any other .data.rel.ro section it really
should be marked read-write. (It is read-only after relocation, not
before.) When using the standard linker scripts this usually doesn't
matter since the output section is among other read-write sections and
not page aligned. However, it might matter in the extraordinary case
of the dynamic section being the only .data.rel.ro section with the
output section just happening to be page aligned and a multiple of a
page in size. In that case the output section would be read-only, and
live it its own read-only PT_LOAD segment, which is incorrect.
* elflink.c (_bfd_elf_create_dynamic_sections): Don't make
dynamic .data.rel.ro read-only.
* elf32-arm.c (elf32_arm_finish_dynamic_symbol): Compare section
rather than section flags when deciding where copy reloc goes.
* elf32-cris.c (elf_cris_finish_dynamic_symbol): Likewise.
* elf32-hppa.c (elf32_hppa_finish_dynamic_symbol): Likewise.
* elf32-i386.c (elf_i386_finish_dynamic_symbol): Likewise.
* elf32-metag.c (elf_metag_finish_dynamic_symbol): Likewise.
* elf32-microblaze.c (microblaze_elf_finish_dynamic_symbol): Likewise.
* elf32-nios2.c (nios2_elf32_finish_dynamic_symbol): Likewise.
* elf32-or1k.c (or1k_elf_finish_dynamic_symbol): Likewise.
* elf32-ppc.c (ppc_elf_finish_dynamic_symbol): Likewise.
* elf32-s390.c (elf_s390_finish_dynamic_symbol): Likewise.
* elf32-tic6x.c (elf32_tic6x_finish_dynamic_symbol): Likewise.
* elf32-tilepro.c (tilepro_elf_finish_dynamic_symbol): Likewise.
* elf64-ppc.c (ppc64_elf_finish_dynamic_symbol): Likewise.
* elf64-s390.c (elf_s390_finish_dynamic_symbol): Likewise.
* elf64-x86-64.c (elf_x86_64_finish_dynamic_symbol): Likewise.
* elfnn-aarch64.c (elfNN_aarch64_finish_dynamic_symbol): Likewise.
* elfnn-riscv.c (riscv_elf_finish_dynamic_symbol): Likewise.
* elfxx-mips.c (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_finish_dynamic_symbol): Likewise.
* elfxx-tilegx.c (tilegx_elf_finish_dynamic_symbol): Likewise.
Interpret the `jalr $0, $25' instruction encoding with an R_MIPS_JALR
relocation attached as an alias to `jr $25' and convert the jump to an
equivalent branch where possible, consequently covering the MIPSr6
architecture for the purpose of this optimization too.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Also handle the
`jalr $0, $25' instruction encoding.
gas/
* testsuite/gas/mips/jalr4.s: Add `jalr $0, $25' instructions.
* testsuite/gas/mips/jalr4.d: Adjust accordingly. Remove MIPSr6
encoding patterns.
* testsuite/gas/mips/jalr4-n64.d: Likewise.
* testsuite/gas/mips/mipsr6@jalr4.d: New test.
* testsuite/gas/mips/mipsr6@jalr4-n32.d: New test.
* testsuite/gas/mips/mipsr6@jalr4-n64.d: New test.
ld/
* testsuite/ld-mips-elf/jalr4.dd: Adjust for `jalr $0, $25'
instructions.
* testsuite/ld-mips-elf/jalr4-r6.dd: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
