Update ia64 ELF backend to set DF_TEXTREL for dynamic relocs against
readonly sections like other backends.
* elfnn-ia64.c (elfNN_ia64_link_hash_table): Remove reltext.
(allocate_dynrel_entries): Set DF_TEXTREL instead of reltext.
(elfNN_ia64_size_dynamic_sections): Check DF_TEXTREL instead
of reltext.
* testsuite/ld-elf/linux-x86.exp: Build tests when non-native.
(check_pr25749b): Add optional args. Set expected pass file
from args. Run -1b and -2a tests with passall.out.
* testsuite/ld-elf/passall.out: New file.
* testsuite/ld-elf/pr25749-1.c: Adjust to pass with older glibc.
* testsuite/ld-elf/pr25749-2.c: Likewise.
* testsuite/lib/ld-lib.exp (run_ld_link_exec_tests): Use
regexp_diff to compare expected output from running binary.
Currently the .gdb_index is not enabled for ada executables (PR24713).
Fix this by adding the required support in write_psymbols, similar to how that
is done for .debug_names in debug_names::insert.
Tested on x86_64-linux, with native and target board cc-with-gdb-index.
gdb/ChangeLog:
2020-06-10 Tom de Vries <tdevries@suse.de>
PR ada/24713
* dwarf2/index-write.c (struct mapped_symtab): Add m_string_obstack.
(write_psymbols): Enable .gdb_index for ada.
* dwarf2/read.c: Remove comment stating .gdb_index is unsupported for
ada.
gdb/testsuite/ChangeLog:
2020-06-10 Tom de Vries <tdevries@suse.de>
* gdb.ada/ptype_union.exp: Remove PR24713 workaround.
In commit 9a0bacfb08 "[gdb/symtab] Handle .gdb_index in ada language mode", a
missing part of dw2_map_matching_symbols was added, containing a call to
dw2_expand_symtabs_matching_symbol.
However, the callback passed to that call has one problem: the callback has an
argument "offset_type namei", which is ignored. Instead, match_name is passed
as argument to dw2_symtab_iter_init, where a name lookup is done, which may or
may not yield the same value as namei.
Fix this by creating a new version of dw2_symtab_iter_init that takes a
"offset_type namei" argument instead of "const char *name", and passing namei.
Tested on x86_64-linux, with native and target board cc-with-gdb-index.
gdb/ChangeLog:
2020-06-10 Tom de Vries <tdevries@suse.de>
* dwarf2/read.c (dw2_symtab_iter_init_common): Factor out of ...
(dw2_symtab_iter_init): ... here. Add variant with "offset_type
namei" instead of "const char *name" argument.
(dw2_map_matching_symbols): Use "offset_type namei" variant of
dw2_symtab_iter_init.
Fix:
DUPLICATE: gdb.base/index-cache.exp: test_cache_disabled: no files were created
DUPLICATE: gdb.base/index-cache.exp: test_cache_disabled: check index-cache stats
We use `proc_with_prefix` for test_cache_disabled, but we call it twice. So we
need an additional prefix to identify the specific call. This patch adds that.
gdb/testsuite/ChangeLog:
* gdb.base/index-cache.exp (test_cache_disabled): Add test_prefix
parameter, update callers.
Change-Id: Idf382fd380c77a654e8a7aa236af50b65c96b1d2
Add ifunc_resolvers to elf_link_hash_table and use it for both x86 and
ppc64. Before glibc commit b5c45e837, DT_TEXTREL is incompatible with
IFUNC resolvers. Set ifunc_resolvers if there are IFUNC resolvers and
issue a warning for IFUNC resolvers with DT_TEXTREL.
bfd/
PR ld/18801
* elf-bfd.h (elf_link_hash_table): Add ifunc_resolvers.
(_bfd_elf_allocate_ifunc_dyn_relocs): Remove the
bfd_boolean * argument. Set ifunc_resolvers if there are IFUNC
resolvers.
* elf-ifunc.c (_bfd_elf_allocate_ifunc_dyn_relocs): Updated.
Set ifunc_resolvers if there are FUNC resolvers.
* elf64-ppc.c (ppc_link_hash_table): Remove local_ifunc_resolver.
(build_global_entry_stubs_and_plt): Replace local_ifunc_resolver
with elf.ifunc_resolvers.
(write_plt_relocs_for_local_syms): Likewise.
(ppc64_elf_relocate_section): Likewise.
(ppc64_elf_finish_dynamic_sections): Likewise.
* elfnn-aarch64.c (elfNN_aarch64_allocate_ifunc_dynrelocs):
Updated.
* elfxx-x86.c (elf_x86_allocate_dynrelocs): Likewise.
(_bfd_x86_elf_size_dynamic_sections): Check elf.ifunc_resolvers
instead of readonly_dynrelocs_against_ifunc.
* elfxx-x86.h (elf_x86_link_hash_table): Remove
readonly_dynrelocs_against_ifunc.
ld/
PR ld/18801
* testsuite/ld-i386/i386.exp: Run ifunc-textrel-1a,
ifunc-textrel-1b, ifunc-textrel-2a and ifunc-textrel-2b.
* testsuite/ld-x86-64/x86-64.exp: Likewise.
* testsuite/ld-i386/ifunc-textrel-1a.d: Likewise.
* testsuite/ld-i386/ifunc-textrel-1b.d: Likewise.
* testsuite/ld-i386/ifunc-textrel-2a.d: Likewise.
* testsuite/ld-i386/ifunc-textrel-2b.d: Likewise.
* testsuite/ld-x86-64/ifunc-textrel-1.s: Likewise.
* testsuite/ld-x86-64/ifunc-textrel-1a.d: Likewise.
* testsuite/ld-x86-64/ifunc-textrel-1b.d: Likewise.
* testsuite/ld-x86-64/ifunc-textrel-2.s: Likewise.
* testsuite/ld-x86-64/ifunc-textrel-2a.d: Likewise.
* testsuite/ld-x86-64/ifunc-textrel-2b.d: Likewise.
* testsuite/ld-i386/pr18801a.d: Expect warning for IFUNC
resolvers.
* testsuite/ld-i386/pr18801b.d: Likewise.
* estsuite/ld-x86-64/pr18801a.d: Likewise.
* estsuite/ld-x86-64/pr18801b.d: Likewise.
All of data size, rep, lock, and rex prefixes are invalid with VEX- and
alike encoded insns. Make sure they get printed explicitly in all cases,
to signal the anomaly. With this, do away with "rex_ignored" - if there
is a rex prefix, we want to print it anyway for VEX etc (and there's
nothing "ignored" about it in the first place - such an instruction will
raise #UD).
Neither the legacy nor the VEX-encoded forms are permitted with register
operands, just like is already the case for their store forms as well as
{,V}MOV{L,H}PS.
At the same time, besides folding respective vex_len_table[] entries,
adjust adjacent related legacy mod_table[] entries:
- when the prefix was already decoded, PREFIX_OPCODE is pointless,
- limit the amount of string literals by using X consistently on all
{,V}MOV{L,H}P{S,D} forms.
For major opcodes allowing only packed FP kinds of operands, i.e. the
ones where legacy and AVX decoding uses the X macro, we can do so for
AVX512 as well, by attaching to the checking logic the "EVEX.W must
match presence of embedded 66 prefix" rule. (Encodings not following
this general pattern simply may not gain the PREFIX_OPCODE attribute.)
Note that testing of the thus altered decoding has already been put in
place by "x86: correct decoding of packed-FP-only AVX encodings".
This can also be at least partly applied to scalar-FP-only insns (i.e.
V{,U}COMIS{S,D}) as well as the vector-FP forms of insns also allowing
scalar encodings (e.g. VADDP{S,D}).
Take the opportunity and also fix EVEX-encoded VMOVNTP{S,D} as well as
to-memory forms of VMOV{L,H}PS and both forms of VMOV{L,H}PD to wrongly
disassemble with only register operands.
Various AVX insns utilizing the X macro fail to reject F3/F2 embedded
prefix encodings. As the PREFIX_OPCODE attribute wasn't used by any
non-legacy-encoded insns so far, re-use it to achieve the intended
effect.
An unwanted side effect of 5990e377e5 ("x86-64: Intel64 adjustments
for insns dealing with far pointers") was that with -mintel64 LCALL and
LJMP would now default to 64-bit operand size. Since 64-bit far branches
aren't portable, the default operand size should still be 32-bit.
However, since the 64-bit variant is permitted, an ambiguous operand
warning should be issued.
As to the actual code change, please note that the conditional
surrounding the switch() that gets adjusted covers several cases which
are of no interest to or benign in 64-bit mode, hence the new
conditional added can be quite a bit less involved.
{vex}, {vex3}, and {evex} are mandatory prefixes, and hence should not
be randomly ignored. Fix this for insns without operands as well as for
insns referencing the high 16 [XYZ]MM registers. To achieve the former,
re-purpose VEX_check_operands(), renaming it to VEX_check_encoding() and
moving its only operand check to check_VecOperands().
This involves fixing a testcase relying on {vex2} to get ignored.
For ppc64 I set flags when recording the dynamic relocation rather
than when allocating space. That allows you to distinguish three
cases:
1) The dynamic ifunc relocation is in an executable and will always be
to an ifunc resolver in the executable.
2) The dynamic ifunc relocation is in a shared library which provides
an ifunc resolver, but that may be overridden at runtime to use a
resolver in another binary.
3) The dynamic ifunc relocation is not to a locally defined ifunc
resolver.
Case (3) won't cause a segfault trying to run resolver code that is
non-exec on older glibc.
I made case (1) an error for ppc64, but since newer glibc ld.so does
allow running ifunc resolvers when segments are writable I suppose I
should downgrade that to a warning like case (2).
* elf64-ppc.c (struct ppc_link_hash_table): Delete
maybe_local_ifunc_resolver field.
(build_global_entry_stubs_and_plt): Set local_ifunc_resolver in
cases where maybe_local_ifunc_resolver was set.
(ppc64_elf_relocate_section): Likewise.
(ppc64_elf_finish_dynamic_sections): Downgrade ifunc with textrel
error to a warning.
Remove the `TYPE_FIELD_TYPE` macro, changing all the call sites to use
`type::field` and `field::type` directly.
gdb/ChangeLog:
* gdbtypes.h (TYPE_FIELD_TYPE): Remove. Change all call sites
to use type::field and field::type instead.
Change-Id: Ifda6226a25c811cfd334a756a9fbc5c0afdddff3
Remove the `FIELD_TYPE` macro, changing all the call sites to use
`field::type` directly.
gdb/ChangeLog:
* gdbtypes.h (FIELD_TYPE): Remove. Change all call sites
to use field::type instead.
Change-Id: I7673fedaa276e485189c87991a9043495da22ef5
Add the `type` and `set_type` methods on `struct field`, in order to
remoremove the `FIELD_TYPE` macro. In this patch, the `FIELD_TYPE`
macro is changed to use `field::type`, so all the call sites that are
useused to set the field's type are changed to use `field::set_type`.
The next patch will remove `FIELD_TYPE` completely.
Note that because of the name clash between the existing field named
`type` and the new method, I renamed the field `m_type`. It is not
private per-se, because we can't make `struct field` a non-POD yet, but
it should be considered private anyway (not accessed outside `struct
field`).
gdb/ChangeLog:
* gdbtypes.h (struct field) <type, set_type>: New methods.
Rename `type` field to...
<m_type>: ... this. Change references throughout to use type or
set_type methods.
(FIELD_TYPE): Use field::type. Change call sites that modify
the field's type to use field::set_type instead.
Change-Id: Ie21f866e3b7f8a51ea49b722d07d272a724459a0
Remove `TYPE_INDEX_TYPE` macro, changing all the call sites to use
`type::index_type` directly.
gdb/ChangeLog:
* gdbtypes.h (TYPE_INDEX_TYPE): Remove. Change all call sites
to use type::index_type instead.
Change-Id: I56715df0bdec89463cda6bd341dac0e01b2faf84
Add the `index_type` and `set_index_type` methods on `struct type`, in
order to remove the `TYPE_INDEX_TYPE` macro. In this patch, the
`TYPE_INDEX_TYPE` macro is changed to use `type::index_type`, so all the
call sites that are used to set the type's index type are changed to use
`type::set_index_type`. The next patch will remove `TYPE_INDEX_TYPE`
completely.
gdb/ChangeLog:
* gdbtypes.h (struct type) <index_type, set_index_type>: New
methods.
(TYPE_INDEX_TYPE): Use type::index_type.
* gdbtypes.c (create_array_type_with_stride): Likewise.
Change-Id: I93bdca9de9f3e143d2ccea59310c63745315e18d
All ELF backends with TLS descriptor support have
/* The offset into splt of the PLT entry for the TLS descriptor
resolver. Special values are 0, if not necessary (or not found
to be necessary yet), and -1 if needed but not determined
yet. */
bfd_vma tlsdesc_plt;
/* The GOT offset for the lazy trampoline. Communicated to the
loader via DT_TLSDESC_GOT. The magic value (bfd_vma) -1
indicates an offset is not allocated. */
bfd_vma tlsdesc_got;
in symbol hash entry. Move tlsdesc_plt/tlsdesc_got to elf_link_hash_entry
to reduce code duplication.
* elf-bfd.h (elf_link_hash_entry): Add tlsdesc_plt and
tlsdesc_got.
* elf32-arm.c (elf32_arm_link_hash_table): Remove tlsdesc_plt
and dt_tlsdesc_got.
(elf32_arm_size_dynamic_sections): Updated. Clear
root.tlsdesc_plt for DF_BIND_NOW.
(elf32_arm_finish_dynamic_sections): Updated.
(elf32_arm_output_arch_local_syms): Likewise.
* elf32-nds32.c (nds32_elf_size_dynamic_sections): Updated.
Clear root.tlsdesc_plt for DF_BIND_NOW.
(nds32_elf_finish_dynamic_sections): Updated.
* elf32-nds32.h (elf_nds32_link_hash_table): Remove
dt_tlsdesc_plt and dt_tlsdesc_got.
* elf64-x86-64.c (elf_x86_64_finish_dynamic_sections): Updated.
* elfnn-aarch64.c (elf_aarch64_link_hash_table): Remove
tlsdesc_plt and dt_tlsdesc_got.
(elfNN_aarch64_allocate_dynrelocs): Updated.
(elfNN_aarch64_finish_dynamic_sections): Likewise.
(elfNN_aarch64_size_dynamic_sections): Updated. Clear
root.tlsdesc_plt for DF_BIND_NOW. Don't check DF_BIND_NOW
twice.
* elfxx-x86.c (elf_x86_allocate_dynrelocs): Updated.
(_bfd_x86_elf_size_dynamic_sections): Likewise.
(_bfd_x86_elf_finish_dynamic_sections): Likewise.
* elfxx-x86.h (elf_x86_link_hash_table): Remove tlsdesc_plt and
tlsdesc_got.
With the introduction of what right now is the very first conditional
in the function's loop (commit dc821c5f9a ["x86: replace Reg8, Reg16,
Reg32, and Reg64"]), the last if() in the same loop has become
pointless - retain just its body.
First of all, these registers have never been available on any 64-bit
CPU, and hence should not be recognized in 64-bit mode. But even before
that they had already disappeared - also don't recognize them when 586
or 686 architectures were explicitly set.
While putting together the previous patch I noticed that this test,
forever since its introduction, was dead. Update it so it will pass,
and enable it.
In 0e0eea7820 ("x86: x87-related adjustments") I screwed up CFI
directives with FPU support disabled, by moving the conditional there
across a check of "allow_pseudo_reg". Add the missing check.
Register aliases (created e.g. via .set) check their target register at
the time of creation of the alias. While this makes sense, it's not
enough: The underlying register must also be "visible" at the time of
use. Wrong use of such aliases would lead to internal errors in e.g.
add_prefix() or build_modrm_byte().
Split the checking part of parse_real_register() into a new helper
function and use it also from the latter part of parse_register() (at
the same time replacing a minor open coded part of it).
Since parse_register() returning NULL already has a meaning, a fake new
"bad register" indicator gets added, which all callers need to check
for.
Get
00000000000007c0 d elf32_tic6x_bed
0000000000000000 d elf32_tic6x_elf_bed
00000000000003e0 d elf32_tic6x_linux_bed
instead of
00000000000007c0 d elf32_bed
0000000000000000 d elf32_tic6x_elf_bed
00000000000003e0 d elf32_tic6x_linux_bed
* elf32-tic6x.c (elf32_bed): Defined the default to
elf32_tic6x_bed.
$LFLAGS is needed for -shared test. This fixes
FAIL: PR ld/21703 shared
for tic6x-*-elf.
* testsuite/ld-elf/shared.exp: Pass $LFLAGS to PR ld/21703
shared test.
elf64-hppa should use root.splt and root.srelplt instead of plt_sec and
plt_rel_sec so that elflink.c can see splt and srelplt. This fixed:
FAIL: ld-elf/pr19539
* elf64-hppa.c (elf64_hppa_link_hash_table): Remove plt_sec and
plt_rel_sec.
(elf64_hppa_check_relocs): Replace plt_sec/plt_rel_sec with
root.splt/root.srelplt.
(elf64_hppa_create_dynamic_sections): Likewise.
(elf64_hppa_size_dynamic_sections): Likewise.
(elf64_hppa_finish_dynamic_symbol): Likewise.
(elf_hppa_final_link): Likewise.
(elf_hppa_final_link_relocate): Likewise.
generic_val_print_float has an "embedded_offset" parameter, but it can
only ever be 0. I believe it is a leftover from the val_print
removal. This patch removes this parameter.
gdb/ChangeLog
2020-06-07 Tom Tromey <tom@tromey.com>
* valprint.c (generic_val_print_float): Remove "embedded_offset"
parameter.
(generic_value_print): Update.
