Assemble the esa-g5 test case with -march=g5.
Assemble the zarch-z900 test case with -march=z900.
gas/
* testsuite/gas/s390/s390.exp: Assemble processor specific test
cases for their respective processor (-march=<processor>).
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
The combination of an architecture size of 32 bits and z/Architecture
mode requires the highgprs flag to be set in the ELF output. It causes
the high-halves of the general purpose registers (GPRs) to be preserved
at run-time, so that the code can use 64-bit GPRs.
The architecture size of 32 bits can either be the default in case of
a default architecture name of "s390" or due to specification of the
option -m31 (to generate the 31-bit file format).
The z/Architecture mode can either be the default or due to
specification of the option -mzarch (to assemble for z/Architecture
mode). It can also be selected using the pseudo commands
".machinemode zarch" and ".machinemode zarch_nohighgprs". The latter
not causing the highgprs flag to be set.
The highgprs flag was only set when the following s390-specific
assembler options were given in the following specific order:
"-m31 -mzarch".
The highgprs flag was erroneously not set when:
- the order of above options was inverse (i.e. "-mzarch -m31"),
- the architecture mode defaulted to z/Architecture mode and
option "-m31" was specified,
- the architecture size defaulted to 32 bits due to a default
architecture name of "s390" and option -mzarch was specified,
- the architecture size defaulted to 32 bits and the architecture
mode defaulted to z/Architecture due to the specified processor
(e.g. "-march=z900" or follow-on processor).
Determine whether to set the highgprs flag in init_default_arch() after
having processed all assembler options in md_parse_option(). This
ensures the flag is set in all of the above cases it was erroneously not
set. Add test cases for highgprs flag, including ones that use
.machinemode to switch the architecture mode.
gas/
* config/tc-s390.c: Correct setting of highgprs flag in ELF
output.
* testsuite/gas/s390/s390.exp: Add test cases for highgprs
flag.
* testsuite/gas/s390/blank.s: Empty assembler source used in
test cases for "highgprs" flag.
* testsuite/gas/s390/esa-highgprs-0.d: Add test case for
highgprs flag.
* testsuite/gas/s390/zarch-highgprs-0.d: Likewise.
* testsuite/gas/s390/zarch-highgprs-1.d: Likewise.
* testsuite/gas/s390/esa-highgprs-machinemode-0.s: Add test case
for highgprs flag when using .machinemode to switch
architecture mode.
* testsuite/gas/s390/esa-highgprs-machinemode-0.d: Likewise.
* testsuite/gas/s390/esa-highgprs-machinemode-1.s: Likewise.
* testsuite/gas/s390/esa-highgprs-machinemode-1.d: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
The base register operand B may optionally be omitted in D(B) by coding
D and in D(L,B) by coding D(L). The index register operand X may
optionally be omitted in D(X,B) by coding D(,B) or D(B). Both base and
index register operands may optionally be omitted in D(X,B) by coding D.
In any case the omitted base and/or index register operand value
defaults to zero.
When parsing an erroneously omitted length L operand in D(L,B) by coding
D(,B) the base register operand B was erroneously consumed as length
operand. When using a register name for the base register operand this
was detected and reported as error. But when not using a register name
the base register operand value was erroneously used as length operand
value.
Correct the parsing of an omitted optional base or index register to not
erroneously use the base register operand value as length, when
erroneously omitting the length operand.
While at it rename the variable used to remember whether the base or
index register operand was omitted to enhance code readability.
Additionally add test cases for the optional omission of base and/or
index register operands.
Example assembler source:
mvc 16(1,%r1),32(%r2)
mvc 16(1),32(%r2)
mvc 16(,1),32(%r2) # undetected syntax error
Disassembly of bad assembly without commit shows the base register
operand value was erroneously used as length operand value:
0: d2 00 10 10 20 20 mvc 16(1,%r1),32(%r2)
6: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2)
c: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2)
Assembler messages with commit:
3: Error: operand 1: missing operand
gas/
* config/tc-s390.c: Correct parsing of omitted base register.
* testsuite/gas/s390/s390.exp: Add test cases for omitted base
and/or index register.
* testsuite/gas/s390/zarch-omitted-base-index.s: Test cases for
omitted optional base or index register.
* testsuite/gas/s390/zarch-omitted-base-index.d: Likewise.
* testsuite/gas/s390/zarch-omitted-base-index-err.s: Test cases
for omitted base and/or index register.
* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Do not consume any unexpected character including newline ('\n') when
detecting a syntax error when parsing an operand block with parenthesis.
This resolves the unfavorable assembler messages from the example below,
including consuming the newline at the end of the current statement and
reporting the next statement as junk.
While at it change the only pre-increment of the current instruction
string pointer into a post-increment to align with the other instances.
Example assembler source:
mvi 16(),32 # syntax error
a %r1,16(%r2 # syntax error
a %r1,16(%r2)
mvc 16(1,),32(%r2) # syntax error
mvc 16(1,%r1,32(%r2 # syntax error
Assembler messages without commit:
1: Error: bad expression
1: Error: syntax error; missing ')' after base register
1: Error: syntax error; expected ','
1: Error: junk at end of line: `32'
2: Error: syntax error; missing ')' after base register
2: Error: junk at end of line: `a %r1,16(%r2)'
4: Error: bad expression
4: Error: syntax error; missing ')' after base register
4: Error: syntax error; expected ','
4: Error: operand out of range (32 is not between 0 and 15)
4: Error: syntax error; missing ')' after base register
4: Error: junk at end of line: `%r2)'
5: Error: syntax error; missing ')' after base register
5: Error: syntax error; expected ','
5: Error: operand out of range (32 is not between 0 and 15)
5: Error: syntax error; missing ')' after base register
5: Error: junk at end of line: `%r2'
Assembler messages with commit:
1: Error: bad expression
1: Error: syntax error; missing ')' after base register
2: Error: syntax error; missing ')' after base register
4: Error: bad expression
4: Error: syntax error; missing ')' after base register
5: Error: syntax error; missing ')' after base register
5: Error: syntax error; missing ')' after base register
gas/
* config/tc-s390.c: Do not erroneously consume newline when
parsing an addressing operand with parentheses.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Report s390 assembler syntax errors as error instead of fatal error.
This allows the assembler to continue and potentially report further
syntax errors in the source. This should not cause syntax errors to
be erroneously accepted, as both error and fatal error cause the
assembler to return with a non-zero return code.
The following syntax errors are changed from fatal to error:
- invalid length field specified
- odd numbered general purpose register specified as register pair
- invalid floating point register pair. Valid fp register pair operands
are 0, 1, 4, 5, 8, 9, 12 or 13.
gas/
* config/tc-s390.c: Lower severity of assembler syntax errors
from fatal to error.
* testsuite/gas/s390/zarch-z9-109-err.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Consumers can't know which execution mode is in effect for a certain
piece of code; they can only go from object file properties. Hence which
register numbers to encode ought to depend solely on object file type.
In tc_x86_frame_initial_instructions() do away with parsing a register
name: We have a symbolic constant already for the 64-bit case, and the
32-bit number isn't going to change either. Said constant's definition
needs moving, though, to be available also for non-ELF. While moving
also adjust the comment to clarify that it's applicable to 64-bit mode
only.
... plus the SME part of B16B16. As per
https://sourceware.org/pipermail/binutils/2024-February/132408.html
SVE2.1 support is both incomplete and buggy. SME2.1 "support" goes as
far as a single instruction (a subset of movaz forms) only. The SME part
of B16B16 is entirely missing.
While most logic in optimize_encoding() is already covering APX by way
of the earlier NDD->REX2 conversion, there's a remaining set of cases
which wants handling separately.
In this case spaces 0f38 and 0f3a may not be put in place. To achieve
the intended effect, operand parsing (but not operand processing) needs
pulling ahead, so we know whether eGRP-s are in use.
Even when an EVEX encoding is available, use of such a prefix ought to
be respected (resulting in an error) rather than ignored. As requested
during review already, introduce a new encoding enumerator to record use
of eGPR-s, and update state transitions accordingly.
The optimize_encoding() change also addresses an internal assembler
error that was previously raised when respective memory operands used
eGPR-s for addressing.
While this results in a change of diagnostic issued for VEX-encoded
insns, the new one is at least no worse than the prior one.
gas/
* tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi,
%tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype
renamed to percent_op_relax_only as this matcher is extended to handle
jalr as well which is not R-type.
(riscv_ip): Apply the percent_op_relax_only rename and update comment.
(md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to
TLS relocation check list.
* testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation
generation.
opcodes/
* riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with
%tlsdesc_call annotations.
Catching this at configure time would be nicer, but we'd need to exactly
match mips_parse_cpu in configure.ac and keep it all in sync.
PR 23877
* config/tc-mips.c (mips_after_parse_args): Don't assert that
mips_parse_cpu returns non-NULL, call as_fatal with an informative
message instead.
Hi,
Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature with internal names that don't match the actual feature name pauth. The new feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature of Armv8.3-A. Using a different naming for it not based on the formerly "PAC" would create confusion.
Regression tested on aarch64-none-elf, and no regression found.
Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf.
Regards,
Matthieu.
From 58b38358b2788939d81f2df7f5fb4c64a31ae06e Mon Sep 17 00:00:00 2001
From: Matthieu Longo <matthieu.longo@arm.com>
Date: Fri, 23 Feb 2024 11:30:40 +0000
Subject: [PATCH] aarch64: rename internals related to PAuth feature to use
pauth in their naming for coherency
Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature
with internal names that don't match the actual feature name pauth. The new
feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature
of Armv8.3-A. Using a different naming for it not based on the formerly "PAC"
would create confusion.
gas needs to build lists of sections for each group. This arranges to
build the lists earlier, so they can be used when looking for sections
that belong to a group. Using the section hash table to find sections
by name, then by group isn't efficient when there are numerous groups
with the same section names. Using a hash table to quickly find a
group, then searching by section name on a list for the group results
in a 100-fold speed improvement assembling the testcase in this PR.
To reduce the number of times we traverse the section list, the patch
also moves some processing done in elf_adjust_symtab for linked-to
section, to elf_frob_file. This requires a testsuite change because
processing will stop before elf_frob_file if there is a parse error in
section21.s, ie. you'll only get the "junk at end of line" error, not
the "undefined linked-to symbol" errors.
PR 25333
* config/obj-elf.c (struct group_list, groups): Move earlier.
(match_section): New function, extracted from..
(get_section_by_match): ..here.
(free_section_idx): Move earlier.
(group_section_find, group_section_insert): New functions.
(change_section): Use the above.
(elf_set_group_name): New function.
(obj_elf_attach_to_group): Use elf_set_group_name.
(set_additional_section_info): Handle linked_to_symbol_name and
stabs code, extracted from..
(adjust_stab_sections): ..here,..
(build_additional_section_info): ..and here.
(elf_adjust_symtab): Don't call build_additional_section_info.
(elf_frob_file): Adjust.
* config/obj-elf.h (elf_set_group_name): Declare.
* config/tc-xtensa.c (cache_literal_section): Use elf_set_group_name.
(xtensa_make_property_section): Likewise.
* testsuite/gas/elf/attach-1.d: Stricter group section matching,
and changed group section ordering.
* testsuite/gas/elf/attach-2.d: Stricter group section matching.
* testsuite/gas/elf/attach-2.s: Provide section bar type.
* testsuite/gas/elf/elf.exp: Run attach-2.
* testsuite/gas/elf/section21.l: Update.
* testsuite/gas/elf/section21.s: Don't check for a parse error.
This function is only used by gas, so move it there. Necessary for
gas to keep track of group sections as they are created.
PR 25333
bfd/
* elf32-xtensa.c (xtensa_make_property_section): Delete.
(xtensa_property_section_name): Make public.
include/
* elf/xtensa.h (xtensa_make_property_section): Delete.
(xtensa_property_section_name): Declare
gas/
* config/tc-xtensa.c (xtensa_make_property_section): New,
moved from elf32-xtensa.c.
Even with just VEX these weren't limited to vector insns. With APX the
set of non-vector ones covered has greatly increased. Drop the vec_
prefix. Also drop the vex_ ones off of the enumerators, as they weren't
appropriate anyway: Should have been vec_ then, too.
Next to code using %ymm<N> or %zmm<N> it is more natural to have .cfi_*
directives also reference those, not the corresponding %xmm<N>. Accept
their names as kind of aliases, i.e. resolving to the same numbers.
While extending the respective 64-bit testcase, also add %bnd<N> there
(should have happened right with 633789901c ["x86-64: Dwarf2 register
numbers for %bnd<N>"], sorry), requiring binutils/dwarf.c to be adjusted
accordingly as well.
While various other entries in version 003 of the spec aren't quite as
explicit (due to simply leaving the respective field blank), all three
have a clear IGNORED there. IOW they ought to be emitted with EVEX.W=0
by default (and respect -mevexwig=).
The R_LARCH_ALIGN need to associated with a symbol if .align has the first
and third expressions. If R_LARCH_ALIGN associate with a symbol, the addend can
represent the first and third expression of .align.
For '.align 3', the addend of R_LARCH_ALIGN only need to represent the alignment
and R_LARCH_ALIGN not need to associate with a symbol.
For '.align x, , y', R_LARCH_ALIGN need to associate with a symbol if 0 < y <
2^x - 4.
notes_alloc is perfect for assorted memory you can't free easily
and/or would rather leave freeing until just before exit.
* config/tc-i386.c (i386_elf_section_change_hook): Use notes_alloc.
This patch moves the existing sysreg tests for AArch64 into a subdirectory
(sysreg). The number of test files related to system registers grew
relatively big with time and makes the browsing of those files difficult.
Moreover, the difference of naming for the failure, working, and
feature-specific scenarios causes the tests not to appear next to one
another in the exploration tree when it is ordered alphabetically.
Refer to commit, dff565fcca. Theoretically,
assembler don't need to generate the pc-relative relocation and the refered
local .L symbol when relaxation is disabled. The above commit improved the
pcrel_hi/pcrel_lo relocations, and this commit improves branch and jump
relocations.
Passed the gcc/binutils regressions of riscv-gnu-toolchain.
gas/
* config/tc-riscv.c (md_apply_fix): Raise fixP->fx_done for all
branch and jump relocations when -mno-relax.
Most registers from a register-pair suffixed by .lo and .hi suffixes.
This was not the case of $r14 and $r15 since they are defined by the
ABI: $r14 is the frame pointer, and $r15 is used to return aggregates
from functions. We do not add aliases for $r12 (the stack pointer) and
$r13 (the tls register).
opcodes/ChangeLog:
* kvx-opc.c: Regenerate.
gas/ChangeLog:
* config/kvx-parse.h: Regenerate.
TCA instructions start with an X, this introduces ambiguities when it
comes to XOR (Is it the OR on the TCA or the XOR of the core?). For this
reason, we rename OR to IOR and XOR to EOR.
OR and XOR variants are still valid on KV3-1 and KV3-2. However, they
have been completely removed from KV4-1.
opcodes/ChangeLog:
* kvx-opc.c: Regenerate.
include/ChangeLog:
* opcode/kvx.h: Regenerate.
gas/ChangeLog:
* config/kvx-parse.h: Regenerate.
* testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate.
* testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate.
* testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate.
* testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate.
* testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate.
* testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate.
* testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate.
* testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate.
* testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate.
* testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate.
* testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate.
* testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
Up until now, we used ENV.PROMOTE_IMMEDIATE to get the next candidates,
however this candidate can be directly extracted from the array (in
kvx-parse.h) registering all the immediates.
During lexing, we ignored trailing characters after a number, this is
not good enough since now number can be followed by a modifier. The
function READ_TOKEN and GET_TOKEN_CLASS have been update to take this
into account.
gas/ChangeLog:
* config/kvx-parse.c (promote_token): Do not rely on
env.promote_immediate anymore.
(get_token_class): Do not ignore trailing characters after a
number.
(read_token): Likewise.
(print_token_list): THIS SHOULD NOT BE HERE.
The detection of negative powers of 2 was wrong and could lead to
well-formed bundles ending up taking more syllables than necessary.
gas/ChangeLog:
* config/kvx-parse.c (get_token_class): Use the signed value.
* testsuite/gas/kvx/np2-detection.d: New test.
* testsuite/gas/kvx/np2-detection.s: New test.
This adds teh following files that were missing in the previous
commit ecd16ae4e4
testsuite/gas/bpf/indcall-badoperand.d
testsuite/gas/bpf/indcall-badoperand.l
testsuite/gas/bpf/indcall-badoperand.s
As a result of a switch instead of an if, as would issue non-specific
error messages when it encountered an operand it could not parse in bpf.
This patch fixes that regression and adds a test to prevent it from
reoccurring.
Tested for bpf-unknown-none on x86_64-redhat-linux.
gas/ChangeLog:
* config/tc-bpf.c (parse_expression): Change switch to if so that error
* condition is handled.
* testsuite/gas/bpf/bpf.exp: Invoke new test.
* testsuite/gas/bpf/indcall-badoperand.d: New test.
* testsuite/gas/bpf/indcall-badoperand.l: New test.
* testsuite/gas/bpf/indcall-badoperand.s: New test.
The PARSE_ERROR macro in md_assemble performs pointer subtraction. If
parse_expression returns NULL then the later will be part of the
subtraction and therefore UB will be incurred.
This patch changes md_assemble to:
1. Accommodate all invocations to parse_expression to the fact it will
return NULL when a parse error occurs.
2. Avoid UB in PARSE_ERROR.
Tested in bpf-unknown-none target / x86_64-linux-gnu host.
gas/ChangeLog:
* config/tc-bpf.c (md_assemble): Fix to take into account that
parse_expression can return NULL.
(PARSE_ERROR): Avoid passing invalid length to parse_error.
Hi,
[PATCH][Binutils] aarch64: Add support for the id_aa64isar3_el1 system register
AArch64 defines a read-only system register called id_aa64isar3_el1.
This patch also adds relevant tests.
Regression tested on the aarch64-none-elf and aarch64-none-linux-gnu targets
and no regressions was found.
Is this Ok for trunk? I do not have commit rights, if OK, can someone commit on my behalf?
Thanks,
Yury Khrustalev
From e42c835e8f2ee81150f498675f2faf108bbe79f8 Mon Sep 17 00:00:00 2001
From: Yury Khrustalev <yury.khrustalev@arm.com>
Date: Tue, 6 Feb 2024 11:05:39 +0000
Subject: [PATCH] [PATCH][Binutils] aarch64: Add support for the
id_aa64isar3_el1 system register
AArch64 defines a read-only system register called id_aa64isar3_el1.
This patch also adds relevant tests.
Regression tested on the aarch64-none-elf and aarch64-none-linux-gnu targets
and no regressions was found.
The patch adds support for the IMAGE_REL_ARM64_REL32 coff relocation
type. This is needed for 32-bit relative address.
It also adds a check for relocation offsets over 21 bits. Offsets
inside coff files are stored in instruction code. In the case of ADRP
the actual value is stored, not a downshifted page offset. This means
values over 21 bits would otherwise be truncated.
Finally it adds a mapping for BFD_RELOC_AARCH64_ADR_GOT_PAGE and
BFD_RELOC_AARCH64_LD64_GOT_LO12_NC that were previously skipped.
ChangeLog:
* bfd/coff-aarch64.c (coff_aarch64_reloc_type_lookup): Add
BFD_RELOC_AARCH64_ADR_GOT_PAGE,
BFD_RELOC_AARCH64_LD64_GOT_LO12_NC and IMAGE_REL_ARM64_REL32
relocations.
(coff_pe_aarch64_relocate_section): Likewise.
* gas/write.c (adjust_reloc_syms): COFF AArch64 relocation
offsets need to be limited to 21bits
(defined): Likewise.
Several years ago it was decided that SSE2AVX templates should not be
sensitive to -mvexwig= (upon my suggestion to consistently make all
sensitive as long as they don't require a specific setting of VEX.W).
Adjust the four that still are, switching to use of Vex128 at the same
time.
Display -msse-check= default as none for "as --help" since its default
is none, not warning.
PR gas/31389
* config/tc-i386.c (md_show_usage): Change -msse-check= default
to none.
Albeit not being a currently valid BPF instruction, callx is generated
by both clang and GCC when BPF programs are compiled unoptimized.
Until now, GCC would emit it only whe using the experimental
compiler-testing cpu version xbpf, whereas clang would emit it from
v1. This patch makes GAS to accept callx also starting with cpu v1.
opcodes/ChangeLog
* bpf-opc.c: Move callx into the v1 BPF CPU variant.
gas/ChangeLog
* testsuite/gas/bpf/indcall-1-pseudoc.d: Do not select xbpf cpu
version.
* testsuite/gas/bpf/indcall-1.d: Likewise.
This patch exposes the symbol "resolving" flag for use in
i386_intel_simplify, not only preventing infinite recursion on the
testcase in the PR but also more complicated cases like:
.intel_syntax
b = a
a = b
mov eax, [a]
PR 30308
* symbols.c (symbol_mark_resolving, symbol_clear_resolving),
(symbol_resolving_p): New functions.
* symbols.h: Declare them.
* config/tc-i386-intel.c (i386_intel_simplify): Delete forward
declaration. Formatting.
(i386_intel_simplify_symbol): Use resolving flag to prevent
infinite recursion.
DBNZ instruction decrements its source register operand, and if
the result is non-zero it branches to the location defined by a signed
half-word displacement operand.
DBNZ instruction is in BRANCH class as other branch instrucitons
like B, Bcc, etc. However, DBNZ is the only branch instruction
that stores a branch offset in the second operand. Thus it must
be placed in a distinct class and treated differently.
For example, current logic of arc_insn_get_branch_target in GDB
assumes that a branch offset is always stored in the first operand
for BRANCH class and it's wrong for DBNZ.
include/ChangeLog:
2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com>
* opcode/arc.h (enum insn_class_t): Add DBNZ class.
opcodes/ChangeLog:
2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com>
* arc-tbl.h (dbnz): Use "DBNZ" class.
* arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class.
gas/ChangeLog:
2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com>
* config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".
Interestingly unlike VROUND{P,S}{S,D} and VPERM{F,I}128 they weren't
even present in the x86-64-apx-egpr-inval testcase, hence why I
overlooked that these can actually be encoded, (again) using suitable
AVX512 counterparts.
While there also "modernize" the adjacent AVX/AVX2 entries.
Already the %bnd<N> registers used numbers beyond 127, and eGPR ones are
all out of reach for "signed char", at least when CHAR_BITS=8. Switch to
"unsigned char", covering appropriately in places where the value
returned for "none" actually matters (in tc_x86_parse_to_dw2regnum()
this is actually achieved by altering how X_op is set).
It has been observed that the run of scfi-unsupported-1 test with --x32
arg on a Solaris2 x86_64 system fails:
Executing on host: sh -c {../as-new --x32 --scfi=experimental \
<...>/scfi-unsupported-1.s 2>&1} /dev/null dump.out (timeout = 300)
Assembler messages:
Fatal error: no compiled in support for 32bit x86_64
regexp_diff match failure
regexp "^Fatal error: SCFI is not supported for this ABI$"
line "Fatal error: no compiled in support for 32bit x86_64"
FAIL: x86_64 scfi-unsupported-1
Fix the above by adding a check for --x32 support before running the
test. While at it, also include a similar check for --32 support.
gas/testsuite/
* gas/scfi/x86_64/scfi-x86-64.exp: Add gas_x32_check and
gas_32_check. Conditionalize the execution of affected
testcases.
PR gas/31326
SCFI must handle non QWORD ALU with imm and MOV ops correctly
As per the x86 ISA manual:
- 32-bit operands generate a 32-bit result, zero-extended to a 64-bit
result in the destination general-purpose register.
- 8-bit and 16-bit operands generate an 8-bit or 16-bit result. The
upper 56 bits or 48 bits (respectively) of the destination
general-purpose register are not modified by the operation.
Unlike previously thought, sub-QWORD ALU/imm and MOV ops do have
implications on SCFI. SCFI/ginsn machinery does not track operation size
in the ginsn representation. But given that these sub-QWORD ops update
only a portion of a 64-bit destination register, for SCFI purposes, this
needs to be deemed as an untraceable update (when the destination is
REG_SP / REG_FP). Although in most cases, sub-QWORD ops are not expected
for stack management, but the SCFI machinery must behave correctly, when
such ops are indeed present.
As mentioned earlier, ginsn representation does not carry operation size
information. To resolve the issue raised in PR gas/31326, an option is
to force the generation of GINSN_TYPE_OTHER for all cases when there is
a 8/16/32 bit op. But this may dilute the utility of ginsn for other
use-cases, when they pop up in future.
The current approach is less disruptive than above in that it generates
GINSN_TYPE_OTHER for all cases only when:
- there is a 8/16/32 bit op, and
- the 64-bit op is otherwise traceable.
In other words this means:
- For add/sub ops where dest is reg and src is reg/mem: these always
make dest reg untraceable; So, the current handling is unchanged. We
simply skip detecting 8/16/32-bit ops.
- An x86 pop instruction is translated to a load ginsn followed by a stack
increment add op. A load op always makes dest reg untraceable.
Hence, if the pop instruction is sub-QWORD, we continue to (skip
detecting 8/16/32-bit op, and) generate the load instruction as usual.
This means that if input asm does have save and restore of unequal sized
registers, gas/SCFI will not detect nor warn.
- For ALU imm or MOV reg,reg, however, a GINSN_TYPE_OTHER is generated
when a 8/16/32-bit op is seen.
gas/
PR gas/31326
* config/tc-i386.c (x86_ginsn_addsub_reg_mem): Add a code
comment.
(x86_ginsn_addsub_mem_reg): Likewise.
(x86_ginsn_alu_imm): Detect sub-QWORD opsize and exit early.
(x86_ginsn_move): Likewise.
(x86_ginsn_new): Add comment for 8-bit add/sub opcodes (in
opcode_space SPACE_BASE) about skipped handling.
gas/testsuite/:
PR gas/31326
* gas/scfi/x86_64/ginsn-add-1.l: Update.
* gas/scfi/x86_64/ginsn-add-1.s: Add some sub-QWORD add ops.
* gas/scfi/x86_64/ginsn-dw2-regnum-1.l: Update.
* gas/scfi/x86_64/ginsn-dw2-regnum-1.s: Use mov ops instead of
add to invoke and test the ginsn_dw2_regnum code path.
Change .insn instruction with length > 15 bytes from error to warning.
PR gas/31323
* config/tc-i386.c (output_insn): Issue a warning when .insn
instruction length exceeds the limit of 15 bytes.
* testsuite/gas/i386/oversized64.s: Add a test for .insn
* testsuite/gas/i386/oversized64.l: Updated.
When a symbol is referred with %le_{hi20,lo12,add}_r, it's definitely a
TLS symbol and we should set its type to TLS in the symtab. Otherwise
when building Perl with gcc-14 -flto, we get:
/usr/bin/ld: PL_current_context: TLS definition in
./miniperl.ltrans0.ltrans.o section .tbss mismatches non-TLS reference
in ./miniperl.ltrans1.ltrans.o
A minimal reproducer:
$ cat t1.s
.section .tbss
.globl x
x: .word 0
$ cat t2.s
f:
lu12i.w $a0, %le_hi20_r(x)
add.d $a0, $a0, $tp, %le_add_r(x)
li.w $a1, 1
st.w $a1, $a0, %le_lo12_r(x)
$ gas/as-new t1.s -o t1.o
$ gas/as-new t2.s -o t2.o
$ ld/ld-new t1.o t2.o
ld/ld-new: x: TLS definition in t1.o section .tbss mismatches
non-TLS reference in t2.o
Unfortunately this was undetected before Binutils-2.42 release because
GCC < 14 does not use %le_*_r, and without LTO it's very rare to have a
TLS LE definition and its reference in two different translation units.
So this fix should be backported to Binutils-2.42 branch too.
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
By pulling it ahead of the SHORT_MNEM_SUFFIX case label we can drop a
part of another conditional there. While moving, also drop a pointless
check: With QWORD_MNEM_SUFFIX, register operands of XCHG necessarily
have both been 64-bit ones.
For quite some time we've had support for -O command line options. With
that ignoring at least .noopt isn't really a good idea.
Re-purpose the optimize-3 test for testing this directive's effect as
well.
As to the doc addition - this uses the same text as is there for the
{nooptimize} pseudo-prefix, despite me not being convinced of the "size"
part being fully accurate there (and hence also here).
A review comment on the SCFI V4 series was to handle ginsn creation for
certain lea opcodes more precisely.
Specifically, we should preferably handle the following two cases of lea
opcodes similarly:
- #1 lea with "index register and scale factor of 1, but no base
register",
- #2 lea with "no index register, but base register present".
Currently, a ginsn of type GINSN_TYPE_OTHER is generated for the
case of #1 above. For #2, however, the lea insn is translated to either
a GINSN_TYPE_ADD or GINSN_TYPE_MOV depending on whether the immediate
for displacement is non-zero or not respectively.
Change the handling in x86_ginsn_lea so that both of the above lea
manifestations are handled similarly.
While at it, remove the code paths creating GINSN_TYPE_OTHER altogether
from the function. It makes sense to piggy back on the
x86_ginsn_unhandled code path to create GINSN_TYPE_OTHER if the
destination register is interesting. This was also suggested in one of
the previous review rounds; the other functions already follow that
model, so this keeps functions symmetrical looking.
gas/
* gas/config/tc-i386.c (x86_ginsn_lea): Handle select lea ops with
no base register similar to the case of no index register. Remove
creation of GINSN_TYPE_OTHER from the function.
gas/testsuite/
* gas/scfi/x86_64/ginsn-lea-1.l: New test.
* gas/scfi/x86_64/ginsn-lea-1.s: Likewise.
* gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
There are no legacy ldind nor ldabs BPF instructions with BPF_SIZE_DW.
For some reason we were (incorrectly) supporting these. This patch
updates the opcodes so the instructions get removed and modifies the
GAS manual and testsuite accordingly.
See discussion at
https://lore.kernel.org/bpf/110aad7a-f8a3-46ed-9fda-2f8ee54dcb89@linux.dev
Tested in bpf-uknonwn-none target, x86-64-linux-gnu host.
include/ChangeLog:
2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/bpf.h (enum bpf_insn_id): Remove BPF_INSN_LDINDDW and
BPF_INSN_LDABSDW instructions.
opcodes/ChangeLog:
2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and
BPF_INSN_LDABSDW instructions.
gas/ChangeLog:
2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
* doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit
load instruction.
(BPF Instructions): There is no absolute 64-bit load instruction.
* testsuite/gas/bpf/mem.s: Update test accordingly.
* testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-be.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
* testsuite/gas/bpf/mem.d: Likewise.
* testsuite/gas/bpf/mem.s: Likewise.
PR gas/31284
Currently, if an indirect jump is seen, GCFG (a CFG of ginsns) cannot be
created, and the SCFI machinery bails out with a warning:
"Warning: Untraceable control flow for func 'foo'; Skipping SCFI"
It is, however, better suited if this is a hard error. Change it to a
hard error. Also change the message to skip mentioning "SCFI", because
the error itself may also useful when ginsns are used for other passes
(distinct from SCFI) involving GCFG, like a pass to detect if there is
unreachable code. Hence, simply say:
"Error: untraceable control flow for func 'foo'"
gas/
PR gas/31284
* ginsn.c (ginsn_data_end): Use as_bad instead of as_warn.
gas/testsuite/
PR gas/31284
* gas/scfi/x86_64/ginsn-cofi-1.l: Adjust to the expected output
in case of errors.
* gas/scfi/x86_64/scfi-unsupported-cfg-1.l: Error not Warning.
The testcase for change of flow instructions in its current shape is not
doing much: it checks that SCFI issues an appropriate warning. The same
warning is covered by another testcase (scfi-unsupported-cfg-1); It is
better to test the ginsn translation instead, for these 'change of flow
instructions'.
gas/testsuite/
* gas/scfi/x86_64/scfi-cofi-1.s: Moved to...
* gas/scfi/x86_64/ginsn-cofi-1.s: ...here.
* gas/scfi/x86_64/scfi-x86-64.exp: Adjust tests.
* gas/scfi/x86_64/scfi-cofi-1.d: Removed.
* gas/scfi/x86_64/scfi-cofi-1.l: Removed.
* gas/scfi/x86_64/ginsn-cofi-1.l: New test.
Adjustments made for the directive (by set_intel_syntax()) need also
making for the command line option. Break out respective code into a new
helper function, to also be invoked during command line processing.
Further also set register_prefix when processing -mnaked-reg.
With identical source and destination it can be covered by the NDD-to-
legacy conversion logic as well, even if in this case the original insn
doesn't use an NDD encoding. The size savings are even better here, for
the replacement (BSWAP) not having a ModR/M byte.
For R_LARCH_TLS_{LE_HI20_R,LE_ADD_R,LD_PC_HI20,GD_PC_HI20, DESC_PC_HI20}
relocations, start a new frag to get correct eh_frame Call Frame Information
FDE DW_CFA_advance_loc info.
Gcc may generate "\t.align\t%d,54525952,4\n" before commit
b20c7ee066cb7d952fa193972e8bc6362c6e4063. To write 54525952 (NOP) to object
file, we call s_align_ptwo (-4). It result in alignment padding must be a
multiple of 4 if .align has second parameter.
Use default s_align_ptwo for .align.
Restructure the architecture extensions table, add a new table for architecture
version dependencies, add missing architecture extensions, and improve some
extension descriptions.
Append "#pass" to APX tests for targets which pad text sections with NOPs.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Append
"#pass".
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: Likewise.
VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As
long as the immediate has the top 4 bits clear, they are equivalent to
the earlier VEX-encoded insns, and hence can be used to permit use of
eGPR-s in the memory operand. Since this is the normal way of using
these insns, also alter the resulting diagnostic to complain about the
immediate, not the eGPR use.
When there's a suitably disambiguating register operand, suffixes are
generally omitted (unless in suffix-always mode). All NDD insns have a
suitable register operand, so they shouldn't have suffixes by default.
Since SCFI isn't supported on x32:
Fatal error: SCFI is not supported for this ABI
skip SCFI tests for x32 targets.
PR gas/31245
* testsuite/gas/scfi/x86_64/scfi-x86-64.exp: Skip for x32
targets.
Along with the relevant unit-tests, this adds the following rcpc3
instructions:
STL1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAP1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAPUR <Bt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Ht>, [<Xn|SP>{, #<simm>}]
LDAPUR <St>, [<Xn|SP>{, #<simm>}]
LDAPUR <Dt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Qt>, [<Xn|SP>{, #<simm>}]
STLUR <Bt>, [<Xn|SP>{, #<simm>}]
STLUR <Ht>, [<Xn|SP>{, #<simm>}]
STLUR <St>, [<Xn|SP>{, #<simm>}]
STLUR <Dt>, [<Xn|SP>{, #<simm>}]
STLUR <Qt>, [<Xn|SP>{, #<simm>}]
with `#<simm>' taking on a signed 8-bit integer value in the range
[-256,255] and `index' the values 0 or 1.
Co-authored-by: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
- AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
- AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
Indicating the presence of the Armv8.2-a feature adding further
support for the Release Consistency Model, the `+rcpc3' architectural
extension flag is added to the list of possible `-march' options in
Binutils, together with the necessary macro for encoding rcpc3
instructions.
There are some tlbi operations that don't have a corresponding tlbip operation,
but we were incorrectly using the same list for both. Add the missing tlbi
*nxs operations, and use the F_REG_128 flag to filter tlbi operations that
don't have a tlbip analogue. For increased clarity, I have also used a macro
to reduce duplication between the 'nxs' and non-'nxs' variants, and added a
test to verify that no invalid combinations are accepted.
Additionally, fix two missing checks for AARCH64_OPND_SYSREG_TLBIP that were
preventing disassembly of tlbip instructions.
Hi,
This patch add support for SVE2.1 instructions ld1q,
ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 instruction faddqv,
fmaxnmqv, fmaxqv, fminnmqv and fminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 instruction dupq, eorqv and extq.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature
along with +sve2p1 optional flag to enabe this feature.
Also support for following SVE2p1 instructions is added
addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for FEAT_SME2p1 and "movaz" instructions
along with the optional flag +sme2p1.
Following "movaz" instructions are add:
Move and zero two ZA tile slices to vector registers.
Move and zero four ZA tile slices to vector registers.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 and SME2.1 non-widening BFloat16
(FEAT_B16B16) instructions.
Following instructions predicated, unpredicated and indexed
variants are added in this patch.
bfadd, bfclamp, bfmax bfmaxnm, bfmin,bfminnm,
bfmla,bfmls,bfmul and bfsub.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
The testsuite for SCFI contains target-specific tests.
When a test is executed with --scfi=experimental command line option,
the CFI annotations in the test .s files are skipped altogether by the
GAS for processing. The CFI directives in the input assembly files are,
however, validated by running the assembler one more time without
--scfi=experimental.
Some testcases are used to highlight those asm constructs that the SCFI
machinery in GAS currently does not support:
- Only System V AMD64 ABI is supported for now. Using either --32 or
--x32 with SCFI results in hard error.
See scfi-unsupported-1.s.
- Untraceable stack-pointer manipulation in function epilougue and prologue.
See scfi-unsupported-2.s.
- Using Dynamically Realigned Arguement Pointer (DRAP) register to
realign the stack. For SCFI, the CFA must be only REG_SP or REG_FP
based. See scfi-unsupported-drap-1.s
Some testcases are used to highlight some diagnostics that the SCFI
machinery in GAS currently issues, with an intent to help user correct
inadvertent errors in their hand-written asm. An error is issued when
GAS finds that input asm is not amenable to correct CFI synthesis.
- (#1) "Warning: SCFI: Asymetrical register restore"
- (#2) "Error: SCFI: usage of REG_FP as scratch not supported"
- (#3) "Error: SCFI: unsupported stack manipulation pattern"
In case of (#2) and (#3), SCFI generation is skipped for the respective
function. Above is a subset of the warnings/errors implemented in the
code.
gas/testsuite/:
* gas/scfi/README: New test.
* gas/scfi/x86_64/ginsn-add-1.l: New test.
* gas/scfi/x86_64/ginsn-add-1.s: New test.
* gas/scfi/x86_64/ginsn-dw2-regnum-1.l: New test.
* gas/scfi/x86_64/ginsn-dw2-regnum-1.s: New test.
* gas/scfi/x86_64/ginsn-pop-1.l: New test.
* gas/scfi/x86_64/ginsn-pop-1.s: New test.
* gas/scfi/x86_64/ginsn-push-1.l: New test.
* gas/scfi/x86_64/ginsn-push-1.s: New test.
* gas/scfi/x86_64/scfi-add-1.d: New test.
* gas/scfi/x86_64/scfi-add-1.l: New test.
* gas/scfi/x86_64/scfi-add-1.s: New test.
* gas/scfi/x86_64/scfi-add-2.d: New test.
* gas/scfi/x86_64/scfi-add-2.l: New test.
* gas/scfi/x86_64/scfi-add-2.s: New test.
* gas/scfi/x86_64/scfi-asm-marker-1.d: New test.
* gas/scfi/x86_64/scfi-asm-marker-1.l: New test.
* gas/scfi/x86_64/scfi-asm-marker-1.s: New test.
* gas/scfi/x86_64/scfi-asm-marker-2.d: New test.
* gas/scfi/x86_64/scfi-asm-marker-2.l: New test.
* gas/scfi/x86_64/scfi-asm-marker-2.s: New test.
* gas/scfi/x86_64/scfi-asm-marker-3.d: New test.
* gas/scfi/x86_64/scfi-asm-marker-3.l: New test.
* gas/scfi/x86_64/scfi-asm-marker-3.s: New test.
* gas/scfi/x86_64/scfi-bp-sp-1.d: New test.
* gas/scfi/x86_64/scfi-bp-sp-1.l: New test.
* gas/scfi/x86_64/scfi-bp-sp-1.s: New test.
* gas/scfi/x86_64/scfi-bp-sp-2.d: New test.
* gas/scfi/x86_64/scfi-bp-sp-2.l: New test.
* gas/scfi/x86_64/scfi-bp-sp-2.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-1.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-1.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-1.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-2.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-2.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-2.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-3.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-3.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-3.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-4.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-4.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-4.s: New test.
* gas/scfi/x86_64/scfi-cfg-1.d: New test.
* gas/scfi/x86_64/scfi-cfg-1.l: New test.
* gas/scfi/x86_64/scfi-cfg-1.s: New test.
* gas/scfi/x86_64/scfi-cfg-2.d: New test.
* gas/scfi/x86_64/scfi-cfg-2.l: New test.
* gas/scfi/x86_64/scfi-cfg-2.s: New test.
* gas/scfi/x86_64/scfi-cfi-label-1.d: New test.
* gas/scfi/x86_64/scfi-cfi-label-1.l: New test.
* gas/scfi/x86_64/scfi-cfi-label-1.s: New test.
* gas/scfi/x86_64/scfi-cfi-sections-1.d: New test.
* gas/scfi/x86_64/scfi-cfi-sections-1.l: New test.
* gas/scfi/x86_64/scfi-cfi-sections-1.s: New test.
* gas/scfi/x86_64/scfi-cofi-1.d: New test.
* gas/scfi/x86_64/scfi-cofi-1.l: New test.
* gas/scfi/x86_64/scfi-cofi-1.s: New test.
* gas/scfi/x86_64/scfi-diag-1.l: New test.
* gas/scfi/x86_64/scfi-diag-1.s: New test.
* gas/scfi/x86_64/scfi-diag-2.l: New test.
* gas/scfi/x86_64/scfi-diag-2.s: New test.
* gas/scfi/x86_64/scfi-dyn-stack-1.d: New test.
* gas/scfi/x86_64/scfi-dyn-stack-1.l: New test.
* gas/scfi/x86_64/scfi-dyn-stack-1.s: New test.
* gas/scfi/x86_64/scfi-enter-1.d: New test.
* gas/scfi/x86_64/scfi-enter-1.l: New test.
* gas/scfi/x86_64/scfi-enter-1.s: New test.
* gas/scfi/x86_64/scfi-fp-diag-2.l: New test.
* gas/scfi/x86_64/scfi-fp-diag-2.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-1.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-1.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-1.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-2.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-2.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-2.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-3.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-3.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-3.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-4.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-4.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-4.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-5.s: New test.
* gas/scfi/x86_64/scfi-lea-1.d: New test.
* gas/scfi/x86_64/scfi-lea-1.l: New test.
* gas/scfi/x86_64/scfi-lea-1.s: New test.
* gas/scfi/x86_64/scfi-leave-1.d: New test.
* gas/scfi/x86_64/scfi-leave-1.l: New test.
* gas/scfi/x86_64/scfi-leave-1.s: New test.
* gas/scfi/x86_64/scfi-pushq-1.d: New test.
* gas/scfi/x86_64/scfi-pushq-1.l: New test.
* gas/scfi/x86_64/scfi-pushq-1.s: New test.
* gas/scfi/x86_64/scfi-pushsection-1.d: New test.
* gas/scfi/x86_64/scfi-pushsection-1.l: New test.
* gas/scfi/x86_64/scfi-pushsection-1.s: New test.
* gas/scfi/x86_64/scfi-pushsection-2.d: New test.
* gas/scfi/x86_64/scfi-pushsection-2.l: New test.
* gas/scfi/x86_64/scfi-pushsection-2.s: New test.
* gas/scfi/x86_64/scfi-selfalign-func-1.d: New test.
* gas/scfi/x86_64/scfi-selfalign-func-1.l: New test.
* gas/scfi/x86_64/scfi-selfalign-func-1.s: New test.
* gas/scfi/x86_64/scfi-simple-1.d: New test.
* gas/scfi/x86_64/scfi-simple-1.l: New test.
* gas/scfi/x86_64/scfi-simple-1.s: New test.
* gas/scfi/x86_64/scfi-simple-2.d: New test.
* gas/scfi/x86_64/scfi-simple-2.l: New test.
* gas/scfi/x86_64/scfi-simple-2.s: New test.
* gas/scfi/x86_64/scfi-sub-1.d: New test.
* gas/scfi/x86_64/scfi-sub-1.l: New test.
* gas/scfi/x86_64/scfi-sub-1.s: New test.
* gas/scfi/x86_64/scfi-sub-2.d: New test.
* gas/scfi/x86_64/scfi-sub-2.l: New test.
* gas/scfi/x86_64/scfi-sub-2.s: New test.
* gas/scfi/x86_64/scfi-unsupported-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-1.s: New test.
* gas/scfi/x86_64/scfi-unsupported-2.l: New test.
* gas/scfi/x86_64/scfi-unsupported-2.s: New test.
* gas/scfi/x86_64/scfi-unsupported-3.l: New test.
* gas/scfi/x86_64/scfi-unsupported-3.s: New test.
* gas/scfi/x86_64/scfi-unsupported-4.l: New test.
* gas/scfi/x86_64/scfi-unsupported-4.s: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-1.s: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-2.l: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-2.s: New test.
* gas/scfi/x86_64/scfi-unsupported-drap-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-drap-1.s: New test.
* gas/scfi/x86_64/scfi-unsupported-insn-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-insn-1.s: New test.
* gas/scfi/x86_64/scfi-x86-64.exp: New file.
Add a new listing option, -i, to emit ginsn in the listing output. We
may also emit other SCFI information if necessary in the future.
ginsn are most useful when seen alongside the assembly instructions.
Hence, they are emitted when the user includes the assembly instructions
in the listing output, i.e., "-ali=FILE".
gas/doc/:
* as.texi: Add documentation for the new listing option, -i.
This patch adds support in GAS to create generic GAS instructions
(a.k.a., the ginsn) for the x86 backend (AMD64 ABI only at this time).
Using this ginsn infrastructure, GAS can then synthesize CFI for
hand-written asm for x86_64.
A ginsn is a target-independent representation of the machine
instructions. One machine instruction may need one or more ginsn.
This patch also adds skeleton support for printing ginsn in the listing
output for debugging purposes.
Since the current use-case of ginsn is to synthesize CFI, the x86 target
needs to generate ginsns necessary for the following machine
instructions only:
- All change of flow instructions, including all conditional and
unconditional branches, call and return from functions.
- All register saves and unsaves to the stack.
- All instructions affecting the two registers that could potentially
be used as the base register for CFA tracking. For SCFI, the base
register for CFA tracking is limited to REG_SP and REG_FP only for
now.
The representation of ginsn is kept simple:
- GAS instruction has GINSN_NUM_SRC_OPNDS (defined to be 2 at this time)
number of source operands and one destination operand at this time.
- GAS instruction uses DWARF register numbers in its representation and
does not track register size.
- GAS instructions carry location information (file name and line
number).
- GAS instructions are ID's with a natural number in order of their
addtion to the list. This can be used as a proxy for the static
program order of the corresponding machine instructions.
Note that, GAS instruction (ginsn) format does not support
GINSN_TYPE_PUSH and GINSN_TYPE_POP. Some architectures, like aarch64,
do not have push and pop instructions, but rather STP/LDP/STR/LDR etc.
instructions. Further these instructions have a variety of addressing
modes, like offset, pre-indexing and post-indexing etc. Among other
things, one of differences in these addressing modes is _when_ the addr
register is updated with the result of the address calculation: before
or after the memory operation. To best support such needs, the generic
instructions like GINSN_TYPE_LOAD, GINSN_TYPE_STORE together with
GINSN_TYPE_ADD, and GINSN_TYPE_SUB may be used.
The functionality provided in ginsn.c and scfi.c is compiled in when a
target defines TARGET_USE_SCFI and TARGET_USE_GINSN. This can be
revisited later when there are other use-cases of creating ginsn's in
GAS, apart from the current use-case of synthesizing CFI for
hand-written asm.
Support is added only for System V AMD64 ABI for ELF at this time. If
the user enables SCFI with --32, GAS issues an error:
"Fatal error: SCFI is not supported for this ABI"
For synthesizing (DWARF) CFI, the SCFI machinery requires the programmer
to adhere to some pre-requisites for their asm:
- Hand-written asm block must begin with a .type foo, @function
It is highly recommended to, additionally, also ensure that:
- Hand-written asm block ends with a .size foo, .-foo
The SCFI machinery encodes some rules which align with the standard
calling convention specified by the ABI. Apart from the rules, the SCFI
machinery employs some heuristics. For example:
- The base register for CFA tracking may be either REG_SP or REG_FP.
- If the base register for CFA tracking is REG_SP, the precise amount of
stack usage (and hence, the value of REG_SP) must be known at all times.
- If using dynamic stack allocation, the function must switch to
FP-based CFA. This means using instructions like the following (in
AMD64) in prologue:
pushq %rbp
movq %rsp, %rbp
and analogous instructions in epilogue.
- Save and Restore of callee-saved registers must be symmetrical.
However, the SCFI machinery at this time only warns if any such
asymmetry is seen.
These heuristics/rules are architecture-independent and are meant to
employed for all architectures/ABIs using SCFI in the future.
gas/
* Makefile.am: Add new files.
* Makefile.in: Regenerated.
* as.c (defined): Handle documentation and listing option for
ginsns and SCFI.
* config/obj-elf.c (obj_elf_size): Invoke ginsn_data_end.
(obj_elf_type): Invoke ginsn_data_begin.
* config/tc-i386.c (x86_scfi_callee_saved_p): New function.
(ginsn_prefix_66H_p): Likewise.
(ginsn_dw2_regnum): Likewise.
(x86_ginsn_addsub_reg_mem): Likewise.
(x86_ginsn_addsub_mem_reg): Likewise.
(x86_ginsn_alu_imm): Likewise.
(x86_ginsn_move): Likewise.
(x86_ginsn_lea): Likewise.
(x86_ginsn_jump): Likewise.
(x86_ginsn_jump_cond): Likewise.
(x86_ginsn_enter): Likewise.
(x86_ginsn_safe_to_skip): Likewise.
(x86_ginsn_unhandled): Likewise.
(x86_ginsn_new): New functionality to generate ginsns.
(md_assemble): Invoke x86_ginsn_new.
(s_insn): Likewise.
(i386_target_format): Add hard error for usage of SCFI with non AMD64 ABIs.
* config/tc-i386.h (TARGET_USE_GINSN): New definition.
(TARGET_USE_SCFI): Likewise.
(SCFI_MAX_REG_ID): Likewise.
(REG_FP): Likewise.
(REG_SP): Likewise.
(SCFI_INIT_CFA_OFFSET): Likewise.
(SCFI_CALLEE_SAVED_REG_P): Likewise.
(x86_scfi_callee_saved_p): Likewise.
* gas/listing.h (LISTING_GINSN_SCFI): New define for ginsn and
SCFI.
* gas/read.c (read_a_source_file): Close SCFI processing at end
of file read.
* gas/scfidw2gen.c (scfi_process_cfi_label): Add implementation.
(scfi_process_cfi_signal_frame): Likewise.
* subsegs.h (struct frch_ginsn_data): New forward declaration.
(struct frchain): New member for ginsn data.
* gas/subsegs.c (subseg_set_rest): Initialize the new member.
* symbols.c (colon): Invoke ginsn_frob_label to convey
user-defined labels to ginsn infrastructure.
* ginsn.c: New file.
* ginsn.h: New file.
* scfi.c: New file.
* scfi.h: New file.
Rex2 is currently an operand constraint. For the upcoming SCFI
implementation in GAS, we need to identify operations which implicitly
update the stack pointer. An operand constraint enumerator for implicit
stack op seems more appropriate than an attribute. However, two opcodes
currently necessitate both Rex2 and an implicit stack op marker; this
prompts revisiting the current representations a bit.
Make Rex2 a standalone attribute, so that later a new operand constraint
may be added for IMPLICIT_STACK_OP.
ChangeLog:
* gas/config/tc-i386.c (is_apx_rex2_encoding): Update the check.
* opcodes/i386-gen.c: Add a new BITFIELD for Rex2.
* opcodes/i386-opc.h (REX2_REQUIRED): Remove.
* opcodes/i386-opc.tbl: Remove Rex2 operand constraint.
* opcodes/i386-tbl.h: Regenerated.
Define a new set of handlers for CFI directives for the purpose of SCFI.
The SCFI machinery ignores many of the user-specified CFI direcives when
SCFI is in effect. A warning ("Warning: SCFI ignores most
user-specified CFI directives") is issued once per file. The following
CFI directives, however, are not ignored:
- .cfi_sections
- .cfi_label
- .cfi_signal_frame
gas/
* Makefile.am: Add new files to GAS_CFILES and HFILES.
* Makefile.in: Likewise.
* gas/read.c (scfi_pop_insert): New define.
(pobegin): Use the SCFI handlers.
* scfidw2gen.c: New file.
* scfidw2gen.h: New file.
When the command line option --scfi=experimenta is passed to the GNU
assembler, it will synthesize DWARF call frame information (CFI) for the
input assembly.
The option --scfi=experimental will also ignore most of the existing
.cfi_* directives, if already contained in the provided input file.
Only the following CFI directives will not be ignored:
- .cfi_sections,
- .cfi_label,
- .cfi_signal_frame
To use SCFI, a target will need to:
- define TARGET_USE_SCFI and TARGET_USE_GINSN, and other necessary
definitions,
- provide means to help GAS understand the target specific instruction
semantics by creating ginsns.
The upcoming support for SCFI is inteded to be experimental, hence the
option --scfi=experimental. The --scfi= may see more options like
--scfi=[all,none] added in future, once the SCFI support in GAS is
mature and robust. The offering may also see for example, an
--scfi=inline option for dealing with inline asm may be added in the
future. In --scfi=inline option, the GNU assembler may consume (and not
ignore) the compiler generated CFI for the code surrounding the inline
asm.
Also document the option.
gas/
* as.c (show_usage): Add support for --scfi=experimental.
(parse_args): Likewise.
* as.h (enum synth_cfi_type): Define new type.
* doc/as.texi: Document the new option.
scfidw2gen will use this for processing the .cfi_sections directive.
gas/
* dw2gencfi.c (dot_cfi_sections): Not static anymore.
* dw2gencfi.h (dot_cfi_sections): Mark as extern.
Move the following three defines to the header file, so the SCFI
machinery can use them:
- tc_cfi_frame_initial_instructions
- tc_cfi_startproc
- tc_cfi_endproc
gas/
* dw2gencfi.c: Move from ...
* dw2gencfi.h: ... to here.
The code in dw2gencfi.c was checking variable cfi_sections and
all_cfi_sections seemingly randomly. Accessing all_cfi_sections seems
to the correct variable to access.
The data in cfi_sections has already been propagated to all_cfi_sections
once cfi_dot_startproc () has been called.
gas/
* dw2gencfi.c (dot_cfi_startproc): Use all_cfi_sections
instead.
(dot_cfi_endproc): Likewise.
(dot_cfi_fde_data): Likewise.
cfi_sections_set is best set to true in cfi_dot_startproc (). Setting
it to true again in other APIs (dot_cfi_endproc, dot_cfi_fde_data, and
cfi_finish) is unnecessary. Also, move setting the global var
all_cfi_sections into cfi_set_sections ().
gas/
* dw2gencfi.c (cfi_set_sections): Set cfi_sections_set and
cfi_sections here.
(dot_cfi_startproc): Remove unnecessarily setting
cfi_set_sections to true.
(dot_cfi_endproc): Likewise.
(dot_cfi_fde_data): Likewise.
(cfi_finish): Likewise.
Relocations installed by the BPF ELF backend were sometimes incorrectly
adding the symbol value to the relocation entry addend, when the correct
relocation value was already stored in the addend. This could lead to a
relocation effectively adding the symbol value twice.
Fix that by making bpf_elf_generic_reloc () more similar to the flow of
bfd_install_relocation in the case where howto->install_addend is set,
which is how it ought to behave.
bfd/
* bpf-reloc.def (R_BPF_64_ABS32, R_BPF_64_ABS64)
(R_BPF_64_NODYLD32): Set partial_inplace to true.
* elf64-bpf.c (bpf_elf_generic_reloc): Do not include the value
of the symbol when installing relocation. Copy some additional
logic from bfd_elf_generic_reloc.
gas/
* testsuite/gas/bpf/bpf.exp: Run new test.
* testsuite/gas/bpf/elf-relo-1.d: New.
* testsuite/gas/bpf/elf-relo-1.s: New.
Additionally, change FEAT_XS tlbi variants to be gated on "+xs" instead of
"+d128". This is an incremental improvement; there are still some FEAT_XS tlbi
variants that are gated incorrectly or missing entirely.
Fix PR gas/31213.
gas/
PR gas/31213
* gen-sframe.c (sframe_do_cfi_insn): Add new warning.
gas/testsuite/
* gas/cfi-sframe/common-empty-1.d: Test the new warning as well.
* gas/cfi-sframe/common-empty-2.d: Likewise.
Due to the formatted output of objdump, some instructions
that do not require output operands (such as nop/ret) will
have extra spaces added after them.
Determine whether to output operands through the format
of opcodes. When opc->format is an empty string, no extra
spaces are output.
This patch adds support for the new AArch64 system registers that are part of the following extensions:
* FEAT_DEBUGv8p9
* FEAT_PMUv3p9
* FEAT_PMUv3_SS
* FEAT_PMUv3_ICNTR
* FEAT_SEBEP
As already indicated during review, we can't get away without certain
adjustments here: Without these, respective {evex}-prefixed insns are
assembled to APX encodings even when APX_F is turned off.
While there also extend the respective comment in the opcode table, to
explain why this construct is used.
PR gas/31178
In da0784f961 ("x86: fold FMA VEX and EVEX templates") I overlooked
that C aliases StaticRounding, and hence build_vex_prefix() now needs to
be aware of that aliasing. Disambiguation is easy, as StaticRounding is
only ever used together with SAE (hence why the overlaying works in the
first place).
This patch adds support for FEAT_THE doubleword and quadword instructions.
doubleword insturctions are enabled by "+the" flag whereas quadword
instructions are enabled on passing both "+the and +d128" flags.
Support for following sets of instructions is added in this patch.
Read check write compare and swap doubleword:
(rcwcas, rcwcasa, rcwcasal, rcwcasl)
Read check write compare and swap quadword:
(rcwcasp,rcwcaspa, rcwcaspal, rcwcaspl)
Read check write software compare and swap doubleword:
(rcwscas, rcwscasa, rcwscasal, rcwscasl)
Read check write software compare and swap quadword:
(rcwscasp, rcwscaspa, rcwscaspal, rcwscaspl)
Read check write atomic bit clear on doubleword:
(rcwclr, rcwclra, rcwclral, rcwclrl)
Read check write atomic bit clear on quadword:
(rcwclrp, rcwclrpa, rcwclrpal, rcwclrpl)
Read check write software atomic bit clear on doubleword:
(rcwsclr, rcwsclra, rcwsclral, rcwsclrl)
Read check write software atomic bit clear on quadword:
(rcwsclrp,rcwsclrpa, rcwsclrpal,rcwsclrpl)
Read check write atomic bit set on doubleword:
(rcwset,rcwseta, rcwsetal,rcwsetl)
Read check write atomic bit set on quadword:
(rcwsetp,rcwsetpa,rcwsetpal,rcwsetpl)
Read check write software atomic bit set on doubleword:
(rcwsset,rcwsseta,rcwssetal,rcwssetl)
Read check write software atomic bit set on quadword:
(rcwssetp,rcwssetpa,rcwssetpal,rcwssetpl)
Read check write swap doubleword:
(rcwswp,rcwswpa,rcwswpal,rcwswpl)
Read check write swap quadword:
(rcwswpp,rcwswppa, rcwswppal,rcwswppl)
Read check write software swap doubleword:
(rcwsswp,rcwsswpa,rcwsswpal,rcwsswpl)
Read check write software swap quadword:
(rcwsswpp,rcwsswppa,rcwsswppal,rcwsswppl)
Add tests to cover the full range of behaviors observed around
optional register operands for the `tlbip' and `sysp' instructions,
namely:
* Not all `tlbip' operations take GPR operands. When this is the
case, we should check that neither optional operand was supplied.
* When a `tlbip' operation is labeled with the `F_HASXT' flag, xzr
is not a valid optional operand. In such case, at least the fist
optional register needs to be specified with a non-xzr value.
* The first operand for both insns should be either xzr or an
even-numbered register (n % 2 == 0). In the former scenario, the
second operand should default to xzr too, while in the latter, it
should default to n + 1.
With the addition of 128-bit system registers to the Arm architecture
starting with Armv9.4-a, a mechanism for manipulating their contents
is introduced with the `msrr' and `mrrs' instruction pair.
These move values from one such 128-bit system register into a pair of
contiguous general-purpose registers and vice-versa, as for example:
msrr ttlb0_el1, x0, x1
mrrs x0, x1, ttlb0_el1
This patch adds the necessary support for these instructions, adding
checks for system-register width by defining a new operand type in the
form of `AARCH64_OPND_SYSREG128' and the `aarch64_sys_reg_128bit_p'
predicate, responsible for checking whether the requested system
register table entry is marked as implemented in the 128-bit mode via
the F_REG_128 flag.
The addition of 128-bit page table descriptors and, with it, the
addition of 128-bit system registers for these means that special
"invalidate translation table entry" instructions are needed to cope
with the new 128-bit model. This is introduced with the `tlbpi'
instruction, implemented here.
While CRn and CRm fields in the SYSP instruction are 4-bit wide and
are thus able to accommodate values in the range 0-15, the
specifications for the SYSP instructions limit their ranges to 8-9 for
CRm and 0-7 in the case of CRn.
This led to the need to signal in some way to the operand parser that
a given operand is under special restrictions regarding its use. This
is done via the new `F_OPD_NARROW' flag, indicating a narrowing in the
range of operand values for fields in the instruction tagged with the
flag.
The flag is then used in `parse_operands' when the instruction is
assembled, but needs not be taken into consideration during
disassembly.
Mirroring the use of the `sys' - System Instruction assembly
instruction, this implements its 128-bit counterpart, `sysp'.
This optionally takes two contiguous general-purpose registers
starting at an even number or, when these are omitted, by default
sets both of these to xzr.
Syntax:
sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>}
Two of the instructions added by the `+d128' architectural extension
add the flexibility to have two optional operands. Prior to the
addition of the `tlbip' and `sysp' instructions, no mnemonic allowed
more than one such optional operand.
With `tlbip' as an example, some TLBIP instruction names do not allow
for any optional operands, while others allow for both to be optional.
In the latter case, it is possible that either the second operand
alone is omitted or both operands are omitted.
Therefore, a considerable degree of flexibility needed to be added to
the way operands were parsed. It was, however, possible to achieve
this with relatively few changes to existing code.
it is noteworthy that opcode flags specifying the optional operand
number are non-orthogonal. For example, we have:
#define F_OPD1_OPT (2 << 12) : 0b10 << 12
#define F_OPD2_OPT (3 << 12) : 0b11 << 12
such that by virtue of the observation that
(F_OPD1_OPT | F_OPD2_OPT) == F_OPD2_OPT
it is impossible to mark both operands 1 and 2 as optional for an
instruction and it is assumed that a maximum of 1 operand can ever be
optional. This is not overly-problematic given that, for optional
pairs, the second optional operand is always found immediately after
the first. Thus, it suffices for us to flag that there is a second
optional operand. With this fact, we can infer its position in the
mnemonic from the position of the first (e.g. if the second operand in
the mnemonic is optional, we know the third is too). We therefore
define the `F_OPD_PAIR_OPT' flag and calculate its position in the
mnemonic from the value encoded by the `F_OPD<n>_OPT' flag.
Another observation is that there is a tight coupling between default
values assigned to the two registers when one (or both) are omitted
from the mnemonic. Namely, if Xt1 has a value of 0x1f (the zero
register is specified), Xt2 defaults to the same value, otherwise Xt2
will be assigned Xt + 1. This meant that where you have default value
validation, in checking the second optional operand's value, it is
also necessary to look at the value assigned to the
previously-processed operand value before deciding its validity. Thus
`process_omitted_operand' needs not only access to its `operand'
argument, but also to the global `inst' struct.
Analysis of the allowed operand values for `sysp' and `tlbip' reveals
a significant departure from the allowed behavior for operand register
pairs (hitherto labeled AARCH64_OPND_PAIRREG) observed for other
insns in this category.
For instructions `casp', `mrrs' and `msrr' the register pair must
always start at an even index and the second register in the pair is
the index + 1. This precludes the use of xzr as the first register,
given it corresponds to register number 31.
This is different in the case of `sysp' and `tlbip', however. These
allow the use of xzr and, where the first operand in the pair is
omitted, this is the default value assigned to it. When this
operand is assigned xzr, it is expected that the second operand will
likewise take on a value of xzr.
These two instructions therefore "break" two rules of register pairs:
* The first of the two registers is odd-numbered.
* The index of the second register is equal to that of the first,
and not n+1.
To allow for this departure from hitherto standard behavior, we
extend the functionality of the assembler by defining an extension of
the AARCH64_OPND_PAIRREG, called AARCH64_OPND_PAIRREG_OR_XZR.
It is used in defining `sysp' and `tlbip' and allows
`operand_general_constraint_met_p' to allow the pair to both take on
the value of xzr.
Indicating the presence of the Armv9.4-a features concerning 128-bit
Page Table Descriptors, 128-bit System Registers and Instructions,
the "+d128" architectural extension flag is added to the list of
possible -march options in Binutils, together with the necessary macro
for encoding d128 instructions.
Currently, only mipsisa32-linux and mipsisa32el-linux is marked
as addr32, which make mipsisa32rN(el) not marked.
This change can fix 2 test failures on mipsisa32rN(el)-linux:
FAIL: MIPS MIPS64 MIPS-3D ASE instructions (-mips3d flag)
FAIL: MIPS MIPS64 MDMX ASE instructions (-mdmx flag)
These failures don't happen for mipsisa32rN-mti-elf etc,
due to that, the output is set as NO_ABI instead of O32, then
gas won't warn:
`fp=64' used with a 32-bit ABI
Maybe, we should change this behaivour in future.
This patch adds AArch32 support for -march=armv8.9-a and
-march=armv9.4-a. The behaviour of the new options can be
expressed using a combination of existing feature flags
and tables.
The cpu_arch_ver entries for ARM_ARCH_V9_4A and ARM_ARCH_V8_9A
are technically redundant but it including them for macro code
consistency across architectures.
Also recognized are aarch64-*-gnu tagrets, e.g. aarch64-pc-gnu or
aarch64-unknown-gnu.
The ld/emulparams/aarch64gnu.sh file is (for now) identical to aarch64fbsd.sh,
or to aarch64linux.sh with Linux-specific logic removed; and mainly different
from the generic aarch64elf.sh in that it does not set EMBEDDED=yes.
Coupled with a corresponding GCC patch, this produces a toolchain that can
sucessfully build working binaries targeting aarch64-gnu.
Signed-off-by: Sergey Bugaev <bugaevc@gmail.com>
Since 0x66 is the opcode prefix for adcx, it is wrong to use the 'S'
prefix:
'S' => print 'w', 'l' or 'q' if suffix_always is true
on adcx. Add
'L' => print 'l' or 'q' if suffix_always is true
replace S with L on adcx and adox.
gas/
PR binutils/31219
* testsuite/gas/i386/suffix.d: Updated.
* testsuite/gas/i386/x86-64-suffix.d: Likewise.
* testsuite/gas/i386/suffix.s: Add tests for adcx and adox.
* testsuite/gas/i386/x86-64-suffix.s: Likewise.
opcodes/
PR binutils/31219
* i386-dis.c: Add the 'L' suffix.
(prefix_table): Replace S with L on adcx and adox.
(putop): Handle the 'L' suffix.
There are a number of issues with 734dfd1cc9 ("x86: pack CPU flags in
opcode table"):
- the condition when two array slots need writing wasn't correct (with
enough new Cpu* added an out of bounds array access would validly have
been complained about by the compiler),
- table generation didn't take into account CpuAttrUnused and CpuUnused
being independent, and hence there not always (not) being an "unused"
bitfield member in both structures,
- cpu_flags_from_attr() wasn't ready for use on big-endian hosts,
- there were two style violations.
Various targets have / had overrides for .bss. Make sure that in such
cases
- .previous still works correctly (requiring such targets to invoke
obj_elf_section_change_hook() from their overriding handlers),
- sub-section specifiers are accepted as far as feasible (mandated by
the doc).
It doesn't look to be a good idea to override the custom handlers that
ELF and COFF have; afaict doing so broke .previous on ELF, and a sub-
section specifier wasn't accepted either.
The comment in s_bss() looks bogus (perhaps simply stale, or wrongly
copied from another target). It also doesn't look to be a good idea to
override the custom handler that ELF has (afaict doing so broke
.previous as well as sub-section specification).
The override for .skip is simply pointless, for read.c having exactly
the same.
While there also drop two adjacent redundant (with read.h) declarations
(which would be outright dangerous if read.h wasn't included anyway).
While there doesn't look to be anything wrong with this override,
there's also no apparent reason why this override would be needed. Drop
it, reducing overall size a tiny bit.
The comment looks bogus (perhaps simply stale, or wrongly copied from
another target). It also doesn't look to be a good idea to override the
custom handler that ELF has (afaict doing so broke .previous as well as
sub-section specification).
While there also fold the identical handlers for .text (there likely is
more room for such folding).
The comment looks bogus (perhaps simply stale), and there are also no
other precautions against subsections being used on ELF with .bss. It
also doesn't look to be a good idea to override the custom handler that
ELF has (afaict doing so further broke .previous).
While only ELF is supported right now, (stub) code generally is in place
for the non-ELF case as well. Don't override .bss for ELF - that's
unlikely to be a good idea anyway and prevented the sub-section
specifier from being usable. Don't override .text and .data at all - for
.data and ELF for the same reason, while for .text and ELF obj-elf.c's is
all we need, and for (hypothetical) non-ELF read.c's identical handling
would have been invoked anyway.
The comment looks bogus (perhaps simply stale), and there are also no
other precautions against subsections being used on ELF with .bss. It
also doesn't look to be a good idea to override the custom handler that
ELF has (afaict doing so further broke .previous).
It doesn't look to be a good idea to override the custom handlers that
ELF and COFF have. While in this case interaction with ELF's .previous
wasn't screwed, the sub-section specifier wasn't permitted.
The comment looks bogus (perhaps simply stale, perhaps wrongly copied
from Arm in the first place), and there are also no other precautions
against subsections being used on ELF with .bss. It also doesn't look
to be a good idea to override the custom handlers that ELF and COFF
have (afaict doing so further broke .previous on ELF).
As to the mapping state update - such also doesn't appear to be done
for other section switching, so its original purpose was at best
questionable as well.
The comment looks bogus (perhaps simply stale), and there are also no
other precautions against subsections being used on ELF with .bss. It
also doesn't look to be a good idea to override the custom handlers that
ELF and COFF have (afaict doing so further broke .previous on ELF).
Since the particularity of "th.vsetvli" was not taken into account in the
initial support patches for XTheadVector, the program operation failed
due to instruction coding errors. According to T-Head SPEC ([1]), the
"vsetvl" in the XTheadVector extension consists of SEW, LMUL and EDIV,
which is quite different from the "V" extension. Therefore, we cannot
simply reuse the processing of vsetvl in V extension.
We have set up tens of thousands of test cases to ensure that no
further encoding issues are there, and and execute all compiled test
files on real HW and make sure they don't trigger SIGILL.
Ref:
[1] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Add handling for
th.vsetvli.
(my_getThVsetvliExpression): New function.
(riscv_ip): Likewise.
* testsuite/gas/riscv/x-thead-vector.d: Likewise.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv.h (OP_MASK_XTHEADVLMUL): New macro.
(OP_SH_XTHEADVLMUL): Likewise.
(OP_MASK_XTHEADVSEW): Likewise.
(OP_SH_XTHEADVSEW): Likewise.
(OP_MASK_XTHEADVEDIV): Likewise.
(OP_SH_XTHEADVEDIV): Likewise.
(OP_MASK_XTHEADVTYPE_RES): Likewise.
(OP_SH_XTHEADVTYPE_RES): Likewise.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Likewise.
* riscv-opc.c: Likewise.
Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:
1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
author I haven't committed, 'Kalray SA.', to cover gas testsuite
files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
Suppose we want to use la.got to generate 32 pcrel and
32 abs instruction sequences respectively. According to
the existing conditions, to generate 32 pcrel sequences
use -mabi=ilp32*, and to generate 32 abs use -mabi=ilp32*
and -mla-global-with-abs.
Due to the fact that the conditions for generating 32 abs
also satisfy 32 pcrel, using -mabi=ilp32* and -mla-global-with-abs
will result in only generating instruction sequences of 32 pcrel.
By modifying the conditions for macro expansion and adjusting
the matching order of macro instructions, it is ensured that
the correct sequence of instructions can be generated.
Append "#pass" to APX tests for targets which pad text sections with NOPs.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Append
"#pass".
* testsuite/gas/i386/x86-64-apx-ndd-optimize.d: Likewise.
* testsuite/gas/i386/x86-64-apx-ndd.d: Likewise.
* testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: Likewise.
* testsuite/gas/i386/x86-64-apx-pushp-popp.d: Likewise.
'/' starts a comment for some targets. Use .byte instead of .insn with
'/'.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Use .byte
instead of .insn with '/'.
commit 3d5a60de52
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Thu Jun 8 10:01:03 2023 -0700
x86-64: Add R_X86_64_CODE_4_GOTPCRELX
added a new field, fx_tcbit3, to fix. But it didn't initialize it.
Fix it by clearing it in fix_new_internal.
* wrtite.c (fix_new_internal): Clear fx_tcbit3.
Add tls le relax related relocs support and testsuites in gas.
The main test is three new relocation items,
R_LARCH_TLS_LE_ADD_R, R_LARCH_TLS_LE_HI20_R,
R_LARCH_TLS_LE_LO12_R can be generated properly
and tls le insn format check.
gas/ChangeLog:
* config/tc-loongarch.c:
(loongarch_args_parser_can_match_arg_helper): Add support for relax.
* gas/testsuite/gas/loongarch/reloc.d: Likewise.
* gas/testsuite/gas/loongarch/reloc.s: Likewise.
* gas/testsuite/gas/loongarch/loongarch.exp: Likewise.
* gas/testsuite/gas/loongarch/tls_le_insn_format_check.s: New test.
In order to make it easier to complete the compiler's support for
the XTheadVector extension and to be as compatible as possible
with the programming model of the 'V' extension ([1]), we consider
adding a few pseudo instructions ([2]).
th.vmmv.m vd,vs => th.vmand.mm vd,vs,vs
th.vneg.v vd,vs => th.vrsub.vx vd,vs,x0
th.vncvt.x.x.v vd,vs,vm => th.vnsrl.vx vd,vs,x0,vm
th.vfneg.v vd,vs => th.vfsgnjn.vv vd,vs,vs
th.vfabs.v vd,vs => th.vfsgnjx.vv vd,vs,vs
Ref:
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641302.html
[2] https://github.com/T-head-Semi/thead-extension-spec/pull/40
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for new
pseudoinstructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
opcodes/ChangeLog:
* riscv-opc.c: Add new pseudoinstructions.
For
add name@gottpoff(%rip), %reg
mov name@gottpoff(%rip), %reg
add
# define R_X86_64_CODE_4_GOTTPOFF 44
and for
lea name@tlsdesc(%rip), %reg
add
# define R_X86_64_CODE_4_GOTPC32_TLSDESC 45
if the instruction starts at 4 bytes before the relocation offset.
They are similar to R_X86_64_GOTTPOFF and R_X86_64_GOTPC32_TLSDESC,
respectively. Linker can covert GOTTPOFF to
add $name@tpoff, %reg
mov $name@tpoff, %reg
and GOTPC32_TLSDESC to
mov $name@tpoff, %reg
mov name@gottpoff(%rip), %reg
if the instruction is encoded with the REX2 prefix when possible.
bfd/
* elf64-x86-64.c (x86_64_elf_howto_table): Add
R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC.
(R_X86_64_standard): Updated.
(x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF
and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC.
(elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_4_GOTTPOFF
and R_X86_64_CODE_4_GOTPC32_TLSDESC.
(elf_x86_64_tls_transition): Likewise.
(elf_x86_64_scan_relocs): Likewise.
(elf_x86_64_relocate_section): Likewise.
* reloc.c (bfd_reloc_code_real): Add
BFD_RELOC_X86_64_CODE_4_GOTTPOFF and
BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC.
* bfd-in2.h: Regenerated.
* libbfd.h: Likewise.
gas/
* config/tc-i386.c (tc_i386_fix_adjustable): Handle
BFD_RELOC_X86_64_CODE_4_GOTTPOFF and
BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC.
(md_assemble): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF.
(output_insn): Don't add empty REX prefix with REX2 prefix.
(output_disp): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and
BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC.
(md_apply_fix): Likewise.
(i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTTPOFF or
BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC if ixp->fx_tcbit3 is set.
(tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and
BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC.
* testsuite/gas/i386/x86-64-gottpoff.d: New file.
* testsuite/gas/i386/x86-64-gottpoff.s: Likewise.
* testsuite/gas/i386/x86-64-tlsdesc.d: Likewise.
* testsuite/gas/i386/x86-64-tlsdesc.s: Likewise.
include/
* elf/x86-64.h (elf_x86_64_reloc_type): Add
R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC
ld/
* testsuite/ld-x86-64/tlsbindesc.d: Updated.
* testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
* testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_4_GOTTPOFF
and R_X86_64_CODE_4_GOTPC32_TLSDESC tests.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* testsuite/gas/i386/x86-64-apx-egpr-inval.l: Add some insn don't
support gpr32.
* testsuite/gas/i386/x86-64-apx-egpr-inval.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add new test.
* testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: New test.
* testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-egpr.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-egpr.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: New test.
* testsuite/gas/i386/x86-64-apx-evex-promoted.s: New test.
This patch adds non-ND, non-NF forms of EVEX promotion insn.
EVEX extension of legacy instructions:
All promoted legacy instructions are placed in EVEX map 4, which is
currently reserved.
EVEX extension of EVEX instructions:
All existing EVEX instructions are extended by APX using the extended
EVEX prefix, so that they can access all 32 GPRs.
EVEX extension of VEX instructions:
Promoting a VEX instruction into the EVEX space does not change the map
id, the opcode, or the operand encoding of the VEX instruction.
Note: The promoted versions of MOVBE will be extended to include the “MOVBE
reg1, reg2”.
gas/ChangeLog:
2023-12-28 Lingling Kong <lingling.kong@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Lili Cui <lili.cui@intel.com>
Lin Hu <lin1.hu@intel.com>
* config/tc-i386.c (struct _i386_insn): Add has_egpr.
(need_evex_encoding): Adjusted for apx.
(cpu_flags_match): Ditto.
(install_template): Handled APX combines.
(is_apx_evex_encoding): Test apx evex encoding.
(build_apx_evex_prefix): Enabe APX evex prefix.
(md_assemble): Handle apx with evex encoding.
(process_suffix): Handle apx map4 prefix.
(check_register): Assign i.vec_encoding for APX evex instructions.
* testsuite/gas/i386/x86-64-evex.d: Adjust test cases.
* testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe.
opcodes/ChangeLog:
* i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3.
* i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0,
PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8,
PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB,
PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD,
PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF,
PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1,
PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8.
* i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0.
* i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn
promote to apx to use gpr32
* opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90,
X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2,
X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6,
X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91.
* i386-dis.c
(struct instr_info): Deleted bool r.
(PREFIX_NP_OR_DATA): New.
(NO_PREFIX): New.
(putop): Ditto.
(X86_64_EVEX_FROM_VEX_TABLE): Diito.
(get_valid_dis386): Decode insn erex in extend evex prefix.
Handle EVEX_MAP4
(print_insn): Handle PREFIX_DATA_AND_NP_ONLY.
(print_register): Handle apx instructions decode.
(OP_E_memory): Diito.
(OP_G): Diito.
(OP_XMM): Diito.
(DistinctDest_Fixup): Diito.
* i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4.
* i386-opc.h (SPACE_EVEXMAP4): Add legacy insn
promote to evex.
* i386-opc.tbl: Handle some legacy and vex insns don't
support gpr32. And add some legacy insn (map2 / 3) promote
to evex.
For some ELF targets .text/.data are overridden. In that case
obj_elf_{text,data}() need calling, just like .code vectors to that
function for the remaining ELF targets.
While there also hand on the function arguments, even if right now
they're meaningless. This matches what other targets' code does.
It doesn't look to be a good idea to override the custom handler that
ELF has; afaict doing so broke .previous, and a sub-section specifier
wasn't accepted either.
Much like REX, those encodings - if permitting 8-bit regs at all, i.e.
only starting with APX - permit use of "new" 8-bit registers only. %ah,
%ch, %dh, and %bh cannot be encoded and hence should be rejected.
Permit their use outside of 64-bit code though, as "new" registers
simply don't exist there.
This addresses two issues: For one, a user specified "rex" did not cause
the diagnostic to trigger when there was no other need for a REX prefix;
instead, another than the specified insn+operands was encoded. And then
(which is what this started from) .insn didn't respect {rex} (and was
otherwise similarly flawed as ordinary insns).
The latter requires splitting out code from md_assemble(), for it to
become re-usable. Besides the addition to address the first issue, that
code then also needs generalizing to account for immediate operands, as
with .insn we can't make assumptions anymore on all respective templates
having at most two operands (we still can build upon there being at most
two non-immediate operands, though). While moving the code also simplify
the first if(), by folding redundant checks.
In the new testcase also test a few more things which afaics weren't
tested till now.
If the symbol index is not zero, the addend is used to represent
the first and the third expressions of the .align.
The lowest 8 bits are used to represent the first expression.
Other bits are used to represent the third expression.
The addend of R_LARCH_ALIGN for ".align 5, ,4" is 0x405.
The addend of R_LARCH_ALIGN for ".balign 32, ,4" is 0x405.
Suffix the instruction description of conditional branch extended
mnemonics with their condition (e.g. "on A high"). This complements
the optional printing of instruction descriptions as comments in the
disassembly.
Due to the added text the maximum description length is increased from
80 to 128 characters (including the trailing '\0' character).
opcodes/
* s390-mkopc.c: Add suffix to conditional branch extended
mnemonic instruction descriptions.
gas/
* testsuite/gas/s390/zarch-insndesc.s: Add test cases for
printing of suffixed instruction description of conditional
branch extended mnemonics.
* testsuite/gas/s390/zarch-insndesc.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Print instruction description as comment in disassembly with s390
architecture specific option "insndesc":
- For objdump it can be enabled with option "-M insndesc"
- In gdb it can be enabled with "set disassembler-options insndesc"
Since comments are not column aligned the output can enhanced for
readability by postprocessing using a filter such as "expand":
... | expand -t 8,16,24,32,40,80
Or when using in combination with objdump option --visualize-jumps:
... | expand | sed -e 's/ *#/\t#/' | expand -t 1,80
Note that the instruction descriptions add about 128 KB to s390-opc.o:
s390-opc.o without instruction descriptions: 216368 bytes
s390-opc.o with instruction descriptions : 348432 bytes
binutils/
* NEWS: Mention new s390-specific disassembler option
"insndesc".
include/
* opcode/s390.h (struct s390_opcode): Add field to hold
instruction description.
opcodes/
* s390-mkopc.c: Copy instruction description from s390-opc.txt
into generated operation code table s390-opc.tab.
* s390-opc.c (s390_opformats): Provide NULL as description in
.insn pseudo-mnemonics opcode table.
* s390-dis.c: Add s390-specific disassembler option "insndesc"
and optionally print the instruction description as comment in
the disassembly when it is specified.
gas/
* testsuite/gas/s390/s390.exp: Add new test disassembly test
case "zarch-insndesc".
* testsuite/gas/s390/zarch-insndesc.s: New test case for s390-
specific disassembler option "insndesc".
* testsuite/gas/s390/zarch-insndesc.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
This patch add support for FEAT_ECBHB "Exploitative control using
branch history information" adding the "clrbhb" instruction. AFAIU
the same alias was originally added as "clearbhb" before the
architecture was finalized (Mandatory v8.9-a/v9.4-a; Optional
v8.0-a+/v9.0-a+).
This patch add supports for FEAT_SPECRES2 "Enhanced speculation
restriction instructions" adding the "cosp" instruction.
This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+. It is
enabled by the +predres2 march flag.
Since AVX10.1/256 will also allow 64 bit mask register, we will
remove the restriction for size of the mask register in AVX10.
gas/ChangeLog:
* config/tc-i386.c (VSZ128, VSZ256, VSZ512): New.
(VEX_check_encoding): Remove opcode_modifier check for vsz.
* testsuite/gas/i386/avx10-vsz.l: Remove testcases for mask
registers since they are not needed.
* testsuite/gas/i386/avx10-vsz.s: Ditto.
opcodes/ChangeLog:
* i386-gen.c: Remove Vsz.
* i386-opc.h: Ditto.
* i386-opc.tbl: Remove kvsz.
* i386-tbl.h: Regenerated.
For tail36, it is necessary to explicitly indicate the temporary register.
Therefore, the compiler and users will know that the tail will use a register.
call36 func
pcalau18i $ra, %call36(func)
jirl $ra, $ra, 0;
tail36 $t0, func
pcalau18i $t0, %call36(func)
jirl $zero, $t0, 0;
R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and
these two instructions must adjacent.
The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs.
