Commit Graph

2341 Commits

Author SHA1 Message Date
Yao Qi
43cdf5aeb8 Pass noaliases_p to aarch64_decode_insn
Nowadays aarch64_decode_insn is a public interface used by both
opcodes and gdb.  However, its behaviour relies on a global variable
no_aliases, which isn't a good practise.  On the other hand, In default,
no_aliases is zero, but in GDB, we do want no alias when decoding
instructions for prologue analysis (patches to be posted), so that we
can handle both instructions "add" and "mov" (an alias of "add") as
"add".  The code in GDB can be simplified.

This patch adds a new argument in aarch64_decode_insn, and pass no_aliases
to it.  In GDB side, always pass 1 to it.

include/opcode:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_decode_insn): Update declaration.

opcodes:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c	(aarch64_decode_insn): Add one argument
	noaliases_p.  Update comments.  Pass noaliases_p rather than
	no_aliases to aarch64_opcode_decode.
	(print_insn_aarch64_word): Pass no_aliases to
	aarch64_decode_insn.

gdb:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
	aarch64_decode_insn.
2015-10-28 14:22:57 +00:00
Vinay Kumar
c2f2875869 Fix RL78 disassembly of DE+offset addressing to always show the offset, even when zero.
PR binutils/19159
opcodes	* rl78-decode.opc (MOV): Added offset to DE register in index
	addressing mode.
	* rl78-decode.c: Regenerate.

test	* gas/rl78/pr19159.s: New test source file.
	* gas/rl78/pr19159.d: New test case.
	* gas/rl78/rl78.exp: Run the new test.
2015-10-27 15:24:40 +00:00
Vinay Kumar
4666280441 Display system registers by their names when disassembling RL78 instructions.
PR binutils/19158
opcodes	* rl78-decode.opc: Add 's' print operator to instructions that
	access system registers.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78_common): Decode all system
	registers.

tests	* gas/rl78/pr19158.s: New test source file.
	* gas/rl78/pr19158.d: New test case.
	* gas/rl78/rl78.exp: Run the new test.
2015-10-27 14:49:02 +00:00
Vinay Kumar
02f12cd466 Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, even when zero.
PR binutils/19157
opcodes	* rl78-decode.opc: Add 'a' print operator to mov instructions
	using stack pointer plus index addressing.
	* rl78-decode.c: Regenerate.

tests	* gas/rl78: New directory.
	* gas/rl78/rl78.exp: New test driver.
	* gas/rl78/pr19157.s: New test source file.
	* gas/rl78/pr19157.d: New test case.
2015-10-27 14:00:40 +00:00
Andreas Krebbel
485f23cf5c Add missing changelog entries 2015-10-14 12:19:39 +02:00
Andreas Krebbel
c46eb7b88a S/390: Fix instruction type of troo, trot, trto, and trtt.
opcodes/ChangeLog:

2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Fix comment.
	* s390-opc.txt: Change instruction type for troo, trot, trto, and
	trtt to RRF_U0RER since the second parameter does not need to be a
	register pair.

gas/testsuite/ChangeLog:

2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gas/s390/esa-g5.d: Use odd GPR for the second operand.
	* gas/s390/esa-g5.s: Likewise.
	* gas/s390/esa-z9-109.d: Likewise.
	* gas/s390/esa-z9-109.s: Likewise.
2015-10-14 10:58:41 +02:00
Nick Clifton
3f94e60d92 Fix compile time warning compiling ARC port. 2015-10-08 12:34:13 +01:00
Yao Qi
875880c661 Avoid using 'template' C++ keyword
'template' is used in include/opcode/aarch64.h as below,

 typedef struct
 {
   const char *template;
   uint32_t value;
   int has_xt;
 } aarch64_sys_ins_reg;

and it triggers compilation errors when GDB is built in C++ mode.

In file included from git/gdb/aarch64-tdep.c:62:0:
git/gdb/../include/opcode/aarch64.h:651:15: error: expected unqualified-id before 'template'
   const char *template;

This patch is to rename field template to name.

gas/

	* config/tc-aarch64.c (md_begin): Access field 'name' rather
	than 'template'.

include/opcode/

	* aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
	<name>: New field.

opcodes/

	* aarch64-dis.c (aarch64_ext_sysins_op): Access field
	'name' rather than 'template'.
	* aarch64-opc.c (aarch64_print_operand): Likewise.
2015-10-07 15:22:47 +01:00
Nick Clifton
886a250647 New ARC implementation.
bfd	* archures.c: Remove support for older ARC. Added support for new
	ARC cpus (ARC600, ARC601, ARC700, ARCV2).
	* bfd-in2.h: Likewise.
	* config.bfd: Likewise.
	* cpu-arc.c: Likewise.
	* elf32-arc.c: Totally changed file with a refactored
	inplementation of the ARC port.
	* libbfd.h: Added ARC specific relocation types.
	* reloc.c: Likewise.

gas     * config/tc-arc.c: Revamped file for ARC support.
        * config/tc-arc.h: Likewise.
        * doc/as.texinfo: Add new ARC options.
        * doc/c-arc.texi: Likewise.

ld	* configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
	* emulparams/arcebelf_prof.sh: New file
	* emulparams/arcebelf.sh: Likewise.
	* emulparams/arceblinux_prof.sh: Likewise.
	* emulparams/arceblinux.sh: Likewise.
	* emulparams/arcelf_prof.sh: Likewise.
	* emulparams/arcelf.sh: Likewise.
	* emulparams/arclinux_prof.sh: Likewise.
	* emulparams/arclinux.sh: Likewise.
	* emulparams/arcv2elfx.sh: Likewise.
	* emulparams/arcv2elf.sh: Likewise.
	* emultempl/arclinux.em: Likewise.
	* scripttempl/arclinux.sc: Likewise.
	* scripttempl/elfarc.sc: Likewise.
	* scripttempl/elfarcv2.sc: Likewise
	* Makefile.am: Add new ARC emulations.
	* Makefile.in: Regenerate.
	* NEWS: Mention the new feature.

opcodes * arc-dis.c: Revamped file for ARC support
	* arc-dis.h: Likewise.
	* arc-ext.c: Likewise.
	* arc-ext.h: Likewise.
	* arc-opc.c: Likewise.
	* arc-fxi.h: New file.
	* arc-regs.h: Likewise.
	* arc-tbl.h: Likewise.

binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
	and ARCv2.
	(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
	(guess_is_rela): Likewise.
	(dump_relocations): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_16bit_abs_reloc): Likewise.
	(is_none_reloc): Likewise.
	* NEWS: Mention the new feature.

include	* dis-asm.h (arc_get_disassembler): Correct declaration.
	* arc-reloc.def: Macro file with definition of all relocation
	types.
	* arc.h: Changed macros for the newly supported ARC cpus.  Altered
	enum defining the supported relocations.
	* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
	macro for EM_ARC_COMPACT2.
        * arc-func.h: New file.
        * arc.h: Likewise.
2015-10-07 14:20:19 +01:00
Yao Qi
36f4aab18c [aarch64] expose disas_aarch64_insn and rename it to aarch64_decode_insn
We want to use disas_aarch64_insn inside GDB to decode instructions, so
this patch exposes it and rename it to aarch64_decode_insn to follow
the conventions of other interfaces.

include/opcode:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_decode_insn): Declare it.

opcodes:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c	(disas_aarch64_insn): Remove static.  Change
	argument insn type to aarch64_insn.  Rename to ...
	(aarch64_decode_insn): ... it.
	(print_insn_aarch64_word): Caller updated.
2015-10-02 15:23:58 +01:00
Yao Qi
7232d38966 [aarch64] Remove argument pc from disas_aarch64_insn
I happen to see that argument pc is not used inside disas_aarch64_insn
at all.  This patch is to remove it.

OK to apply?

opcodes:

2015-10-02  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
	(print_insn_aarch64_word): Caller updated.
2015-10-02 15:23:54 +01:00
Dominik Vogt
7ecc513a44 Add support for extensions in the .machine pseudoop on S/390, e.g. ".machine zEC12+nohtm+vx"
gas	* doc/c-s390.texi: Add documentation.
	Add missing code markup.
	* config/tc-s390.c (current_flags): New static variable.
	(s390_parse_cpu): Parse cpu flags a la "+nohtm" etc.
	(s390_setup_opcodes): Use cpu flags to determine the set of opcodes.
	Fix indentation.
	(md_parse_option): Call s390_parse_cpu with the new signature.
	(s390_machine): Likewise.
	Keep track of current_flags.
	Simplify code a bit.
	undefine MAX_HISTORY at end of function.
	(s390_machinemode): undefine MAX_HISTORY at end of function.
	Update an error message.

tests	* gas/s390/s390.exp: Add new tests.
	* gas/s390/machine-parsing-1.s: New test file.
	* gas/s390/machine-parsing-1.l: Likewise.
	* gas/s390/machine-parsing-2.s: Likewise.
	* gas/s390/machine-parsing-2.l: Likewise.
	* gas/s390/machine-parsing-3.s: Likewise.
	* gas/s390/machine-parsing-3.l: Likewise.
	* gas/s390/machine-parsing-4.s: Likewise.
	* gas/s390/machine-parsing-4.l: Likewise.
	* gas/s390/machine-parsing-5.s: Likewise.
	* gas/s390/machine-parsing-5.l: Likewise.
	* gas/s390/machine-parsing-6.s: Likewise.
	* gas/s390/machine-parsing-6.l: Likewise.

opcode	* s390.h (S390_INSTR_FLAG_HTM): New flag.
	(S390_INSTR_FLAG_VX): New flag.
	(S390_INSTR_FLAG_FACILITY_MASK): New flag mask.

opcodes	* s390-mkopc.c (main): Parse htm and vx flag.
	* s390-opc.txt: Mark instructions from the hardware transactional
	memory and vector facilities with the "htm"/"vx" flag.
2015-09-29 13:22:07 +01:00
Nick Clifton
b08b78e7d4 Updare French translation for binutils and German translation for opcodes. 2015-09-28 16:34:00 +01:00
Tom Rix
36f7a9411d Patches for illegal ppc 500 instructions
This change marks a few opcodes as invalid for ppc e500 as well as adds
a test to verify the change.
2015-09-28 12:09:51 +09:30
jamesbowman
9a09557a93 The FT32's disassembly of 10-bit literals has the incorrect mask.
[opcodes]
	* ft32-dis.c (print_insn_ft32): Fix incorrect data field mask.
2015-09-25 12:33:30 -07:00
Nick Clifton
b6518b3871 Fix compile time warnings generated when compiling with clang.
bfd	* bout.c (b_out_slurp_reloc_table): Cast constant to unsigned in
	order to avoid problems with left shifting negative values.
	(abs32code): Likewise.
	* mach-o.c (FILE_ALIGN): Likewise.
	* coff-rs6000.c (xcoff_debug_sections): Delete unused static
	array.
	* elf32-visium.c (visium_reloc_map): Likewise.
	* elf32-arm.c (elf32_arm_final_link_relocate): Remove useless
	calls to abs function.
	* elf32-frv.c (_frvfdpic_relax_tls_entries): Likewise.
	* elf32-score.c (score_elf_final_link_relocate): Likewise.
	* elf32-score7.c (score_elf_final_link_relocate): Likewise.
	* elf32-i860.c (i860_howto_pc26_reloc): Use multiplication instead
	of shifting to create a negative mask.
	* elf32-msp430.c (elf_backend_special_sections): Define.
	* elfxx-mips.c (got_ofst_reloc_p): Delete unused function.
	(got_hi16_reloc_p): Delete unused function.
	* ppcboot.c (ppcboot_bfd_print_private_bfd_data): Fix test of
	partition name.

gas	* config/tc-ppc.c (insn_validate): Cast PPC_OPSHIFT_INV to an int.

opcode	* ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
	shifting.

ld	* emultempl/elf32.em (ehdr_start_empty): New static variable.
	(before_allocation): Use it to initialise ehdr_start_save.
	* emultempl/pe.em (write_build_id): Remove useless double
	parenthesis.
	* emultempl/pep.em (write_build_id): Likewise.

opcodes	* bfin-dis.c (fmtconst): Remove unnecessary call to the abs
	function.
	* tic30-dis.c (print_branch): Likewise.
	* cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
	value before left shifting.
	* fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
	* hppa-dis.c (print_insn_hppa): Likewise.
	* mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
	array.
	* msp430-dis.c (msp430_singleoperand): Likewise.
	(msp430_doubleoperand): Likewise.
	(print_insn_msp430): Likewise.
	* nds32-asm.c (parse_operand): Likewise.
	* sh-opc.h (MASK): Likewise.
	* v850-dis.c (get_operand_value): Likewise.
2015-09-23 18:05:16 +01:00
Nick Clifton
f04265eceb Enhance the RX disassembler to detect and report bad instructions.
opcode	* rx.h (enum RX_Size): Add RX_Bad_Size entry.

opcodes	* rx-decode.opc (bwl): Use RX_Bad_Size.
	(sbwl): Likewise.
	(ubwl): Likewise.  Rename to ubw.
	(uBWL): Rename to uBW.
	Replace all references to uBWL with uBW.
	* rx-decode.c: Regenerate.
	* rx-dis.c (size_names): Add entry for RX_Bad_Size.
	(opsize_names): Likewise.
	(print_insn_rx): Detect and report RX_Bad_Size.
2015-09-22 17:21:13 +01:00
Anton Blanchard
6dca4fd141 opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
2015-09-22 16:10:14 +10:00
Andreas Krebbel
be62444771 S/390: Fix instruction format of crj*, clrj*, and clgrj*.
This fixes the instruction format for 3 of the compare and branch
extended mnemonics.  That way the extended mnemonics are actually
being found by objdump.

gas/testsuite/ChangeLog:

2015-09-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gas/s390/zarch-z10.d: Fix testcase for some of the compare and
	branch extended mnemonics.

opcodes/ChangeLog:

2015-09-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.txt: Fix instruction format of crj*, clrj*, and clgrj*.
2015-09-10 15:26:35 +02:00
Andreas Krebbel
08f3c71119 S/390: Remove F_20 and FE_20. Adjust comments.
This is cleanup only.

opcodes/ChangeLog:

2015-09-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Remove unused (and broken) F_20 and FE_20 operand
	types and adjust numbering accordingly.  Fix some comments.
2015-09-10 15:26:23 +02:00
Andreas Krebbel
9c1c2a0bb1 S/390: Fix MASK_RIE_R0PI and MASK_RIE_R0PU.
This makes objdump to be able to recognize some of the extended
mnemonics more often.  It does not lead to wrong being generated.

opcodes/ChangeLog:

2015-09-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Fix MASK_RIE_R0PI and MASK_RIE_R0PU.

gas/testsuite/ChangeLog:

2015-09-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gas/s390/zarch-z10.d: Fix testcase for compare and branch
	extended mnemonics.
2015-09-10 15:25:55 +02:00
Andreas Krebbel
d660d56578 S/390: Remove trailing zeros on 4-bytes opcodes.
This is a NOP change only relevant when reading the file or parsing it
with other tools.

opcodes/ChangeLog:

2015-09-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Add OP32 definition.
	* s390-opc.txt: Reduce the opcode padding of some extended
	mnemonics from 6 to the actual length (which is 4).
2015-09-09 14:10:33 +02:00
Andreas Krebbel
c694bafc0b S/390: Fix opcode of ppno.
opcodes/ChangeLog:

2015-09-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.txt: Fix opcode of ppno instruction.

gas/testsuite/ChangeLog:

2015-09-09  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* gas/s390/zarch-z13.d: Fix opcode of ppno instruction.
2015-09-09 14:10:13 +02:00
Jose E. Marchesi
3807431192 Support for the sparc %pmcdper privileged register.
opcodes/ChangeLog:

2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-dis.c (print_insn_sparc): Handle the privileged register
	%pmcdper.

gas/ChangeLog:

2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (priv_reg_table): New privileged register
	%pmcdper.

gas/testsuite/ChangeLog:

2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* gas/sparc/wrpr.s: Test writing to the privileged %pmcdper
	register.
	* gas/sparc/wrpr.d: ...and the expected result.
	* gas/sparc/rdpr.s: Test reading from the privileged %pmcdper
	register.
	* gas/sparc/rdpr.d: ...and the expected result.
2015-08-25 17:16:34 +02:00
Jan Stancek
5f40e14d76 Fix the partial disassembly of a broken three byte instruction at the end of a function.
opcodes	* i386-dis.c (print_insn): Fix decoding of three byte operands.

tests	* gas/i386/intel.s: Add test of disassembly of a potential
	three byte instuction at the end of a function.
	* gas/i386/intel.d: Update expected disassembly.
2015-08-24 14:50:15 +01:00
Alexander Fomin
ab4e4ed5da PR binutils/18257: Properly decode x86/Intel mask instructions.
opcodes/

	PR binutils/18257
	* i386-dis.c: Use MOD_TABLE for most of mask instructions.
	(MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1, MOD_VEX_W_1_0F41_P_0_LEN_1,
	MOD_VEX_W_0_0F41_P_2_LEN_1, MOD_VEX_W_1_0F41_P_2_LEN_1,
	MOD_VEX_W_0_0F42_P_0_LEN_1, MOD_VEX_W_1_0F42_P_0_LEN_1,
	MOD_VEX_W_0_0F42_P_2_LEN_1, MOD_VEX_W_1_0F42_P_2_LEN_1,
	MOD_VEX_W_0_0F44_P_0_LEN_1, MOD_VEX_W_1_0F44_P_0_LEN_1,
	MOD_VEX_W_0_0F44_P_2_LEN_1, MOD_VEX_W_1_0F44_P_2_LEN_1,
	MOD_VEX_W_0_0F45_P_0_LEN_1, MOD_VEX_W_1_0F45_P_0_LEN_1,
	MOD_VEX_W_0_0F45_P_2_LEN_1, MOD_VEX_W_1_0F45_P_2_LEN_1,
	MOD_VEX_W_0_0F46_P_0_LEN_1, MOD_VEX_W_1_0F46_P_0_LEN_1,
	MOD_VEX_W_0_0F46_P_2_LEN_1, MOD_VEX_W_1_0F46_P_2_LEN_1,
	MOD_VEX_W_0_0F47_P_0_LEN_1, MOD_VEX_W_1_0F47_P_0_LEN_1,
	MOD_VEX_W_0_0F47_P_2_LEN_1, MOD_VEX_W_1_0F47_P_2_LEN_1,
	MOD_VEX_W_0_0F4A_P_0_LEN_1, MOD_VEX_W_1_0F4A_P_0_LEN_1,
	MOD_VEX_W_0_0F4A_P_2_LEN_1, MOD_VEX_W_1_0F4A_P_2_LEN_1,
	MOD_VEX_W_0_0F4B_P_0_LEN_1, MOD_VEX_W_1_0F4B_P_0_LEN_1,
	MOD_VEX_W_0_0F4B_P_2_LEN_1, MOD_VEX_W_0_0F91_P_0_LEN_0,
	MOD_VEX_W_1_0F91_P_0_LEN_0, MOD_VEX_W_0_0F91_P_2_LEN_0,
	MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0,
	MOD_VEX_W_0_0F92_P_2_LEN_0, MOD_VEX_W_0_0F92_P_3_LEN_0,
	MOD_VEX_W_1_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
	MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_W_0_0F93_P_3_LEN_0,
	MOD_VEX_W_1_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0,
	MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0,
	MOD_VEX_W_1_0F98_P_2_LEN_0, MOD_VEX_W_0_0F99_P_0_LEN_0,
	MOD_VEX_W_1_0F99_P_0_LEN_0, MOD_VEX_W_0_0F99_P_2_LEN_0,
	MOD_VEX_W_1_0F99_P_2_LEN_0, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
	MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
	MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
	MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
	MOD_VEX_W_1_0F3A33_P_2_LEN_0.
	(vex_w_table): Replace terminals with MOD_TABLE entries for
	most of mask instructions.

gas/testsuite

	PR binutils/18257
	* gas/i386/disassem.s: Add mask instructions with invalid ModR/M byte.
	* gas/i386/x86-64-disassem.s: Likewise.
	* gas/i386/disassem.d: Updated.
	* gas/i386/x86-64-disassem.d: Likewise.
2015-08-21 14:48:05 +03:00
Alan Modra
919b75f7e2 Trailing space in opcodes/ generated files
HJ recently removed trailing space in binutils files, but unfortunately
they return when regenerating files in opcodes.  This fixes the regen
process.

	* cgen.sh: Trim trailing space from cgen output.
	* ia64-gen.c (print_dependency_table): Don't generate trailing space.
	(print_dis_table): Likewise.
	* opc2c.c (dump_lines): Likewise.
	(orig_filename): Warning fix.
	* ia64-asmtab.c: Regenerate.
2015-08-17 12:07:12 +09:30
Andre Vieira
4ab90a7a90 Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.
opcodes * arm-dis.c (print_insn_arm): Disassembling for all targets V6
	and higher with ARM instruction set will now mark the 26-bit
	versions of teq,tst,cmn and cmp as UNPREDICTABLE.
	(arm_opcodes): Fix for unpredictable nop being recognized as a teq.

test    * gas/arm/nops.d: New.
	* gas/arm/nops.s: New.
	* gas/arm/inst.d: Changed expectation file for 26-bit  teq,
	tst, cmn and cmp.
2015-08-13 11:39:08 +01:00
Simon Dardis
40fc1451c6 [MIPS] Map 'move' to 'or'.
The MIPS assembly idiom 'move' now maps to the 'or' machine instruction. This
change affects microMIPS, MIPS32, MIPS64.

2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>

opcodes/

	* micromips-opc.c (micromips_opcodes): Re-order table so that move
	based on 'or' is first.
	* mips-opc.c (mips_builtin_opcodes): Ditto.

bfd/

	* elfxx-mips.c (STUB_MOVE): Change to use 'or' only.
	(mips_o32_exec_plt0_entry, mips_n32_exec_plt0_entry,
	mips_n64_exec_plt0_entry, micromips_insn32_o32_exec_plt0_entry):
	Update to use 'or' instead of 'addu/daddu'.
	(_bfd_mips_elf_finish_dynamic_symbol): Update usage of STUB_MOVE.
	(move_insns_32): Reorder table.

gas/

	* config/tc-mips.c (move_register): Change to use 'or' only.
	(s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Update to
	use or for move.

gas/testsuite/

	* gas/mips/elf-rel23.d: Update test.
	* gas/mips/elf-rel23.d: Ditto.
	* gas/mips/elf-rel23a.d: Ditto.
	* gas/mips/elf-rel23b.d: Ditto.
	* gas/mips/elf_e_flags1.d: Ditto.
	* gas/mips/elf_e_flags2.d: Ditto.
	* gas/mips/elf_e_flags3.d: Ditto.
	* gas/mips/elf_e_flags4.d: Ditto.
	* gas/mips/loc-swap-dis.d: Ditto.
	* gas/mips/micromips-insn32.d: Ditto.
	* gas/mips/micromips-noinsn32.d: Ditto.
	* gas/mips/micromips-trap.d: Ditto.
	* gas/mips/micromips.d: Ditto.
	* gas/mips/mips-abi32-pic.d: Ditto.
	* gas/mips/mips-abi32.d: Ditto.
	* gas/mips/mips-gp32-fp32-pic.d: Ditto.
	* gas/mips/mips-gp32-fp32.d: Ditto.
	* gas/mips/mips-gp32-fp64-pic.d: Ditto.
	* gas/mips/mips-gp32-fp64.d: Ditto.
	* gas/mips/mips-gp64-fp32-pic.d: Ditto.
	* gas/mips/mips-gp64-fp32.d: Ditto.
	* gas/mips/mips-gp64-fp64-pic.d: Ditto.
	* gas/mips/mips-gp64-fp64.d: Ditto.
	* gas/mips/mipsr6@loc-swap-dis.d: Ditto.
	* gas/mips/tls-o32.d: Ditto.
	* gas/mips/uld2-eb.d: Ditto.
	* gas/mips/uld2-el.d: Ditto.
	* gas/mips/ulw2-eb-ilocks.d: Ditto.
	* gas/mips/ulw2-eb.d: Ditto.
	* gas/mips/ulw2-el-ilocks.d: Ditto.
	* gas/mips/ulw2-el.d: Ditto.
	* gas/mips/move.d: New test.
	* gas/mips/move.s: Ditto.
	* gas/mips/micromips32-move.d: Ditto.
	* gas/mips/micromips32-move.s: Ditto.
	* gas/mips/mips.exp: Run the new tests.

gold/

	* mips.cc (plt0_entry_o32, plt0_entry_n32, plt0_entry_n64,
	lazy_stub_normal_1, lazy_stub_normal_1_n64,
	lazy_stub_normal_2, lazy_stub_normal_2_n64, lazy_stub_big,
	lazy_stub_big_n64, lazy_stub_micromips32_normal_1_n64,
	lazy_stub_micromips32_normal_2_n64, lazy_stub_micromips32_big,
	lazy_stub_micromips32_big_n64): Update to use 'or' for move instead
	of 'addu/daddu'.

ld/testsuite/

	* ld-mips-elf/compressed-plt-1-n32-mips16.od: Update test.
	* ld-mips-elf/compressed-plt-1-n32-umips.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16-got.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16-only.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16-word.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-mips16.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-se.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-umips-got.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-umips-word.od: Ditto.
	* ld-mips-elf/compressed-plt-1-o32-umips.od: Ditto.
	* ld-mips-elf/jalx-2.dd: Ditto.
	* ld-mips-elf/mips16-pic-3.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-3a.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-3b.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-5b.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-6-n32.dd: Ditto.
	* ld-mips-elf/pic-and-nonpic-6-o32.dd: Ditto.
	* ld-mips-elf/stub-dynsym-1-10000.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-2fe80.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-7fff.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-8000.d: Ditto.
	* ld-mips-elf/stub-dynsym-1-fff0.d: Ditto.
	* ld-mips-elf/tlsbin-o32.d: Ditto.
	* ld-mips-elf/tlsdyn-o32-1.d: Ditto.
	* ld-mips-elf/tlsdyn-o32-2.d: Ditto.
	* ld-mips-elf/tlsdyn-o32-3.d: Ditto.
	* ld-mips-elf/tlsdyn-o32.d: Ditto.
	* ld-mips-elf/tlslib-o32.d: Ditto.
2015-08-12 17:10:22 +01:00
H.J. Lu
43e65147c0 Remove trailing spaces in opcodes 2015-08-12 04:45:07 -07:00
Nick Clifton
922c5db5e7 Fix the disassembly of the AArch64 SIMD EXT instruction.
PR 18800
	* aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
	instruction.
2015-08-11 18:00:36 +01:00
Robert Suchanek
75fb7498c2 Add SIGRIE instruction for MIPS R6
opcodes/

	* mips-opc.c (mips_builtin_opcodes): Add "sigrie".

gas/testsuite/

	* gas/mips/r6.s: Add tests for "sigrie".
	* gas/mips/r6.d: Check for "sigrie".
	* gas/mips/r6-n32.d: Likewise.
	* gas/mips/r6-n64.d: Likewise.
2015-08-10 09:14:07 +01:00
Amit Pawar
36aed29d37 Remove CpuFMA4 support from CPU_ZNVER1_FLAGS.
opcodes/

	* i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
	* i386-init.h: Regenerated.
2015-08-07 07:31:51 -07:00
H.J. Lu
a8484f9612 Properly disassemble movnti in Intel mode
gas/testsuite/

	PR binutils/13571
	* gas/i386/i386.exp: Run i386-intel and x86_64-intel.
	* gas/i386/i386-intel.d: New file.
	* gas/i386/x86_64-intel.d: Likewise.

opcodes/

	PR binutils/13571
	* i386-dis.c (MOD_0FC3): New.
	(PREFIX_0FC3): Renamed to ...
	(PREFIX_MOD_0_0FC3): This.
	(dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
	(prefix_table): Replace Ma with Ev on movntiS.
	(mod_table): Add MOD_0FC3.
2015-07-30 04:17:02 -07:00
H.J. Lu
37a42ee9ad Regenerate configure files
bfd/

	* configure: Regenerated.

binutils/

	* configure: Regenerated.

gas/

	* configure: Regenerated.

gold/

	* configure: Regenerated.

gprof/

	* configure: Regenerated.

ld/

	* configure: Regenerated.

opcodes/

	* configure: Regenerated.
2015-07-27 07:56:32 -07:00
Alan Modra
070fe95d07 Fix ubsan signed integer overflow
IMO a fairly useless warning in this case, but technically correct.

	PR 18708
	* i386-dis.c (get64): Avoid signed integer overflow.
2015-07-23 12:52:46 +09:30
H.J. Lu
20c2a61587 Fix memory operand size for vcvtt?ps2u?qq instructions
When disassembling AVX512 vcvtt?ps2u?q instructions with data
broadcasting enabled, memory operand size should be DWORD.

gas/testsuite/

	PR binutils/18631
	* gas/i386avx512dq-intel.d: Replace "QWORD" with "DWORD" in
	vcvtt?ps2u?qq instructions disassembly regexes.
	Add disassembly regex for new test.
	* gas/i386/avx512dq.d: Likewise.
	* gas/i386/avx512dq_vl-intel.d: Likewise.
	* gas/i386/avx512dq_vl.d: Likewise.
	* gas/i386/x86-64-avx512dq-intel.d: Likewise.
	* gas/i386/x86-64-avx512dq.d: Likewise.
	* gas/i386/x86-64-avx512dq_vl-intel.d: Likewise.
	* gas/i386/x86-64-avx512dq_vl.d: Likewise.
	* gas/i386/avx512dq.s: Add new test for Intel syntax with memory
	operand and broadcasting enabled.
	* gas/i386/avx512dq_vl.s: Likewise.
	* gas/i386/x86-64-avx512dq.s: Likewise.
	* gas/i386/x86-64-avx512dq_vl.s: Likewise.

opcodes/

	PR binutils/18631
	* i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
	"EXEvexHalfBcstXmmq" for the second operand.
	(EVEX_W_0F79_P_2): Likewise.
	(EVEX_W_0F7A_P_2): Likewise.
	(EVEX_W_0F7B_P_2): Likewise.
2015-07-22 13:26:21 -07:00
Alessandro Marzocchi
6f1c214259 Updates the ARM disassembler's output of floating point constants to include the actual floating point value.
opcodes	* arm-dis.c (print_insn_coprocessor): Added support for quarter
	float bitfield format.
	(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
	quarter float bitfield format.

tests	* gas/arm/vfpv3-const-conv.d: Update expected result due to change
	of comment for vmov reg,immediate with VFP coprocessor.
2015-07-16 16:43:16 +01:00
H.J. Lu
8a643cc36c Sync config/warnings.m4 with GCC
config/

	Sync with GCC
	2015-05-27  Jason Merrill  <jason@redhat.com>

	PR bootstrap/66304
	* warnings.m4 (ACX_PROG_CXX_WARNING_OPTS)
	(ACX_PROG_CXX_WARNINGS_ARE_ERRORS)
	(ACX_PROG_CXX_WARNING_ALMOST_PEDANTIC): New.
	(ACX_PROG_CC_WARNING_OPTS, ACX_PROG_CC_WARNING_ALMOST_PEDANTIC)
	(ACX_PROG_CC_WARNINGS_ARE_ERRORS): Push into C language context.

libdecnumber/

	* configure: Regenerated.

libiberty/

	* configure: Regenerated.

opcodes/

	* configure: Regenerated.
2015-07-14 08:39:12 -07:00
Alan Modra
40f77f827b Add missing changelog entries 2015-07-10 20:08:55 +09:30
Alan Modra
ef5a96d564 Remove ppc860, ppc750cl, ppc7450 insns from common ppc.
Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations.  I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8.  This
patch fixes that problem.

Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code.  ie. you might need to modify
makefiles to pass -m860 to gas.

include/opcode/
	* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
	* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
	* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
	PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
gas/
	* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
	* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
	* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.
2015-07-03 10:57:14 +09:30
Sandra Loosemore
c8c8175b62 Opcodes and assembler support for Nios II R2
2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
	    Cesar Philippidis  <cesar@codesourcery.com>

	gas/
	* config/tc-nios2.c (nios2_min_align): New.
	(nop): Replace with....
	(nop_r1, nop_r2, nop_r2_cdx, nop32, nop16): New.
	(nios2_align): Handle alignment on 2-byte boundaries when CDX
	instructions may be present.
	(s_nios2_align): Adjust reference to nop.
	(CDXBRANCH, IS_CDXBRANCH): New.
	(CDX_UBRANCH_SUBTYPE, CDX_CBRANCH_SUBTYPE): New.
	(nios2_relax_subtype_size): Handle 2-byte CDX branches.
	(nios2_relax_frag): Likewise.
	(md_convert_frag): Handle R2 encodings.
	(nios2_check_overflow): Check that low-order bits are zero
	before applying rightshift from howto.
	(nios2_check_overflow): Correct negative overflow calculation.
	(nios2_diagnose_overflow): Handle signed_immed12_overflow.  Issue
	generic overflow messages for miscellaneous instruction formats.
	(md_apply_fix): Recognize new R2 relocations.  For pc_relative
	relocations, store fixup in *valP.
	(nios2_reglist_mask, nios2_reglist_dir): New.
	(nios2_parse_reglist): New.
	(nios2_parse_base_register): New.
	(nios2_assemble_expression): Handle constant expressions designated
	by BFD_RELOC_NONE.
	(nios2_assemble_reg3): New.
	(nios2_assemble_arg_c): Handle R2 instruction formats.
	(nios2_assemble_arg_d): Likewise.
	(nios2_assemble_arg_s): Likewise.
	(nios2_assemble_arg_t): Likewise.
	(nios2_assemble_arg_D): New.
	(nios2_assemble_arg_S): New.
	(nios2_assemble_arg_T): New.
	(nios2_assemble_arg_i): Handle R2 instruction formats.
	(nios2_assemble_arg_I): New.
	(nios2_assemble_arg_u): Handle R2 instruction formats.
	(nios2_assemble_arg_U): New.
	(nios2_assemble_arg_V): New.
	(nios2_assemble_arg_W): New.
	(nios2_assemble_arg_X): New.
	(nios2_assemble_arg_Y): New.
	(nios2_assemble_arg_o): Handle R2 instruction formats.
	(nios2_assemble_arg_O): New.
	(nios2_assemble_arg_P): New.
	(nios2_assemble_arg_j): Handle R2 instruction formats.
	(nios2_assemble_arg_k): New.
	(nios2_assemble_arg_l): Handle R2 instruction formats.
	(nios2_assemble_arg_m): Likewise.
	(nios2_assemble_arg_M): New.
	(nios2_assemble_arg_N): New.
	(nios2_assemble_arg_e): New.
	(nios2_assemble_arg_f): New.
	(nios2_assemble_arg_g): New.
	(nios2_assemble_arg_h): New.
	(nios2_assemble_arg_R): New.
	(nios2_assemble_arg_B): New.
	(nios2_assemble_args): Handle new argument letters.
	(nios2_consume_arg): Likewise.
	(nios2_translate_pseudo_insn): Avoid dereferencing null pointer
	in error message.
	(nios2_ps_insn_info_structs): Add nop.n.
	(output_ubranch): Handle CDX branches.
	(output_cbranch): Likewise.
	(output_call): Handle R2 encodings.
	(output_movia): Likewise.
	(md_begin): Initialize nios2_min_align.
	(md_assemble): Align to nios2_min_align.  Adjust nios2_min_align
	if a 16-bit instruction is seen.
	(nios2_cons_align): Use appropriate nop pattern.

	include/opcode/
	* nios2.h (enum iw_format_type): Add R2 formats.
	(enum overflow_type): Add signed_immed12_overflow and
	enumeration_overflow for R2.
	(struct nios2_opcode): Document new argument letters for R2.
	(REG_3BIT, REG_LDWM, REG_POP): Define.
	(includes): Include nios2r2.h.
	(nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
	(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
	(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
	(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
	(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
	(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
	Declare.
	* nios2r2.h: New file.

	opcodes/
	* nios2-dis.c (nios2_extract_opcode): New.
	(nios2_disassembler_state): New.
	(nios2_find_opcode_hash): Use mach parameter to select correct
	disassembler state.
	(nios2_print_insn_arg): Extend to support new R2 argument letters
	and formats.
	(print_insn_nios2): Check for 16-bit instruction at end of memory.
	* nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
	(NIOS2_NUM_OPCODES): Rename to...
	(NIOS2_NUM_R1_OPCODES): This.
	(nios2_r2_opcodes): New.
	(NIOS2_NUM_R2_OPCODES): New.
	(nios2_num_r2_opcodes): New.
	(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
	(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
	(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
	(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
	(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):	New.
2015-07-01 16:08:03 -07:00
Amit Pawar
9916071f8d Add support for monitorx/mwaitx instructions
gas/

	* config/tc-i386.c (cpu_arch): Add .mwaitx.
	(process_immext): Check operands for monitorx/mwaitx instructions.
	* doc/c-i386.texi: Document mwaitx.

gas/testsuite/

	* gas/i386/i386.exp: Add new mwaitx test cases.
	* gas/i386/mwaitx.s: New.
	* gas/i386/mwaitx-bdver4.d: New.
	* gas/i386/x86-64-mwaitx.s: New.
	* gas/i386/x86-64-mwaitx-bdver4.d: New.
	* gas/i386/mwaitx-reg.s: New.
	* gas/i386/mwaitx-reg.l: New.
	* gas/i386/x86-64-mwaitx-reg.l: New.
	* gas/i386/x86-64-mwaitx-reg.s: New.
	* gas/i386/arch-13.s: Updated.
	* gas/i386/arch-13.d: Updated.
	* gas/i386/arch-13-znver1.d: Updated.
	* gas/i386/x86-64-arch-3.s: Updated.
	* gas/i386/x86-64-arch-3.d: Updated.
	* gas/i386/x86-64-arch-3-znver1.d: Updated.

opcodes/

	* i386-dis.c (OP_Mwaitx): New.
	(rm_table): Add monitorx/mwaitx.
	* i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
	and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
	(operand_type_init): Add CpuMWAITX.
	* i386-opc.h (CpuMWAITX): New.
	(i386_cpu_flags): Add cpumwaitx.
	* i386-opc.tbl: Add monitorx and mwaitx.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2015-06-30 07:50:12 -07:00
Peter Bergner
7b9341139a PPC sync instruction accepts invalid and incompatible operands
ISA 2.07 added a new category called Elemental Memory Barriers that modifies
the sync instruction to accept an additional operand ESYNC.  Edmar added
support for this insruction varient here:

    https://sourceware.org/ml/binutils/2012-02/msg00221.html

Looking at this closer, I see that the insert_ls() function is misnamed
(since it's attached to the ESYNC operand, not the LS operand) but more
importantly, it is silently modifying the LS operand value behind the
users back when the LS operand is either invalid or is incompatible with
the new ESYNC operand.  The ISA 2.07 doc has an Assembler Note that clearly
states that assemblers that support the ESYNC operand should report all
invalid uses of LS and ESYNC.  This patch changes the assembler to
error out on invalid and incompatible operand usage.

opcodes/
	* ppc-opc.c (insert_ls): Test for invalid LS operands.
	(insert_esync): New function.
	(LS, WC): Use insert_ls.
	(ESYNC): Use insert_esync.

gas/testsuite/
	* gas/ppc/e6500.s <sync>: Fix invalid test.
	* gas/ppc/e6500.d: Likewise.
2015-06-22 14:55:24 -05:00
Nick Clifton
bdc4de1b24 Stop "objdump -d" from disassembling past a symbolic address.
include	* dis-asm.h (struct disassemble_info): Add stop_vma field.

binuti  * objdump.c (disassemble_bytes): Set the stop_vma field in the
	disassemble_info structure when disassembling code sections with
	-d.
	* doc/binutils.texi (objdump): Document the discrepancy between -d
	and -D.

opcodes	* dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
	requested region lies beyond it.
	* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
	looking for 32-bit insns.
	* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
	data.
	* sh-dis.c (print_insn_sh): Likewise.
	* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
	blocks of instructions.
	* vax-dis.c (print_insn_vax): Check that the requested address
	does not clash with the stop_vma.

tests	* gas/arm/backslash-at.s: Add extra .byte directives so that the
	foo symbol does not appear to point half way through an
	instruction.
	* gas/arm/backslash-at.d: Update expected disassembly.
	* gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise.
	* gas/i386/ilp32/x86-64-opcode-inval.d: Likewise.
	* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
	* gas/i386/x86-64-opcode-inval.d: Likewise.
2015-06-22 16:53:27 +01:00
Peter Bergner
11a0cf2ec0 Allow for optional operands with non-zero default values.
ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1.  It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case.  I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.

This fixes the rfebb issue.  I also fixed the mftb and mfcr instructions
so they use the same mechanism.  This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].

include/opcode/

	* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
	(ppc_optional_operand_value): New inline function.

opcodes/
	* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
	* ppc-opc.c (FXM4): Add non-zero optional value.
	(TBR): Likewise.
	(SXL): Likewise.
	(insert_fxm): Handle new default operand value.
	(extract_fxm): Likewise.
	(insert_tbr): Likewise.
	(extract_tbr): Likewise.

gas/
	* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
	Allow for optional operands without insert functions.

gas/testsuite/
	* gas/ppc/power8.d: Fixup rfebb test results.
	* gas/ppc/a2.s: Fix invalid mfcr test.
	* gas/ppc/a2.d: Likewise.
2015-06-19 17:17:07 -05:00
Matthew Wahab
bdfa8b951b [AArch64] Support id_mmfr4 system register
2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
opcodes/
  * aarch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".

gas/testsuite
  * sysreg.d: Add id_mmfr4_el1, update expected output.
  * sysreg.s: Add id_mmfr4_el1.
2015-06-16 14:17:34 +01:00
Szabolcs Nagy
24b4cf66a6 Fixes a compile time warnng about left shifting a negative value.
* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
2015-06-16 13:35:33 +01:00
Peter Bergner
99a2c56121 Remove unused MTMSRD_L macro and re-add accidentally deleted comment.
In the commit that added PowerPC Pair Singles, Ben accidentally removed
a comment and re-added an unused MTMSRD_L macro Alan had recently deleted.
This was probably just an oversite when he was refreshing his patch to
trunk.

opcodes/
	* ppc-opc.c: Add comment accidentally removed by old commit.
	(MTMSRD_L): Delete.
2015-06-12 15:06:07 -05:00
Peter Bergner
dc302c0061 Add hwsync extended mnemonic.
This commit adds a new extended menmonic for "sync 0" (same as "sync").
The ISA documentation doesn't explicitly mention hwsync as an extended
mnemonic (yet), but it does mention "heavyweight sync" and "hwsync" as
the operation that gets performed when the sync's L field is 0.
This is only enabled for POWER4 and later.

opcodes/
	* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.

gas/testsuite/
	* gas/ppc/a2.d: Fixup test case due to new extended mnemonic.
	* gas/ppc/power4.s <hwsync, lwsync, ptesync, sync>: Add tests.
	* gas/ppc/power4.d: Likewise.
2015-06-04 20:27:03 -05:00