(cgen.o): Ditto.
(EXTRA_as_new_SOURCES): Comment out.
(.tcdep): <arch>-opc.h renamed to <arch>-desc.h.
* Makefile.in: Rebuild.
* doc/Makefile.in: Rebuild.
* configure.in: Require autoconf 2.13. Redo using_cgen handling.
Delete call to AM_CYGWIN32. Replace AM_EXEEXT with AC_EXEEXT.
(AC_OUTPUT): <arch>-opc.h renamed to <arch>-desc.h.
* configure: Rebuild.
* aclocal.m4: Rebuild.
* config.in: Rebuild.
* cgen.c: Include cgen-desc.h, not cgen-opc.h.
(*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC.
(gas_cgen_cpu_desc): Renamed from gas_cgen_opcode_desc.
CGEN_INSN_ATTR renamed to CGEN_INSN_ATTR_VALUE.
CGEN_OPERAND_ATTR renamed to CGEN_OPERAND_ATTR_VALUE.
(gas_cgen_record_fixup): Remove unnecessary != 0 test.
(gas_cgen_record_fixup_exp): Ditto.
(gas_cgen_finish_insn): Ditto. Refer to operand table via cpu
descriptor, not global variable.
(gas_cgen_md_apply_fix3): Refer to operand_table via cpu
descriptor, not global variable. Refer to insert_operand handler
via cpu descriptor, not global function.
* cgen.h (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC.
* config/tc-fr30.c: Include opcodes/fr30-desc.h.
(*): gas_cgen_opcode_desc renamed to gas_cgen_cpu_desc.
CGEN_INSN_ATTR renamed to CGEN_INSN_ATTR_VALUE.
Update call to CGEN_OPERAND_TYPE,CGEN_INSN_OPERANDS.
* config/tc-m32r.c: Ditto.
(assemble_two_insns): Update calls to cgen_lookup_get_insn_operands.
(md_assemble): Ditto.
(md_convert_frag): Update call to CGEN_OPERAND_ENTRY.
(cgen.o): Ditto.
(EXTRA_as_new_SOURCES): Comment out.
(.tcdep): <arch>-opc.h renamed to <arch>-desc.h.
* Makefile.in: Rebuild.
* configure.in: Require autoconf 2.13. Redo using_cgen handling.
Delete call to AM_CYGWIN32. Replace AM_EXEEXT with AC_EXEEXT.
(AC_OUTPUT): <arch>-opc.h renamed to <arch>-desc.h.
* configure: Rebuild.
* aclocal.m4: Rebuild.
* config.in: Rebuild.
* cgen.c: Include cgen-desc.h, not cgen-opc.h.
(*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC.
(gas_cgen_cpu_desc): Renamed from gas_cgen_opcode_desc.
CGEN_INSN_ATTR renamed to CGEN_INSN_ATTR_VALUE.
CGEN_OPERAND_ATTR renamed to CGEN_OPERAND_ATTR_VALUE.
(gas_cgen_record_fixup): Remove unnecessary != 0 test.
(gas_cgen_record_fixup_exp): Ditto.
(gas_cgen_finish_insn): Ditto. Refer to operand table via cpu
descriptor, not global variable.
(gas_cgen_md_apply_fix3): Refer to operand_table via cpu
descriptor, not global variable. Refer to insert_operand handler
via cpu descriptor, not global function.
* cgen.h (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC.
* config/tc-fr30.c: Include opcodes/fr30-desc.h.
(*): gas_cgen_opcode_desc renamed to gas_cgen_cpu_desc.
CGEN_INSN_ATTR renamed to CGEN_INSN_ATTR_VALUE.
Update call to CGEN_OPERAND_TYPE,CGEN_INSN_OPERANDS.
* config/tc-m32r.c: Ditto.
(assemble_two_insns): Update calls to cgen_lookup_get_insn_operands.
(md_assemble): Ditto.
(md_convert_frag): Update call to CGEN_OPERAND_ENTRY.
(INTEL_DWORD_MNEM_SUFFIX): Define.
(BYTE_PTR): Define.
(WORD_PTR): Define.
(DWORD_PTR): Define.
(XWORD_PTR): Define.
(SHORT): Define.
(OFFSET_FLAT): Define.
(FLAT): Define.
(NONE_FOUND): Define.
(No_dSuf): Define.
(No_xSuf): Define.
* config/tc-i386.c (set_intel_syntax): New routine.
(intel_syntax): Declare.
(allow_naked_reg): Declare.
(md_pseudo_table): Support .intel_syntax and .att_syntax.
(intel_float_operand): New routine.
(md_assemble): Handle INTEL_DWORD_MNEM_SUFFIX.
Handle brackets as well as parens. Call i386_intel_operand for
intel syntax. Reverse operands if appropriate. Handle new
suffixes. Handle movzx and movsx.
(i386_is_reg): New routine.
(i386_immediate): New routine.
(i386_scale): New routine.
(i386_displacement): New routine.
(i386_operand_modifier): New routine.
(build_displacement_string): New routine.
(i386_parse_seg): New routine.
(i386_intel_memory_operand): New routine.
(i386_intel_operand): New routine.
(i386_operand): Call i386_displacement, i386_immediate,
i386_scale, etc. instead of handling inline.
(parse_register): Handle registers without prefix.
* gas/dvp/gifimage-1.[sd]: Add testcases for EOP.
* gas/dvp/upper-[12].[sd]: Test two-operand CLIP; remove
old one-operand CLIP.
Bring over from sky-980617-branch.