This came up because I was looking at ld/tmpdir/addpcis.o and noticed
the odd addends on REL16DX_HA. They ought to both be -4. The error
crept in due REL16DX_HA howto being pc-relative (as indeed it should
be), and code at gas/write.c:1001 after this comment
/* Make it pc-relative. If the back-end code has not
selected a pc-relative reloc, cancel the adjustment
we do later on all pc-relative relocs. */
*not* cancelling the pc-relative adjustment. So I've made a dummy
non-relative split reloc so that the generic code handles this, rather
than attempting to add hacks later in md_apply_fix which would not be
very robust. Having the new internal reloc also makes it easy to
support
addpcis rx,sym@ha
as an equivalent to
addpcis rx,(sym-0f)@ha
0:
The patch also fixes overflow checking, which must test whether the
addi will overflow too since @l relocs don't have any overflow check.
Lastly, since I was poking at md_apply_fix, I arranged to have the
generic gas/write.c code emit errors for subtraction expressions where
we lack reloc support.
include/
* elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment.
* elf/ppc.h (R_PPC_16DX_HA): Likewise.
bfd/
* reloc.c (BFD_RELOC_PPC_16DX_HA): New.
* elf64-ppc.c (ppc64_elf_howto_raw <R_PPC64_16DX_HA>): New howto.
(ppc64_elf_reloc_type_lookup): Translate new bfd reloc.
(ppc64_elf_ha_reloc): Correct overflow test on REL16DX_HA.
(ppc64_elf_relocate_section): Likewise.
* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_16DX_HA>): New howto.
(ppc_elf_reloc_type_lookup): Translate new bfd reloc.
(ppc_elf_check_relocs): Handle R_PPC_16DX_HA to pacify gcc.
* libbfd.h: Regenerate.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (md_assemble): Use BFD_RELOC_PPC_16DX_HA for addpcis.
(md_apply_fix): Remove fx_subsy check. Move code converting to
pcrel reloc earlier and handle BFD_RELOC_PPC_16DX_HA. Remove code
emiiting errors on seeing fx_pcrel set on unexpected relocs, as
that is done now by the generic code via..
* config/tc-ppc.h (TC_FORCE_RELOCATION_SUB_LOCAL): ..this. Define.
(TC_VALIDATE_FIX_SUB): Define.
ld/
* testsuite/ld-powerpc/addpcis.d: Define ext1 and ext2 at
limits of addpcis range.
PR 20744
bfd/
* elf32-ppc.c (ppc_elf_howto_raw): Correct dst_mask on all VLE
16D relocations.
(ppc_elf_vle_split16): Correct field mask and shift for 16D relocs.
(ppc_elf_relocate_section): Correct calculation for VLE SDAREL
relocs.
ld/
* testsuite/ld-powerpc/vle-reloc-2.s: Use r6 for last insn of
each group.
* testsuite/ld-powerpc/vle-reloc-2.d: Update for above change
and sdarel reloc fix.
Remove an inconsistency in linker error message processing causing that
it depends on the ability to infer the name of the originating source
file whether or not the name of the offending function is repeated by
clever formatters for each issue reported within the function.
Taking the `ld/testsuite/ld-powerpc/tocopt7.s' test case source as an
example and the `powerpc-linux' target we have:
$ as -gdwarf2 -o tocopt.o -a64 tocopt.s
$ ld -o tocopt -melf64ppc tocopt.o
tocopt.o: In function `_start':
tocopt.s:35:(.text+0x14): toc optimization is not supported for 0x3fa00000 instruction.
tocopt.s:49:(.text+0x34): toc optimization is not supported for 0x3fa00000 instruction.
$
vs:
$ as -o tocopt.o -a64 tocopt.s
$ ld -o tocopt -melf64ppc tocopt.o
tocopt.o: In function `_start':
(.text+0x14): toc optimization is not supported for 0x3fa00000 instruction.
tocopt.o: In function `_start':
(.text+0x34): toc optimization is not supported for 0x3fa00000 instruction.
$
Similarly with the `mips-linux' target and this source:
$ cat jal-global-multi-overflow.s
.text
.set noreorder
.space 0x2000
.align 4
.globl foo
.ent foo
foo:
jal bar
nor $0, $0
jal bar
nor $0, $0
.end foo
.space 0x1ff0
.align 4
.globl bar
.ent bar
bar:
jal foo
nor $0, $0
jal foo
nor $0, $0
.end bar
$ as -o jal-global-multi-overflow.o jal-global-multi-overflow.s
$ ld -Ttext 0x1fffd000 -e foo -o jal-global-multi-overflow jal-global-multi-overflow.o
jal-global-multi-overflow.o: In function `foo':
(.text+0x2000): relocation truncated to fit: R_MIPS_26 against `bar'
jal-global-multi-overflow.o: In function `foo':
(.text+0x2008): relocation truncated to fit: R_MIPS_26 against `bar'
jal-global-multi-overflow.o: In function `bar':
(.text+0x4000): relocation truncated to fit: R_MIPS_26 against `foo'
jal-global-multi-overflow.o: In function `bar':
(.text+0x4008): relocation truncated to fit: R_MIPS_26 against `foo'
$
Not only this is inconsistent, but it causes output clutter as well with
redundant information.
The cause for this is a check in `vfinfo' the intent of which is to
print the function heading whenever (among others) the name of the
source file has changed, which however does not take into account a
situation where the name couldn't have been established both now and
previously.
Adjust the check then for this situation, yielding:
$ as -o tocopt.o -a64 tocopt.s
$ ld -o tocopt -melf64ppc tocopt.o
tocopt.o: In function `_start':
(.text+0x14): toc optimization is not supported for 0x3fa00000 instruction.
(.text+0x34): toc optimization is not supported for 0x3fa00000 instruction.
$
and:
$ as -o jal-global-multi-overflow.o jal-global-multi-overflow.s
$ ld -Ttext 0x1fffd000 -e foo -o jal-global-multi-overflow jal-global-multi-overflow.o
jal-global-multi-overflow.o: In function `foo':
(.text+0x2000): relocation truncated to fit: R_MIPS_26 against `bar'
(.text+0x2008): relocation truncated to fit: R_MIPS_26 against `bar'
jal-global-multi-overflow.o: In function `bar':
(.text+0x4000): relocation truncated to fit: R_MIPS_26 against `foo'
(.text+0x4008): relocation truncated to fit: R_MIPS_26 against `foo'
$
respectively instead. Adjust the test suite accordingly.
ld/
* ldmisc.c (vfinfo): Don't print the function name again either
if no source file name has been found both now and previously.
* testsuite/ld-cris/tls-err-20x.d: Adjust accordingly.
* testsuite/ld-mips-elf/mode-change-error-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-mips16.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-micromips.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-2.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jump.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jump-mips16.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jump-micromips.d: Likewise.
* testsuite/ld-mips-elf/unaligned-lwpc-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-ldpc-1.d: Likewise.
* testsuite/ld-powerpc/tocopt.out: Likewise.
* testsuite/ld-powerpc/tocopt7.out: Likewise.
This patch fixes a number of issues with powerpc dynamic relocations.
1) Both ppc and ppc64 were emitting more dynamic symbols and
relocations than necessary, due to not supporting static linker
resolution of tls_index entries for __tls_get_addr_opt. This meant
that any @got@tlsgd or @got@tlsld reloc needed to make their symbols
dynamic and generate dptmod and dtprel relocs for the dynamic linker.
That would have been passable, but what happened was that practically
all @got relocations resulted in their symbols being made dynamic and
dynamic relocations emitted against the GOT entries. (Mostly visible
on ppc32 executables since ppc64 gcc really only uses @got style
relocs for TLS.)
2) The PowerOpen syntax was not supported with __tls_get_addr_opt.
DTPMOD/DTPREL relocs on tls_index TOC entries did not use the trick of
forcing dynamic symbols and relocations so those entries always
resulted in the full __tls_get_addr processing. gcc doesn't use the
PowerOpen syntax for TLS, and normally such code would be optimized to
TLS IE or LE so the impact of missing this support was minimal.
3) In an executable, relocations against GNU indirect functions always
used the value of their PLT stub. While this is correct, it is
better in some cases to use a dynamic relocation. An extra dynamic
relocation can mean that calls via function pointers need not bounce
through the PLT stub at runtime.
The patch also tidies the PLT handling code in ppc32
allocate_dynrelocs. Allocating PLT entries after other dynamic relocs
allows the PLT loop to omit special handling for undefined weak
symbols, and that in turn allows the loop to be simplified.
bfd/
* elf32-ppc.c (ppc_elf_adjust_dynamic_symbol): Merge two cases
where dynamic relocs are preferable. Allow ifunc too.
(ensure_undefweak_dynamic): New function.
(allocate_dynrelocs): Use it here. Move plt handling last and
don't make symbols dynamic, simplifying loop. Only make undef
weak symbols with GOT entries dynamic. Correct condition
for GOT relocs. Handle dynamic relocs on ifuncs. Correct
comments. Remove goto.
(ppc_elf_relocate_section): Correct test for using dynamic
symbol on GOT relocs. Rearrange test for emitting GOT relocs
to suit. Set up explicit tls_index entries and implicit GOT
tls_index entries resolvable at link time for
__tls_get_addr_opt. Simplify test to clear mem for prelink.
* elf64-ppc.c (allocate_got): Correct condition for GOT relocs.
(ensure_undefweak_dynamic): New function.
(allocate_dynrelocs): Use it here. Only make undef weak symbols
with GOT entries dynamic. Remove unnecessary test of
WILL_CALL_FINISH_DYNAMIC_SYMBOL in PLT handling.
(ppc64_elf_relocate_section): Correct test for using dynamic
symbol on GOT relocs. Rearrange test for emitting GOT relocs
to suit. Set up explicit tls_index entries and implicit GOT
tls_index entries resolvable at link time for __tls_get_addr_opt.
Simplify expression to clear mem for prelink.
ld/
* testsuite/ld-powerpc/tlsexe.r: Update for fewer dynamic relocs
and symbols.
* testsuite/ld-powerpc/tlsexe.d: Likewise.
* testsuite/ld-powerpc/tlsexe.g: Likewise.
Recognize power9 and a few other insns from older machines. Fixes
linker complaints like "toc optimization is not supported for
0xf4090002 instruction". 0xf4090002 is stxsd v0,0(r9)
bfd/
* elf64-ppc.c (ok_lo_toc_insn): Add r_type param. Recognize
lq,lfq,lxv,lxsd,lxssp,lfdp,stq,stfq,stxv,stxsd,stxssp,stfdp.
Don't match lmd and stmd.
ld/
* testsuite/ld-powerpc/tocopt7.s,
* testsuite/ld-powerpc/tocopt7.out,
* testsuite/ld-powerpc/tocopt7.d: New test.
* testsuite/ld-powerpc/tocopt8.s,
* testsuite/ld-powerpc/tocopt8.d: New test.
* testsuite/ld-powerpc/powerpc.exp: Run them.
Lots of fixes for the compatibility code that handles linking of
-mcall-aixdesc code (or that generated by 12 year old gcc) with
current ELFv1 ABI code.
1) A reference to a dot-symbol in an object file wasn't satisfied by a
function descriptor in later object files.
2) The as-needed code had bit-rotted; Shared libs now need a strong
reference to be counted as needed.
3) --gc-sections involving dot-symbols was broken, needing
func_desc_adjust to be run early and lots of other fixes.
bfd/
* elf64-ppc.c (struct ppc_link_hash_entry): Delete "was_undefined".
(struct ppc_link_hash_table): Delete "twiddled_syms". Add
"need_func_desc_adj".
(lookup_fdh): Link direct fdh sym via oh field and set flags.
(make_fdh): Make strong and weak undefined function descriptor
symbols.
(ppc64_elf_merge_symbol): New function.
(elf_backend_merge_symbol): Define.
(ppc64_elf_archive_symbol_lookup): Don't test undefweak for fake
function descriptors.
(add_symbol_adjust): Don't twiddle symbols to undefweak.
Propagate more ref flags to function descriptor symbol. Make
some function descriptor symbols dynamic.
(ppc64_elf_before_check_relocs): Only run add_symbol_adjust for
ELFv1. Set need_func_desc_adj. Don't fix undefs list.
(ppc64_elf_check_relocs): Set non_ir_ref for descriptors.
Don't call lookup_fdh here.
(ppc64_elf_gc_sections): New function.
(bfd_elf64_bfd_gc_sections): Define.
(ppc64_elf_gc_mark_hook): Mark descriptor.
(func_desc_adjust): Don't make fake function descriptor syms strong
here. Exit earlier on non-dotsyms. Take note of elf.dynamic
flag when deciding whether a dynamic function descriptor might
be needed. Transfer elf.dynamic and set elf.needs_plt. Move
plt regardless of visibility. Make descriptor dynamic if
entry sym is dynamic, not for other cases.
(ppc64_elf_func_desc_adjust): Don't run func_desc_adjust if
already done.
(ppc64_elf_edit_opd): Use oh field rather than lookup_fdh.
(ppc64_elf_size_stubs): Likewise.
(ppc_build_one_stub): Don't clear was_undefined. Only set sym
undefweak if stub symbol is defined.
(undo_symbol_twiddle, ppc64_elf_restore_symbols): Delete.
* elf64-ppc.h (ppc64_elf_restore_symbols): Don't declare.
ld/
* emultempl/ppc64elf.em (gld${EMULATION_NAME}_finish): Don't call
ppc64_elf_restore_symbols.
* testsuite/ld-powerpc/dotsym1.d: New.
* testsuite/ld-powerpc/dotsym2.d: New.
* testsuite/ld-powerpc/dotsym3.d: New.
* testsuite/ld-powerpc/dotsym4.d: New.
* testsuite/ld-powerpc/dotsymref.s: New.
* testsuite/ld-powerpc/nodotsym.s: New.
* testsuite/ld-powerpc/powerpc.exp: Run new tests.
PR ld/20815
bfd * elf.c (elf_modify_segment_map): Allow empty LOAD segments if
they contain the program headers.
(_bfd_elf_map_sections_to_segments): If the linker created the
PHDR segment then always attempt to include it in a LOAD segment.
(assign_file_positions_for_non_load_sections): Allow LOAD segments
to overlap PHDR segments.
(phdr_sorter): New function. Sorts program headers.
(assign_file_positions_except_relocs): Sort the program headers
before writing them out. Issue an error if the PHDR segment is
not covered by a LOAD segment, unless the backend allows it.
* elf-bfd.h (struct elf_backend_data): Add
elf_backend_allow_non_load_phdr.
* elfxx-target.h (elf_backend_allow_non_load_phdr): Provide
default definition that returns FALSE.
(elfNN_bed): Initialise the elf_backend_allow_non_load_phdr
field.
* elf64-hppa.c (elf64_hppa_allow_non_load_phdr): New function.
Returns TRUE.
(elf_backend_allow_non_load_phdr): Define.
* elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Do not
place the interpreter string into the .interp section if the
nointerp flag is set in the link info structure.
* elf32-arc.c (elf_arc_size_dynamic_sections): Likewise.
* elf32-score7.c (score_elf_final_link_relocate): Allow for the
_gp symbol not being part of the output.
binutils* readelf.c (process_program_headers): Check PT_LOAD and PT_PHDR
segments for validity.
ld * ld.texinfo: Note that PT_TLS can be used as a segment type.
* testsuite/ld-discard/discard.ld: Add space for program headers.
* testsuite/ld-elf/flags1.ld: Likewise.
* testsuite/ld-elf/maxpage3.t: Likewise.
* testsuite/ld-elf/noload-1.t: Likewise.
* testsuite/ld-elf/orphan.ld: Likewise.
* testsuite/ld-elf/overlay.t: Likewise.
* testsuite/ld-elf/pr14052.t: Likewise.
* testsuite/ld-elf/pr19539.t: Likewise.
* testsuite/ld-elf/provide-hidden-1.ld: Likewise.
* testsuite/ld-elf/provide-hidden-s.ld: Likewise.
* testsuite/ld-elf/weak-dyn-1.ld: Likewise.
* testsuite/ld-i386/pr19539.t: Likewise.
* testsuite/ld-scripts/defined.t: Likewise.
* testsuite/ld-scripts/defined6.t: Likewise.
* testsuite/ld-scripts/dynamic-sections.t: Likewise.
* testsuite/ld-scripts/empty-aligned.t: Likewise.
* testsuite/ld-scripts/provide-2.t: Likewise.
* testsuite/ld-scripts/provide-4.t: Likewise.
* testsuite/ld-vax-elf/plt-local.ld: Likewise.
* testsuite/ld-x86-64/pr19539.t: Likewise.
* testsuite/ld-elf/ehdr_start-missing.d: Do not initialise the
dynamic linker.
* testsuite/ld-elf/ehdr_start-weak.d: Likewise.
* testsuite/ld-elf/elf.exp (pr14170, pr17068): Likewise.
* testsuite/ld-elf/loadaddr1.d: Update expected readelf output.
* testsuite/ld-elf/noload-2.d: Likewise.
* testsuite/ld-powerpc/vxworks2.sd: Likewise.
* testsuite/ld-scripts/phdrs3a.d: Likewise.
* testsuite/ld-scripts/size-2.d: Likewise.
* testsuite/ld-elf/group.ld: Add program headers.
* testsuite/ld-elf/overlay.d: Skip for SPU.
* testsuite/ld-elf/flags1.d: Skip for RX.
* testsuite/ld-elf/pr19162.d: Skip for HPPA64.
* testsuite/ld-elf/pr19539.d: Skip for ALPHA.
* testsuite/ld-scripts/empty-orphan.t: Update program headers.
* testsuite/ld-scripts/size-2.t: Likewise.
This patch extends Tag_GNU_Power_ABI_FP to cover long double ABIs,
makes the assembler warn about undefined tag values, and removes
similar warnings from the linker. I think it is better to not
warn in the linker about undefined tag values as future extensions to
the tags then won't result in likely bogus warnings. This is
consistent with the fact that an older linker won't warn on an
entirely new tag.
include/
* elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment.
bfd/
* elf-bfd.h (_bfd_elf_ppc_merge_fp_attributes): Declare.
* elf32-ppc.c (_bfd_elf_ppc_merge_fp_attributes): New function.
(ppc_elf_merge_obj_attributes): Use it. Don't copy first file
attributes, merge them. Don't warn about undefined tag bits,
or copy unknown values to output.
* elf64-ppc.c (ppc64_elf_merge_private_bfd_data): Call
_bfd_elf_ppc_merge_fp_attributes.
binutils/
* readelf.c (display_power_gnu_attribute): Catch truncated section
for all powerpc attributes. Display long double ABI. Don't
capitalize words, except for names. Show known bits of tag values
when some unknown bits are present. Whitespace fixes.
gas/
* config/tc-ppc.c (ppc_elf_gnu_attribute): New function.
(md_pseudo_table <ELF>): Handle "gnu_attribute".
ld/
* testsuite/ld-powerpc/attr-gnu-4-4.s: Delete.
* testsuite/ld-powerpc/attr-gnu-4-14.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-24.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-34.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-41.d: Delete.
* testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning.
* testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output.
* testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise.
* testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests.
binutils/
PR binutils/20337
* objdump.c (compare_symbols): For ELF, sort same value/type
symbols according to size.
ld/
* testsuite/ld-powerpc/elfv2exe.d: Update.
VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE. For
example
{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe. Also, we don't check
user assembly against the processor type as well as we could.
Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31. Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.
This patch fixes those problems in the opcode table, and removes
PPCNONE. I find a plain 0 distracts less from other values.
In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects. It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.
include/
* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
PPC_APUINFO_VLE: Define.
opcodes/
* ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
cpu for "vle" to e500.
* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
(PPCNONE): Delete, substitute throughout.
(powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
except for major opcode 4 and 31.
(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
to match other 32-bit archs.
* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
(ppc_elf_object_p): Call it.
(ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
overlong line.
(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
_bfd_elf_ppc_at_tprel_transform): Move to..
* elf-bfd.h: ..here.
(_bfd_elf_ppc_set_arch): Declare.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
add vle_opcodes twice.
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
* testsuite/ld-powerpc/apuinfo-vle2.s: New.
* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
Commit 23283c1b changed the layout of some bss style sections on
powerpc64, but neglected to add a page gap before the third PT_LOAD
segment created by this reording. Without a page gap we get two
PT_LOAD headers that overlap by one page in memory. That shouldn't be
allowed because the dynamic loader will load garbage from the first
page of the last segment over the last page of the previous segment.
bfd/
* elf.c (_bfd_elf_map_sections_to_segments): Do not make a new
segment for loaded sections after nonloaded sections if the
sections are on the same page.
ld/testsuite/
* ld-powerpc/elfv2so.d: Update
bfd/
* elf64-ppc.c (toc_adjusting_stub_needed): Use the symbol value
plus addend rather than the original st_value when looking up
entries in opd->adjust.
ld/testsuite/
* ld-powerpc/tocopt6-inc.s, ld-powerpc/tocopt6a.s,
ld-powerpc/tocopt6b.s, ld-powerpc/tocopt6c.s,
ld-powerpc/tocopt6.d: New test.
* ld-powerpc/powerpc.exp (ppc64elftests): Add it.
When building a shared lib from non-PIC objects, we'll get dynamic
text relocations. These need to move with any insns we move.
Otherwise the dynamic reloc will modify the branch, resulting in
crashes and other unpleasant behaviour.
Also, ld -r --ppc476-workaround used with sufficiently aligned PIC
objects needs a fix for emitted REL16 relocs.
bfd/
* elf64-ppc.c (ppc_elf_relocate_section): Move dynamic text
relocs with insns moved by --ppc476-workaround. Correct
output of REL16 relocs.
ld/testsuite/
* ld-powerpc/ppc476-shared.s,
* ld-powerpc/ppc476-shared.lnk,
* ld-powerpc/ppc476-shared.d,
* ld-powerpc/ppc476-shared2.d: New tests.
* ld-powerpc/powerpc.exp: Run them.
Taking them out showed a bug in the powerpc64 backend with .branch_lt
being removed from output_bfd but not from previously set up segment
section maps. Removing the bfd sections meant their sh_flags (and
practically everything else) remaining zero, ie. not SHF_ALLOC,
triggering complaints about "`.branch_lt' can't be allocated in
segment".
include/elf/
* internal.h (ELF_SECTION_IN_SEGMENT_1): Ensure PT_LOAD and
similar segments only contain alloc sections.
ld/
* emultempl/ppc64elf.em (gld${EMULATION_NAME}_after_allocation):
Call gld${EMULATION_NAME}_map_segments regardless of need_laying_out.
ld/testsuite/
* ld-powerpc/tocnovar.d: Revert last change.
I didn't commit this with the relro and powerpc .TOC. changes,
thinking that something should be done about the odd result of
.shstrtab appearing in PT_GNU_RELRO. On looking at it further,
I think that changing readelf would be wrong, so let's just
accept the results. Real binaries will always have other sections
past .got, so PT_GNU_RELRO won't finish past the end of loaded
sections.
* ld-powerpc/tocnovar.d: Adjust.
I was having a little closer look at what is going on here and noticed
that HJ unconditionally emits a NULL STT_FILE symbol before emitting
forced local symbols. That means we really don't need a second pass
over forced local symbols. The only reason for two passes is when
some forced local symbol can be emitted before the NULL STT_FILE. So
I set about removing the second pass, updating the testsuite all over
again. It's also unnecessary to emit the NULL STT_FILE when no
previous file symbol has been emitted.
bfd/
PR ld/17975
* elflink.c (struct elf_outext_info): Remove need_second_pass
and second_pass.
(elf_link_output_extsym): Delete code handling second forced
local pass. Move code emitting NULL STT_FILE symbol later, so
that it can be omitted if forced local is stripped. Don't
emit the NULL STT_FILE if no file symbols have been output.
(bfd_elf_final_link): Remove second forced local pass.
* elf32-ppc.c (add_stub_sym): Set linker_def on linker syms.
(ppc_elf_size_dynamic_sections): Likewise.
* elf64-ppc.c (ppc_build_one_stub): Likewise.
(build_global_entry_stubs): Likewise.
(ppc64_elf_build_stubs): Likewise.
ld/testsuite/
PR ld/17975
* ld-aarch64/gc-tls-relocs.d, * ld-alpha/tlspic.rd,
* ld-cris/libdso-2.d, * ld-i386/tlsdesc-nacl.rd, * ld-i386/tlsdesc.rd,
* ld-i386/tlsnopic-nacl.rd, * ld-i386/tlsnopic.rd,
* ld-i386/tlspic-nacl.rd, * ld-i386/tlspic.rd, * ld-ia64/tlspic.rd,
* ld-powerpc/tlsexe.r, * ld-powerpc/tlsexetoc.r,
* ld-powerpc/tlsso.r, * ld-powerpc/tlstocso.r,
* ld-s390/tlspic.rd, * ld-s390/tlspic_64.rd,
* ld-sparc/tlssunnopic32.rd, * ld-sparc/tlssunnopic64.rd,
* ld-sparc/tlssunpic32.rd, * ld-sparc/tlssunpic64.rd,
* ld-tic6x/shlib-1.rd, * ld-tic6x/shlib-1b.rd, * ld-tic6x/shlib-1r.rd,
* ld-tic6x/shlib-1rb.rd, * ld-tic6x/shlib-noindex.rd,
* ld-x86-64/tlsdesc-nacl.rd, * ld-x86-64/tlsdesc.rd,
* ld-x86-64/tlspic-nacl.rd, * ld-x86-64/tlspic.rd: Update.
The linker hardcoded r3 into a local-dynamic to local-exec TLS
optimization sequence. This is normally the case since r3 is required
as a parameter to (the optimized out) __tls_get_addr call. However,
it is possible for a compiler, LLVM in this case, to set up the
parameter value in another register then copy it to r3 before the
call.
When fixing this problem, I noticed that ppc32 had another bug when
optimizing away one of the TLS insns to a nop.
The patch also tidies a mask used by global-dynamic to initial-exec
TLS optimization, to just select the fields needed. Leaving the
offset in the instruction wasn't a bug since it will be overwritten
anyway.
bfd/
* elf64-ppc.c (ppc64_elf_relocate_section): Correct GOT_TLSLD
optimization. Tidy mask for GOT_TLSGD optimization.
* elf32-ppc.c (ppc_elf_relocate_section): Likewise. Correct
location of nop zapping high insn too.
ld/testsuite/
* ld-powerpc/tlsld.d, * ld-powerpc/tlsld.s: New test.
* ld-powerpc/tlsld32.d, * ld-powerpc/tlsld32.s: New test.
* ld-powerpc/powerpc.exp: Run them. Move tocvar and tocnovar.
The changes to reorder sections for better relro protection on powerpc64,
3e2b0f31, 23283c1b, and 5ad18f16, run into a problem with xlc.
xlc -qdatalocal puts global variables into .toc, which means that .toc
must be writable. The simplest way to accomplish this is to edit the
linker script to remove .toc sections from .got on detecting xlc object
files.
bfd/
* elf64-ppc.h (struct ppc64_elf_params): Add "object_in_toc".
* elf64-ppc.c (ppc64_elf_add_symbol_hook): Assume that global symbols
in .toc indicate xlc compiled code that might require a rw .toc.
ld/
* emulparams/elf64ppc.sh (INITIAL_READWRITE_SECTIONS): Define.
* emultempl/ppc64elf.em (params): Init new field.
(ppc_after_open): New function.
(LDEMUL_AFTER_OPEN): Define.
* ldlang.c (lang_final): Whitespace fix.
ld/testsuite/
* ld-powerpc/tocvar.d, * ld-powerpc/tocvar.s: New test.
* ld-powerpc/tocnovar.d, * ld-powerpc/tocnovar.s: New test.
* ld-powerpc/powerpc.exp: Run tocvar and tocnovar.
This moves .got too, which requires .sdata and .sbss to move with it,
because these sections share addressing via the toc pointer and with
small-model code must be within a 16-bit signed offset. .plt, .iplt
and .branch_lt must also be moved since they are addressed via a
32-bit offset from the toc pointer, and we might have a very large
.data section.
This change means we may have some bss style sections before the data
segment, necessitating another PT_LOAD header. Also, since _edata is
defined at the end of the data segment it's possible with an empty
.data to have _edata at the end of .plt which looks a little unusual
since .plt is a bss style section. That should only happen rarely in
real world binaries, but does occur in the ld testsuite.
ld/
* emulparams/elf64ppc.sh (BSS_PLT): Don't define.
(OTHER_READWRITE_SECTIONS): Move .branch_lt to..
(OTHER_RELRO_SECTIONS_2): ..here.
(DATA_GOT, SEPARATE_GOTPLT, DATA_SDATA, DATA_PLT,
PLT_BEFORE_GOT): Define.
* scripttempl/elf.sc: Handle DATA_SDATA and DATA_GOT/DATA_PLT/
PLT_BEFORE_GOT combination.
(DATA_GOT, SDATA_GOT): Don't define if either is already defined.
ld/testsuite/
* ld-powerpc/ambiguousv1.d,
* ld-powerpc/ambiguousv1b.d,
* ld-powerpc/ambiguousv2.d,
* ld-powerpc/ambiguousv2b.d,
* ld-powerpc/elfv2exe.d,
* ld-powerpc/elfv2so.d,
* ld-powerpc/tlsexe.r,
* ld-powerpc/tlsexetoc.r,
* ld-powerpc/tlsso.r,
* ld-powerpc/tlstocso.r: Update.
Trying to use the SEC_LINKER_CREATED section flag to determine whether
a symbol is linker defined fails to work on targets like alpha that
define special SEC_COMMON sections. These might contain symbols that
originated in an object file.
include/
* bfdlink.h (struct bfd_link_hash_entry): Comment non_ir_ref. Add
linker_def.
bfd/
* elflink.c (_bfd_elf_define_linkage_sym): Set linker_def.
* linker.c (_bfd_generic_link_add_one_symbol): Clear linker_def
for CDEF, DEF, DEFW, COM.
ld/
* ldexp.c (exp_fold_tree_1 <etree_provide>): Test linker_def.
ld/testsuite/
* ld-powerpc/sdabase.s,
* ld-powerpc/sdabase.t,
* ld-powerpc/sdabase.d: New test.
* ld-powerpc/sdabase2.t,
* ld-powerpc/sdabase2.d: New test.
* ld-powerpc/powerpc.exp: Run them.
Only set the VLE flag if the instruction has been pulled via the VLE
instruction set. This way the flag is guaranteed to be set for VLE-only
instructions or for VLE-only processors, however it'll remain clear for
dual-mode instructions on dual-mode and, more importantly, standard-mode
processors.
gas/
* config/tc-ppc.c (md_assemble): Only set the PPC_APUINFO_VLE
flag if both the processor and opcode flags match.
ld/testsuite/
* ld-powerpc/apuinfo-vle.rd: New test.
* ld-powerpc/apuinfo-vle.s: New test source.
* ld-powerpc/apuinfo.rd: Adjust according to GAS PPC_APUINFO_VLE
handling change.
* ld-powerpc/powerpc.exp: Run the new test.
This fixes a problem seen on powerpc64le ELFv2 when creating a
function symbol alias with ld --defsym. st_other needs to be copied
from the source symbol to the alias in order to set up the local entry
offset for the alias. I decided to make this change in the generic
ELF code rather than in elf64-ppc.c since it looks like other targets
that use st_other bits might benefit too.
bfd/
* elflink.c (_bfd_elf_copy_link_hash_symbol_type): Copy st_other
bits from source to dest.
* linker.c (_bfd_generic_copy_link_hash_symbol_type): Update comment.
* targets.c (struct bfd_target <_bfd_copy_link_hash_symbol_type>):
Likewise.
* bfd-in2.h: Regenerate.
ld/testsuite/
* ld-powerpc/defsym.s, * ld-powerpc/defsym.d: New test.
* ld-powerpc/powerpc.exp: Run it.
doesn't always mean you need to define a function symbol on plt code.
If all references are in read-write sections, then using dynamic relocs
is OK.
bfd/
* elf32-ppc.c (ppc_elf_adjust_dynamic_symbol): Clear
pointer_equality_needed when !readonly_dynrelocs.
* elf64-ppc.c (ppc64_elf_adjust_dynamic_symbol): Likewise.
ld/testsuite/
* ld-powerpc/ambiguousv1.d: Match symbol table too.
* ld-powerpc/ambiguousv2.d: Likewise.
* ld-powerpc/ambiguousv1b.d: New.
* ld-powerpc/ambiguousv2b.d: New.
* ld-powerpc/powerpc.exp: Run new tests.
Power8 fuses addis,addi and addis,ld sequences when the target of the
addis is the same as the addi/ld. Thus
addis r12,r2,xxx@ha
addi r12,r12,xxx@l / ld r12,xxx@l(r12)
is faster than
addis r11,r2,xxx@ha
addi r12,r11,xxx@l / ld r12,xxx@l(r11)
So use the form that allows fusion in plt call and branch stubs.
bfd/
* elf64-ppc.c (ADDIS_R12_R2): Define.
(build_plt_stub): Support fusion on ELFv2 stub.
(ppc_build_one_stub): Likewise for plt branch stubs.
gold/
* powerpc.cc (addis_12_2): Define.
(Stub_table::do_write): Support fusion on ELFv2 stubs.
ld/testsuite/
* ld-powerpc/elfv2exe.d: Update for changed plt call stubs.
gdb/
* ppc64-tdep.c (ppc64_standard_linkage8): New.
(ppc64_skip_trampoline_code): Recognise ELFv2 stub supporting fusion.
ELFv2 needs to create plt entries in a non-PIC executable for an
address reference to a function defined in a shared object. It's
possible that an object file has no features that distinguish it as
ELFv1 or ELFv2, eg. an object only containing data. Such files need
to be handled like those that are known to be ELFv2.
However, this unnecessarily creates plt entries for the analogous
ELFv1 case, so arrange to set output abi version earlier, and use the
output abi version to further distinguish ambiguous input files.
bfd/
* elf64-ppc.c (ppc64_elf_check_relocs): Account for possibly
needed plt entries when taking the address of functions for
abiversion == 0 (ie. unknown) as well as abiversion == 2.
Move opd setup and abiversion checks to..
(ppc64_elf_before_check_relocs): ..here. Renamed from
ppc64_elf_process_dot_syms. Set output abiversion from input and
input abiversion from output, if either is not set.
(ppc64_elf_merge_private_bfd_data): Don't merge flags here.
(elf_backend_check_directives): Update.
ld/testsuite/
* ld-powerpc/startv1.s, * ld-powerpc/startv2.s, * ld-powerpc/funref.s,
* ld-powerpc/funv1.s, * ld-powerpc/funv2.s,
* ld-powerpc/ambiguousv1.d, * ld-powerpc/ambiguousv2.d: New test files.
* ld-powerpc/powerpc.exp: Run new tests.
This adds support for "func@localentry", an expression that returns the
ELFv2 local entry point address of function "func". I've excluded
dynamic relocation support because that obviously would require glibc
changes.
include/elf/
* ppc64.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define.
bfd/
* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_ADDR64_LOCAL entry.
(ppc64_elf_reloc_type_lookup): Support R_PPC64_ADDR64_LOCAL.
(ppc64_elf_check_relocs): Likewise.
(ppc64_elf_relocate_section): Likewise.
* Add BFD_RELOC_PPC64_ADDR64_LOCAL.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): Support @localentry.
(md_apply_fix): Support R_PPC64_ADDR64_LOCAL.
ld/testsuite/
* ld-powerpc/elfv2-2a.s, ld-powerpc/elfv2-2b.s: New files.
* ld-powerpc/elfv2-2exe.d, ld-powerpc/elfv2-2so.d: New files.
* ld-powerpc/powerpc.exp: Run new test.
elfcpp/
* powerpc.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define.
gold/
* powerpc.cc (Target_powerpc::Scan::local, global): Support
R_PPC64_ADDR64_LOCAL.
(Target_powerpc::Relocate::relocate): Likewise.
An assignment to dot in an output section that allocates space of
course keeps the output section. Here, I'm changing the behaviour for
assignments that don't allocate space. The idea is not so much to
allow people to force output of an empty section with ". = .", but
to fix cases where an otherwise empty section has padding added by an
alignment expression that changes with relaxation or .eh_frame
editing. Such a section might have zero size before relaxation and so
be stripped incorrectly.
ld/
* ld.texinfo (Output Section Discarding): Mention assigning to dot
as a way of keeping otherwise empty sections.
* ldexp.c (is_dot, is_value, is_sym_value, is_dot_ne_0,
is_dot_plus_0, is_align_conditional): New predicates.
(exp_fold_tree_1): Set SEC_KEEP when assigning to dot inside an
output section, except for some special cases.
* scripttempl/elfmicroblaze.sc: Use canonical form to align at
end of .heap and .stack.
ld/testsuite/
* ld-shared/elf-offset.ld: Align end of .bss with canonical form
of ALIGN that allows an empty .bss to be removed.
* ld-arm/arm-dyn.ld: Likewise.
* ld-arm/arm-lib.ld: Likewise.
* ld-elfvsb/elf-offset.ld: Likewise.
* ld-mips-elf/mips-dyn.ld: Likewise.
* ld-mips-elf/mips-lib.ld: Likewise.
* ld-arm/arm-no-rel-plt.ld: Remove duplicate ALIGN.
* ld-powerpc/vle-multiseg-1.ld: Remove ALIGN at start of section.
ALIGN address of section instead.
* ld-powerpc/vle-multiseg-2.ld: Likewise.
* ld-powerpc/vle-multiseg-3.ld: Likewise.
* ld-powerpc/vle-multiseg-4.ld: Likewise.
* ld-powerpc/vle-multiseg-6.ld: Likewise.
* ld-scripts/empty-aligned.d: Check section headers not program
headers. Remove xfail and notarget.
* ld-scripts/empty-aligned.t: Use canonical ALIGN for end of .text2.
Changing addis r2,r12,..; addi r2,r2,.. to lis r2,..; addi r2,r2..
in non-PIC executables has the benefit of removing a dependency on r12.
bfd/
* elf64-ppc.c (ppc64_elf_relocate_section): Edit global entry
prologue to non-PIC in non-PIC executables.
ld/testsuite/
* ld-powerpc/elfv2exe.d: Adjust for non-PIC global entry.
This change is to support the new ELFv2 ABI, which uses the value in
r12 on function entry to calculate the got/toc pointer.
bfd/
* elf64-ppc.c (build_plt_stub): Switch stubs to use r11 as base
reg and r12 as destination.
(ppc_build_one_stub): Likewise.
(ppc64_elf_build_stubs): Likewise for glink.
ld/testsuite/
* ld-powerpc/tls.s: Add proper .opd entry for _start.
* ld-powerpc/tlstoc.s: Likewise.
* ld-powerpc/relbrlt.d: Update for changed stubs.
* ld-powerpc/tls.d: Update for changed stubs and _start .opd entry.
* ld-powerpc/tls.g: Likewise.
* ld-powerpc/tlsexe.d: Likewise.
* ld-powerpc/tlsexe.g: Likewise.
* ld-powerpc/tlsexe.r: Likewise.
* ld-powerpc/tlsexetoc.d: Likewise.
* ld-powerpc/tlsexetoc.g: Likewise.
* ld-powerpc/tlsexetoc.r: Likewise.
* ld-powerpc/tlsso.d: Likewise.
* ld-powerpc/tlsso.g: Likewise.
* ld-powerpc/tlsso.r: Likewise.
* ld-powerpc/tlstoc.d: Likewise.
* ld-powerpc/tlstoc.g: Likewise.
* ld-powerpc/tlstocso.d: Likewise.
* ld-powerpc/tlstocso.g: Likewise.
* ld-powerpc/tlstocso.r: Likewise.
