Commit Graph

312 Commits

Author SHA1 Message Date
Sam James
b5c37946cc Revert "2.41 Release sources"
This reverts commit 675b9d612c.

See https://sourceware.org/pipermail/binutils/2023-August/128761.html.
2023-08-02 12:06:23 +01:00
Nick Clifton
675b9d612c 2.41 Release sources 2023-08-02 09:23:36 +01:00
Hu, Lin1
cd2908958a Support Intel PBNDKB
gas/ChangeLog:

	* NEWS: Support Intel PBNDKB.
	* config/tc-i386.c: Add pbndkb.
	* doc/c-i386.texi: Document .pbndkb.
	* testsuite/gas/i386/i386.exp: Add PBNDKB tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/pbndkb-inval.l: New test.
	* testsuite/gas/i386/pbndkb-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-pbndkb-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-pbndkb.d: Ditto.
	* testsuite/gas/i386/x86-64-pbndkb.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_7): New.
	(X86_64_0F01_REG_0_MOD_3_RM_7_P_0): Ditto.
	(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_7.
	(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_7_P_0.
	(rm_table): New entry for pbndkb.
	* i386-gen.c (cpu_flag): Add PBNDKB.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuPBNDKB): New.
	(i386_cpu_flags): Add cpupbndkb.
	* i386-opc.tbl: Add PBNDKB instructions.
	* i386-tbl.h: Regenerated.
2023-07-27 20:52:52 +08:00
Haochen Jiang
2bced1684b Support Intel SM4
gas/ChangeLog:

	* NEWS: Support Intel SM4.
	* config/tc-i386.c: Add sm4.
	* doc/c-i386.texi: Document .sm4.
	* testsuite/gas/i386/i386.exp: Run SM4 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/sm4-intel.d: Add SM4 tests.
	* testsuite/gas/i386/sm4.d: Ditto.
	* testsuite/gas/i386/sm4.s: Ditto.
	* testsuite/gas/i386/x86-64-sm4-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-sm4.d: Ditto.
	* testsuite/gas/i386/x86-64-sm4.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (prefix_table): Add SM4 instructions.
	* i386-gen.c (isa_dependencies): Add SM4.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuSM4): New.
	(i386_cpu_flags): Add cpusm4.
	* i386-opc.tbl: Add SM4 instructions.
	* i386-tbl.h: Regenerated.
2023-07-27 20:52:46 +08:00
Haochen Jiang
c55ba32b7a Support Intel SM3
gas/ChangeLog:

	* NEWS: Support Intel SM3.
	* config/tc-i386.c: Add sm3.
	* doc/c-i386.texi: Document .sm3.
	* testsuite/gas/i386/i386.exp: Run sm3 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/sm3-intel.d: New test.
	* testsuite/gas/i386/sm3.d: Ditto.
	* testsuite/gas/i386/sm3.s: Ditto.
	* testsuite/gas/i386/x86-64-sm3-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-sm3.d: Ditto.
	* testsuite/gas/i386/x86-64-sm3.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_VEX_0F38DA_W_0): New.
	(VEX_LEN_0F38DA_W_0_P_0): Ditto.
	(VEX_LEN_0F38DA_W_0_P_2): Ditto.
	(VEX_LEN_0F3ADE_W_0): Ditto.
	(VEX_W_0F38DA): Ditto.
	(VEX_W_0F3ADE): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38DA_W_0.
	(vex_len_table): Add VEX_LEN_0F38DA_W_0_P_0,
	VEX_LEN_0F38DA_W_0_P_2, VEX_LEN_0F3ADE_W_0.
	(vex_w_table): Add VEX_W_0F38DA, VEX_W_0F3ADE.
	* i386-gen.c (isa_dependencies): Add SM3.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuSM3): New.
	(i386_cpu_flags): Add cpusm3.
	* i386-opc.tbl: Add SM3 instructions.
	* i386-tbl.h: Regenerated.
2023-07-27 20:52:25 +08:00
Haochen Jiang
3ac2eb9481 Support Intel SHA512
gas/ChangeLog:

	* NEWS: Support Intel SHA512.
	* config/tc-i386.c: Add sha512.
	* doc/c-i386.texi: Document .sha512.
	* testsuite/gas/i386/disassem.d: Add SHA512 tests.
	* testsuite/gas/i386/disassem.s: Ditto.
	* testsuite/gas/i386/i386.exp: Run SHA512 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/sha512-intel.d: New test.
	* testsuite/gas/i386/sha512-inval.l: Ditto.
	* testsuite/gas/i386/sha512-inval.s: Ditto.
	* testsuite/gas/i386/sha512.d: Ditto.
	* testsuite/gas/i386/sha512.s: Ditto.
	* testsuite/gas/i386/x86-64-sha512-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-sha512-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-sha512-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-sha512.d: Ditto.
	* testsuite/gas/i386/x86-64-sha512.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (Rxmmq): New.
	(Rymm): Ditto.
	(PREFIX_VEX_0F38CB): Ditto.
	(PREFIX_VEX_0F38CC): Ditto.
	(PREFIX_VEX_0F38CD): Ditto.
	(VEX_LEN_0F38CB_P_3_W_0): Ditto.
	(VEX_LEN_0F38CC_P_3_W_0): Ditto.
	(VEX_LEN_0F38CD_P_3_W_0): Ditto.
	(VEX_W_0F38CB_P_3): Ditto.
	(VEX_W_0F38CC_P_3): Ditto.
	(VEX_W_0F38CD_P_3): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC,
	PREFIX_VEX_0F38CD.
	(vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0,
	VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0.
	(vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3.
	* i386-gen.c (isa_dependencies): Add SHA512.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuSHA512): New.
	(i386_cpu_flags): Add cpusha512.
	* i386-opc.tbl: Add SHA512 instructions.
	* i386-tbl.h: Regenerated.
2023-07-27 20:52:17 +08:00
konglin1
3fde5f6e7d Support Intel AVX-VNNI-INT16
gas/ChangeLog:

	* NEWS: Support Intel AVX-VNNI-INT16.
	* config/tc-i386.c: Add avx_vnni_int16.
	* doc/c-i386.texi: Document avx_vnni_int16.
	* testsuite/gas/i386/i386.exp: Run AVX VNNI INT16 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/avx-vnni-int16-intel.d: New test.
	* testsuite/gas/i386/avx-vnni-int16.d: New test.
	* testsuite/gas/i386/avx-vnni-int16.s: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16-intel.d: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16.d: New test.
	* testsuite/gas/i386/x86-64-avx-vnni-int16.s: New test.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_VEX_0F38D2_W_0): New.
	(PREFIX_VEX_0F38D3_W_0): Ditto.
	(VEX_W_0F38D2_P_0): Ditto.
	(VEX_W_0F38D2_P_1): Ditto.
	(VEX_W_0F38D2_P_2): Ditto.
	(VEX_W_0F38D3_P_0): Ditto.
	(VEX_W_0F38D3_P_1): Ditto.
	(VEX_W_0F38D3_P_2): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38D2_W_0 and
	PREFIX_VEX_0F38D3_W_0.
	(vex_table): Add VEX_W_0F38D2 and VEX_W_0F38D3.
	(vex_w_table): Ditto.
	* i386-gen.c (isa_dependencies): Add AVX_VNNI_INT16.
	(cpu_flag): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h: (CpuAVX_VNNI_INT16): New.
	* i386-opc.tbl: Add Intel AVX_VNNI_INT16 instructions.
	* i386-tbl.h: Regenerated.
2023-07-27 20:51:20 +08:00
Zhang, Jun
c88ed92f0c Support Intel FRED LKGS
gas/ChangeLog:

	* NEWS: Support Intel FRED LKGS.
	* config/tc-i386.c: Add fred lkgs
	* doc/c-i386.texi: Document .fred, .lkgs.
	* testsuite/gas/i386/i386.exp: Add FRED LKGS tests
	* testsuite/gas/i386/x86-64-fred-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-fred.d: Ditto.
	* testsuite/gas/i386/x86-64-fred.s: Ditto.
	* testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-lkgs.d: Ditto.
	* testsuite/gas/i386/x86-64-lkgs.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c: New entry for fred, lkgs.
	* i386-gen.c: Add CPU_FRED CPU_LKGS.
	* i386-init.h : Regenerated.
	* i386-mnem.h : Regenerated.
	* i386-opc.h: Add fred, lkgs.
	* i386-opc.tbl: Add FRED, LKGS instructions.
	* i386-tbl.h: Regenerated.
2023-05-23 14:43:23 +08:00
liuhongt
cbf25f4705 Revert "Support Intel FRED LKGS"
This reverts commit e5a497fe38.
2023-05-23 14:42:20 +08:00
Zhang, Jun
e5a497fe38 Support Intel FRED LKGS
gas/ChangeLog:

        * NEWS: Support Intel FRED LKGS.
        * config/tc-i386.c: Add fred lkgs
        * doc/c-i386.texi: Document .fred, .lkgs.
        * testsuite/gas/i386/i386.exp: Add FRED LKGS tests
        * testsuite/gas/i386/x86-64-fred-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-fred.d: Ditto.
        * testsuite/gas/i386/x86-64-fred.s: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto.
        * testsuite/gas/i386/x86-64-lkgs.d: Ditto.
        * testsuite/gas/i386/x86-64-lkgs.s: Ditto.

opcodes/ChangeLog:

        * i386-dis.c: New entry for fred, lkgs.
        * i386-gen.c: Add CPU_FRED CPU_LKGS.
        * i386-init.h : Regenerated.
        * i386-mnem.h : Regenerated.
        * i386-opc.h: Add fred, lkgs.
        * i386-opc.tbl: Add FRED, LKGS instructions.
        * i386-tbl.h: Regenerated.
2023-05-23 13:50:40 +08:00
Haochen Jiang
d100d8c1f3 Support Intel AMX-COMPLEX
gas/ChangeLog:

	* NEWS: Support Intel AMX-COMPLEX.
	* config/tc-i386.c: Add amx_complex.
	* doc/c-i386.texi: Document .amx_complex.
	* testsuite/gas/i386/i386.exp: Run AMX-COMPLEX tests.
	* testsuite/gas/i386/amx-complex-inval.l: New test.
	* testsuite/gas/i386/amx-complex-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-amx-complex-bad.d: Ditto.
	* testsuite/gas/i386/x86-64-amx-complex-bad.s: Ditto.
	* testsuite/gas/i386/x86-64-amx-complex-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-amx-complex.d: Ditto.
	* testsuite/gas/i386/x86-64-amx-complex.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (MOD_VEX_0F386C_X86_64_W_0): New.
	(PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0): Ditto.
	(X86_64_VEX_0F386C): Ditto.
	(VEX_LEN_0F386C_X86_64_W_0_M_1): Ditto.
	(VEX_W_0F386C_X86_64): Ditto.
	(mod_table): Add MOD_VEX_0F386C_X86_64_W_0.
	(prefix_table): Add PREFIX_VEX_0F386C_X86_64_W_0_M_1_L_0.
	(x86_64_table): Add X86_64_VEX_0F386C.
	(vex_len_table): Add VEX_LEN_0F386C_X86_64_W_0_M_1.
	(vex_w_table): Add VEX_W_0F386C_X86_64.
	* i386-gen.c (cpu_flag_init): Add CPU_AMX_COMPLEX_FLAGS and
	CPU_ANY_AMX_COMPLEX_FLAGS.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuAMX_COMPLEX): New.
	(i386_cpu_flags): Add cpuamx_complex.
	* i386-opc.tbl: Add AMX-COMPLEX instructions.
	* i386-tbl.h: Regenerated.
2023-04-07 05:47:01 +00:00
Jan Beulich
edd6763868 x86: introduce .insn directive
For starters this deals with only very basic constructs.
2023-03-31 08:18:58 +02:00
Jan Beulich
cafa5ef72e x86: MONITOR/MWAIT are not SSE3 insns
These have their own CPUID bit and hence they should also have their own
separate control.
2023-02-24 13:59:35 +01:00
Jan Beulich
c3bb24f566 x86-64: don't permit LAHF/SAHF with "generic64"
The feature isn't universally available on 64-bit CPUs.

Note that in i386-gen.c:isa_dependencies[] I'm only adding it to models
where I'm certain the functionality exists. For Nocona and Core I'm
uncertain in particular.
2023-02-24 13:58:35 +01:00
Jan Beulich
aa1807419b x86: drop use of VEX3SOURCES
The attribute really specifies that the sum of register and memory
operands is 4. Express it like that in most places, while using the 2nd
(apart from XOP) CPU feature flags (FMA4) in reversed operand matching
logic.

With the use in build_modrm_byte() gone, part of an assertion there
also becomes meaningless - simplify that at the same time.

With all uses of the opcode modifier field gone, also drop that.
2023-02-10 08:15:11 +01:00
Jan Beulich
ddb6249593 x86: move (and rename) opcodespace attribute
This really isn't a "modifier" and rather ought to live next to the base
opcode anyway. Use the bits we presently have available to fit in the
field, renaming it to opcode_space. As an intended side effect this
helps readability at the use sites, by shortening the references quite a
bit.

In generated code arrange for human readable output, by using the
SPACE_* constants there rather than raw numbers. This may aid debugging
down the road.
2023-02-10 08:10:38 +01:00
Jan Beulich
06ceca3a90 x86: remove internationalization from i386-gen.c
This is a build time helper utility, which doesn't require translation.
2023-01-27 09:20:26 +01:00
Jan Beulich
a2e2f5ad74 x86: split i386-gen's opcode hash entry struct
All glibc malloc() implementations I've checked have a smallest
allocation size worth of 3 pointers, with an increment worth of 2
pointers. Hence mnemonics with multiple templates can be stored more
efficiently when maintaining the shared "name" field only in the actual
hash entry. (To express the shared nature, also convert "name" to by
pointer-to-const.)

While doing the conversation also pull out common code from the involved
if/else construct in expand_templates().
2023-01-20 10:18:40 +01:00
Jan Beulich
992dd393c9 x86: absorb allocation in i386-gen
When generating the mnemonic string table we already set up an
identifier for the following entry in a number of cases. Re-use that on
the next loop iteration rather than re-doing allocation and conversion.
2023-01-20 10:16:56 +01:00
Jan Beulich
3e451ee4a6 x86: re-use insn mnemonic strings as much as possible
Compact the mnemonic string table such that the tails of longer
mnemonics are re-used for shorter ones, going beyond what compilers
would typically do, but matching what ELF linkers may do when processing
SHF_MERGE|SHF_STRINGS sections. This reduces table size by about 12.5%.
2023-01-20 10:16:17 +01:00
Jan Beulich
5c13920291 x86: move insn mnemonics to a separate table
Using full pointers to reference the insn mnemonic strings is not very
efficient. With overall string size presently just slightly over 20k,
even a 16-bit value would suffice. Use "unsigned int" for now, as
there's no good use we could presently make of the otherwise saved 16
bits.

For 64-bit builds this reduces table size by 6.25% (prior to the recent
ISA extension additions it would have been 12.5%), with a similar effect
on cache occupation of table entries accessed. For PIE builds of gas
this also reduces the number of base relocations quite a bit (obviously
independent of bitness).
2023-01-20 10:15:48 +01:00
Alan Modra
d87bef3a7b Update year range in copyright notice of binutils files
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2023-01-01 21:50:11 +10:30
Jan Beulich
760ab3d0db x86: correct/improve TSX controls
TSXLDTRK takes RTM as a prereq. Additionally introduce an umbrella "tsx"
extension option covering both RTM and HLE, paralleling the "abm" one we
already have.
2022-12-22 09:36:16 +01:00
Jan Beulich
0919e770af x86: add dependencies on SVME
SEV-ES is an extension to SVME. SNP in turn is an extension to SEV-ES,
and yet in turn RMPQUERY is a SNP extension.

Note that cpu_arch[] has no SNP entry, so CPU_ANY_SNP_FLAGS remains
unused (just like CPU_SNP_FLAGS already is).
2022-12-22 09:35:53 +01:00
Jan Beulich
25626f7939 x86: add dependencies on VMX
Both EPT and VMFUNC are extensions to VMX.
2022-12-22 09:35:32 +01:00
Jan Beulich
af1ad9aac5 x86: correct XSAVE* dependencies
Like various other features AMX-TILE takes XSAVE as a prereq.

XSAVES, unconditionally using compacted format, in turn effectively
takes XSAVEC as a prereq (an SDM clarification to this effect is in the
works).
2022-12-22 09:35:11 +01:00
Jan Beulich
9a019125a6 x86: correct dependencies of a few AVX512 sub-features
Like AVX512-FP16, several other extensions require wider than 16-bit
mask registers. As a result they take AVX512BW as a prereq, not (just)
AVX512F. Which in turn points out wrong expectations in the noavx512-1
testcase.
2022-12-22 09:34:50 +01:00
Jan Beulich
b20f426174 x86: add dependencies on AVX2
Like AVX-VNNI both VAES and VPCLMUL take AVX2 as a prereq, for operating
on up to 256-bit packed integer vectors.
2022-12-22 09:33:53 +01:00
Jan Beulich
88bd2203ef x86: correct SSE dependencies
SSE itself takes FXSR as a prereq. Like AES, PCLMUL, and SHA both GFNI
and KL take SSE2 as a prereq, for operating on packed integers. And
while correcting KL also record it as a prereq to WIDEKL.
2022-12-22 09:33:26 +01:00
Jan Beulich
4d97c5c833 x86: re-work ISA extension dependency handling
Getting both forward and reverse ISA dependencies right / consistent has
been a permanent source of mistakes. Reduce what needs specifying
manually to just the direct forward dependencies. Transitive forward
dependencies as well as reverse ones are now derived and hence cannot go
out of sync anymore (at least in the vast majority of cases; there are a
few special cases to still take care of manually). In the course of this
several CPU_ANY_*_FLAGS disappear, requiring adjustment to the
assembler's cpu_arch[].

Note that to retain the correct reverse dependency of AVX512F wrt
AVX512-VP2INTERSECT, the latter has the previously missing AVX512F
prereq added.

Note further that to avoid adding the following undue prereqs:
* ATHLON, K8, and AMDFAM10 gain CMOV and FXSR,
* IAMCU gains 387,
auxiliary table entries (including a colon-separated modifier) are
introduced in addition to the ones representing from converting the old
table.

To maintain forward-only dependencies between AVX (XOP) and SSE* (SSE4a)
(i.e. "nosse" not disabling AVX), reverse dependency tracking is
artifically suppressed.

As a side effect disabling of SSE or SSE2 will now also disable AES,
PCLMUL, and SHA (respective elements were missing from
CPU_ANY_SSE2_FLAGS).
2022-12-22 09:32:29 +01:00
Jan Beulich
9c19e9ec4d x86: rename CheckRegSize to CheckOperandSize
While originally indeed used for register size checking only, the
attribute has been used for memory operand size checking as well already
for quite a while, with more such uses recently having been added.
2022-12-21 09:07:03 +01:00
Jan Beulich
4fdeb2a379 x86: omit Cpu prefixes from opcode table
These enumerators can be used in only one specific field, and hence the
Cpu prefix isn't needed ther for disambiguation / name space separation.
2022-12-19 09:22:33 +01:00
Jan Beulich
689933867a x86: change representation of extension opcode
Having a "None" field in the vast majority of entries is needlessly
cluttering the overall table. Instead of this being a separate field,
use a representation matching that of Intel SDM and AMD PM for the main
use of the field: Append the value after a / as the separator.
2022-12-16 09:00:23 +01:00
Jan Beulich
65f440c8fb x86: generate template sets data at build time
Speed up gas startup by avoiding runtime allocation of the instances of
type "templates". At the same time cut the memory requirement to just
very little over half (not even accounting for any overhead
notes_alloc() may incur) by reusing the "end" slot of a preceding entry
for the "start" slot of the subsequent one.
2022-12-12 08:49:26 +01:00
Jan Beulich
daf15e3e96 x86: drop sentinel from i386_optab[]
Now that the table is local to gas, ARRAY_SIZE() can be used to
determine the end of the table. Re-arrange the processing loop in
md_begin() accordingly, at the same time folding the two calls to
notes_alloc() into just one.
2022-12-12 08:49:00 +01:00
Jan Beulich
99f0fb12d5 x86: instantiate i386_{op,reg}tab[] in gas instead of in libopcodes
Unlike many other architectures, x86 does not share an opcode table
between assembly and disassembly. Any consumer of libopcodes would only
ever access one of the two. Since gas is the only consumer of the
assembly data, move it there. While doing so mark respective entities
"static" in i386-gen (we may want to do away with i386_regtab_size
altogether).

This also shrinks the number of relocations to be processed for
libopcodes.so by about 30%.
2022-12-12 08:46:47 +01:00
Jan Beulich
05909f2341 x86: drop most OPERAND_TYPE_* (and rework the rest)
With the general use of C99 there's no need anymore to have i386-gen
produce these. For more frequently used ones introduce local #define-s,
while others are simply spelled out directly. While doing this move
some static constants into more narrow scopes.

Note that as a "side effect" this corrects type_names[]'es imm8s entry.
2022-12-02 09:54:09 +01:00
Jan Beulich
f207f1c113 x86: drop No_ldSuf
With LONG_DOUBLE_MNEM_SUFFIX gone there'salso no use for No_ldSuf
anymore.
2022-12-01 10:00:07 +01:00
Jan Beulich
ac9226cf8c x86: drop FloatR
There are just 4 templates using it, which can be easily identified by
other means, as D is set only on a very limited number of FPU templates.
Also move the respective conditional out of the code path taken by all
"reverse match" insns (it probably should have been this way already
before, to avoid the one conditional in the common case).

With this the templates which had FloatR dropped no longer differ from
their AT&T syntax + mnemonic counterparts - the only difference is now
which of the two would be recognized. For this, however, we don't need
two templates - we can simply arrange the condition for setting
Opcode_FloatR accordingly.
2022-11-30 09:06:33 +01:00
Tejas Joshi
b0e8fa7ff0 Add AMD znver4 processor support
2022-09-28  Tejas Joshi <TejasSanjay.Joshi@amd.com>

gas/

        * config/tc-i386.c (cpu_arch): Add znver4 ARCH and rmpquery SUBARCH.
        (md_assemble): Expand comment before swap_operands() with rmpquery.
        * doc/c-i386.texi: Add znver4.
        * testsuite/gas/i386/arch-14-1.d: New.
        * testsuite/gas/i386/arch-14-1.s: New.
        * testsuite/gas/i386/arch-14-znver4.d: New.
        * testsuite/gas/i386/i386.exp: Add new znver4 test cases.
        * testsuite/gas/i386/rmpquery.d: New.
        * testsuite/gas/i386/rmpquery.s: New.
        * testsuite/gas/i386/x86-64-arch-4-1.d: New.
        * testsuite/gas/i386/x86-64-arch-4-1.s: New.
        * testsuite/gas/i386/x86-64-arch-4-znver4.d: New.

opcodes/

        * i386-dis.c (x86_64_table): Add rmpquery.
        * i386-gen.c (cpu_flag_init): Add CPU_ZNVER4_FLAGS and
        CPU_RMPQUERY_FLAGS.
        (cpu_flags): Add CpuRMPQUERY.
        * i386-opc.h (enum): Add CpuRMPQUERY.
        (i386_cpu_flags): Add cpurmpquery.
        * i386-opc.tbl: Add rmpquery insn.
        * i386-init.h: Re-generated.
        * i386-tbl.h: Re-generated.
2022-11-15 10:07:02 -08:00
Jan Beulich
255571cdbf x86: fold special-operand insn attributes into a single enum
Attributes which aren't used together in any single insn template can be
converted from individual booleans to a single enum, as was done for a few
other attributes before. This is more space efficient. Collect together
all attributes which express special operand constraints (and which fit
the criteria for folding).
2022-11-14 17:10:14 +01:00
Kong Lingling
b06311adb4 Support Intel RAO-INT
gas/ChangeLog:

	* NEWS: Support Intel RAO-INT.
	* config/tc-i386.c: Add raoint.
	* doc/c-i386.texi: Document .raoint.
	* testsuite/gas/i386/i386.exp: Run RAO_INT tests.
	* testsuite/gas/i386/raoint-intel.d: New test.
	* testsuite/gas/i386/raoint.d: Ditto.
	* testsuite/gas/i386/raoint.s: Ditto.
	* testsuite/gas/i386/x86-64-raoint-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-raoint.d: Ditto.
	* testsuite/gas/i386/x86-64-raoint.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_0F38FC): New.
	(prefix_table): Add PREFIX_0F38FC.
	* i386-gen.c: (cpu_flag_init): Add CPU_RAO_INT_FLAGS and
	CPU_ANY_RAO_INT_FLAGS.
	* i386-init.h: Regenerated.
	* i386-opc.h: (CpuRAO_INT): New.
	(i386_cpu_flags): Add cpuraoint.
	* i386-opc.tbl: Add RAO_INT instructions.
	* i386-tbl.h: Regenerated.
2022-11-08 10:24:59 +08:00
konglin1
01d8ce742c Support Intel AVX-NE-CONVERT
gas/ChangeLog:

	* NEWS: Support Intel AVX-NE-CONVERT.
	* config/tc-i386.c: Add avx_ne_convert.
	* doc/c-i386.texi: Document .avx_ne_convert.
	* testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests.
	* testsuite/gas/i386/avx-ne-convert-intel.d: New test.
	* testsuite/gas/i386/avx-ne-convert.d: Ditto.
	* testsuite/gas/i386/avx-ne-convert.s: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (Mw): New.
	(PREFIX_VEX_0F3872): Ditto.
	(PREFIX_VEX_0F38B0_W_0): Ditto.
	(PREFIX_VEX_0F38B1_W_0): Ditto.
	(VEX_W_0F3872_P_1): Ditto.
	(VEX_W_0F38B0): Ditto.
	(VEX_W_0F38B1): Ditto.
	(prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0_W_0,
	PREFIX_VEX_0F38B1_W_0.
	(vex_w_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0, VEX_W_0F38B1.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and
	CPU_ANY_AVX_NE_CONVERT_FLAGS.
	(cpu_flags): Add CpuAVX_NE_CONVERT.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuAVX_NE CONVERT): New.
	(i386_cpu_flags): Add cpuavx_ne_convert.
	* i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions.
	* i386-tbl.h: Regenerated.
2022-11-04 11:42:17 +08:00
Hu, Lin1
2188d6ea4f Support Intel MSRLIST
gas/ChangeLog:

	* NEWS: Support Intel MSRLIST.
	* config/tc-i386.c: Add msrlist.
	* doc/c-i386.texi: Document .msrlist.
	* testsuite/gas/i386/i386.exp: Add MSRLIST tests.
	* testsuite/gas/i386/msrlist-inval.l: New test.
	* testsuite/gas/i386/msrlist-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-msrlist.d: Ditto.
	* testsuite/gas/i386/x86-64-msrlist.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New.
	(X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto.
	(prefix_table): New entry for msrlist.
	(x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1
	and X86_64_0F01_REG_0_MOD_3_RM_6_P_3.
	* i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS
	and CPU_ANY_MSRLIST_FLAGS.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuMSRLIST): New.
	(i386_cpu_flags): Add cpumsrlist.
	* i386-opc.tbl: Add MSRLIST instructions.
	* i386-tbl.h: Regenerated.
2022-11-02 09:19:26 +08:00
Hu, Lin1
941f083324 Support Intel WRMSRNS
gas/ChangeLog:

        * NEWS: Support Intel WRMSRNS.
        * config/tc-i386.c: Add wrmsrns.
        * doc/c-i386.texi: Document .wrmsrns.
        * testsuite/gas/i386/i386.exp: Add WRMSRNS tests.
        * testsuite/gas/i386/wrmsrns-intel.d: New test.
        * testsuite/gas/i386/wrmsrns.d: Ditto.
        * testsuite/gas/i386/wrmsrns.s: Ditto.
        * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New.
	(prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6.
	(rm_table): New entry for wrmsrns.
	* i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS
	and CPU_ANY_WRMSRNS_FLAGS.
	(cpu_flags): Add CpuWRMSRNS.
        * i386-init.h: Regenerated.
        * i386-opc.h (CpuWRMSRNS): New.
	(i386_cpu_flags): Add cpuwrmsrns.
        * i386-opc.tbl: Add WRMSRNS instructions.
        * i386-tbl.h: Regenerated.
2022-11-02 09:19:24 +08:00
Haochen Jiang
a93e323427 Support Intel CMPccXADD
gas/ChangeLog:

	* NEWS: Support Intel CMPccXADD.
	* config/tc-i386.c: Add cmpccxadd.
	(build_modrm_byte): Add operations for Vex.VVVV reg
	on operand 0 while have memory operand.
	* doc/c-i386.texi: Document .cmpccxadd.
	* testsuite/gas/i386/i386.exp: Run CMPccXADD tests.
	* testsuite/gas/i386/cmpccxadd-inval.s: New test.
	* testsuite/gas/i386/cmpccxadd-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto.
	* testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (Mdq): New.
	(X86_64_VEX_0F38E0): Ditto.
	(X86_64_VEX_0F38E1): Ditto.
	(X86_64_VEX_0F38E2): Ditto.
	(X86_64_VEX_0F38E3): Ditto.
	(X86_64_VEX_0F38E4): Ditto.
	(X86_64_VEX_0F38E5): Ditto.
	(X86_64_VEX_0F38E6): Ditto.
	(X86_64_VEX_0F38E7): Ditto.
	(X86_64_VEX_0F38E8): Ditto.
	(X86_64_VEX_0F38E9): Ditto.
	(X86_64_VEX_0F38EA): Ditto.
	(X86_64_VEX_0F38EB): Ditto.
	(X86_64_VEX_0F38EC): Ditto.
	(X86_64_VEX_0F38ED): Ditto.
	(X86_64_VEX_0F38EE): Ditto.
	(X86_64_VEX_0F38EF): Ditto.
	(x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1,
	X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4,
	X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7,
	X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA,
	X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED,
	X86_64_VEX_0F38EE, X86_64_VEX_0F38EF.
	* i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and
	CPU_ANY_CMPCCXADD_FLAGS.
	(cpu_flags): Add CpuCMPCCXADD.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuCMPCCXADD): New.
	(i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0.
	* i386-opc.tbl: Add Intel CMPccXADD instructions.
	* i386-tbl.h: Regenerated.
2022-11-02 09:19:22 +08:00
Cui,Lili
23ae61ad89 Support Intel AVX-VNNI-INT8
gas/
        * NEWS: Support Intel AVX-VNNI-INT8.
	* config/tc-i386.c: Add avx_vnni_int8.
	* doc/c-i386.texi: Document avx_vnni_int8.
	* testsuite/gas/i386/avx-vnni-int8-intel.d: New file.
	* testsuite/gas/i386/avx-vnni-int8.d: Likewise.
	* testsuite/gas/i386/avx-vnni-int8.s: Likewise.
	* testsuite/gas/i386/x86-64-avx-vnni-int8-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-vnni-int8.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-vnni-int8.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run AVX VNNI INT8 tests.

opcodes/
	* i386-dis.c: (PREFIX_VEX_0F3850) New.
	(PREFIX_VEX_0F3851): Likewise.
	(VEX_W_0F3850_P_0): Likewise.
	(VEX_W_0F3850_P_1): Likewise.
	(VEX_W_0F3850_P_2): Likewise.
	(VEX_W_0F3850_P_3): Likewise.
	(VEX_W_0F3851_P_0): Likewise.
	(VEX_W_0F3851_P_1): Likewise.
	(VEX_W_0F3851_P_2): Likewise.
	(VEX_W_0F3851_P_3): Likewise.
	(VEX_W_0F3850): Delete.
	(VEX_W_0F3851): Likewise.
	(prefix_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851.
	(vex_table): Add PREFIX_VEX_0F3850 and PREFIX_VEX_0F3851,
	delete VEX_W_0F3850 and VEX_W_0F3851.
	(vex_w_table): Add VEX_W_0F3850_P_0, VEX_W_0F3850_P_1, VEX_W_0F3850_P_2
	VEX_W_0F3850_P_3, VEX_W_0F3851_P_0, VEX_W_0F3851_P_1, VEX_W_0F3851_P_2
	and VEX_W_0F3851_P_3, delete VEX_W_0F3850 and VEX_W_0F3851.
	* i386-gen.c: (cpu_flag_init): Add CPU_AVX_VNNI_INT8_FLAGS
	and CPU_ANY_AVX_VNNI_INT8_FLAGS.
	(cpu_flags): Add CpuAVX_VNNI_INT8.
	* i386-opc.h (CpuAVX_VNNI_INT8): New.
	* i386-opc.tbl: Add Intel AVX_VNNI_INT8 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2022-11-02 09:19:20 +08:00
Hongyu Wang
4321af3e4d Support Intel AVX-IFMA
x86: Support Intel AVX-IFMA

Intel AVX IFMA instructions are marked with CpuVEX_PREFIX, which is
cleared by default.  Without {vex} pseudo prefix, Intel IFMA instructions
are encoded with EVEX prefix.  {vex} pseudo prefix will turn on VEX
encoding for Intel IFMA instructions.

gas/

	* NEWS: Support Intel AVX-IFMA.
	* config/tc-i386.c (cpu_arch): Add avx_ifma.
	* doc/c-i386.texi: Document .avx_ifma.
	* testsuite/gas/i386/avx-ifma.d: New file.
	* testsuite/gas/i386/avx-ifma-intel.d: Likewise.
	* testsuite/gas/i386/avx-ifma.s: Likewise.
	* testsuite/gas/i386/x86-64-avx-ifma.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-ifma-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx-ifma.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run AVX IFMA tests.

opcodes/

	* i386-dis.c (PREFIX_VEX_0F38B4): New.
	(PREFIX_VEX_0F38B5): Likewise.
	(VEX_W_0F38B4_P_2): Likewise.
	(VEX_W_0F38B5_P_2): Likewise.
	(prefix_table): Add PREFIX_VEX_0F38B4 and PREFIX_VEX_0F38B5.
	(vex_table): Add VEX_W_0F38B4_P_2 and VEX_W_0F38B5_P_2.
	* i386-dis-evex.h: Fold AVX512IFMA entries to AVX-IFMA.
	* i386-gen.c (cpu_flag_init): Clear the CpuAVX_IFMA bit in
	CPU_UNKNOWN_FLAGS. Add CPU_AVX_IFMA_FLGAS and
	CPU_ANY_AVX_IFMA_FLAGS. Add CpuAVX_IFMA to CPU_AVX2_FLAGS.
	(cpu_flags): Add CpuAVX_IFMA.
	* i386-opc.h (CpuAVX_IFMA): New.
	(i386_cpu_flags): Add cpuavx_ifma.
	* i386-opc.tbl: Add Intel AVX IFMA instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2022-11-02 09:19:20 +08:00
Jan Beulich
8f0212acb1 x86: minor improvements to optimize_imm() (part III)
Earlier tidying still missed an opportunity: There's no need for the
"anyimm" static variable. Instead of using it in the loop to mask
"allowed" (which is necessary to satisfy operand_type_or()'s assertions)
simply use "mask", requiring it to be calculated first. That way the
post-loop masking by "mask" ahead of the operand_type_all_zero() can be
dropped.
2022-10-31 17:56:06 +01:00
Cui, Lili
ef07be453e Support Intel PREFETCHI
gas/ChangeLog:

	* NEWS: Add support for Intel PREFETCHI instruction.
	* config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches.
	(md_assemble): Add warning for illegal input of PREFETCHI.
	* doc/c-i386.texi: Document .prefetchi.
	* testsuite/gas/i386/i386.exp: Run PREFETCHI tests.
	* testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI.
	* testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetch.d: New test.
	* testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise..
	* testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi.d: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi.s: Likewise.

opcodes/ChangeLog:

	* i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7
	(x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0.
	(mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7.
	(prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and
	PREFIX_0F18_REG_7_MOD_0_X86_64.
	(PREFETCHI_Fixup): New.
	* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS.
	(cpu_flags): Add CpuPREFETCHI.
	* i386-opc.h (CpuPREFETCHI): New.
	(i386_cpu_flags): Add cpuprefetchi.
	* i386-opc.tbl: Add Intel PREFETCHI instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2022-10-31 21:15:29 +08:00