On OBS I ran into:
...
(gdb) shell diff -s outputs/gdb.base/signals-state-child/standalone.txt \
outputs/gdb.base/signals-state-child/gdb.txt^M
diff: outputs/gdb.base/signals-state-child/standalone.txt: \
No such file or directory^M
(gdb) FAIL: gdb.base/signals-state-child.exp: signals states are identical
...
I managed to reproduce this by adding "sleep (5)" at the start of main in
signals-state-child.c.
Fix this by waiting on the result of the spawned command.
Tested on x86_64-linux.
Put bpf back in the 32-bit targets, even though bpf requires a 64-bit
bfd. bpf sim support apparently works without being 64-bit.
* Makefile.am (TARGET64_LIBOPCODES_CFILES): Move bpf files..
(TARGET32_LIBOPCODES_CFILES): ..to here.
* Makefile.in: Regenerate.
Pick up the elfutils/debuginfod.h install location -I flags from
a variable set by debuginfod.m4 (via pkg.m4 and pkg-config).
* Makefile.am (DEBUGINFOD_CFLAGS): Define.
(dwarf.@OBJECT@): New rule.
Use gpr when the zfinx enable, the testcases contain float
instructions that reuse by z[fdq]inx.
gas/ChangeLog:
* testsuite/gas/riscv/zdinx.d: New test.
* testsuite/gas/riscv/zdinx.s: New test.
* testsuite/gas/riscv/zfinx.d: New test.
* testsuite/gas/riscv/zfinx.s: New test.
* testsuite/gas/riscv/zqinx.d: New test.
* testsuite/gas/riscv/zqinx.s: New test.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to
verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
z*inx extension.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Added register choice for z*inx.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Added disassemble check for
z*inx.
* riscv-opc.c: Reused INSN_CLASS_* for z*inx.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Minimal support for zfinx, zdinx, zqinx. Like f/d/q, the zqinx
imply zdinx and zdinx imply zfinx, where zfinx are not compatible
with f/d/q.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Added implicit rules
for z*inx extensions.
(riscv_supported_std_z_ext): Added entries for z*inx.
(riscv_parse_check_conflicts): Added conflict check for z*inx.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
This patch is adding new SVE2 instructions added to support SME extension.
The following SVE2 instructions are added by the SME architecture:
* PSEL,
* REVD, SCLAMP and UCLAMP.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_pred_reg_with_index):
New parser.
(parse_operands): New parser.
* testsuite/gas/aarch64/sme-9-illegal.d: New test.
* testsuite/gas/aarch64/sme-9-illegal.l: New test.
* testsuite/gas/aarch64/sme-9-illegal.s: New test.
* testsuite/gas/aarch64/sme-9.d: New test.
* testsuite/gas/aarch64/sme-9.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_SME_PnT_Wm_imm.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index):
New inserter.
* aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index):
New extractor.
* aarch64-opc.c (aarch64_print_operand): Printout of
OPND_SME_PnT_Wm_imm.
* aarch64-opc.h (enum aarch64_field_kind): New bitfields
FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl.
* aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier.
(OP_SVE_QMQ): New qualifier.
(struct aarch64_opcode): New instructions PSEL, REVD,
SCLAMP and UCLAMP.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
This patch is adding miscellaneous SME related system registers.
gas/ChangeLog:
* testsuite/gas/aarch64/sme-sysreg.d: New test.
* testsuite/gas/aarch64/sme-sysreg.s: New test.
* testsuite/gas/aarch64/sme-sysreg-illegal.d: New test.
* testsuite/gas/aarch64/sme-sysreg-illegal.l: New test.
* testsuite/gas/aarch64/sme-sysreg-illegal.s: New test.
opcodes/ChangeLog:
* aarch64-opc.c: New system registers id_aa64smfr0_el1,
smcr_el1, smcr_el12, smcr_el2, smcr_el3, smpri_el1,
smprimap_el2, smidr_el1, tpidr2_el0 and mpamsm_el1.
This patch is adding new SME mode selection and state access instructions:
* Add SMSTART and SMSTOP instructions.
* Add SVCR system register.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_sm_za): New parser.
(parse_operands): New parser.
* testsuite/gas/aarch64/sme-8-illegal.d: New test.
* testsuite/gas/aarch64/sme-8-illegal.l: New test.
* testsuite/gas/aarch64/sme-8-illegal.s: New test.
* testsuite/gas/aarch64/sme-8.d: New test.
* testsuite/gas/aarch64/sme-8.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_SME_SM_ZA.
(enum aarch64_insn_class): New instruction classes
sme_start and sme_stop.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_pstatefield): New inserter.
(aarch64_ins_sme_sm_za): New inserter.
* aarch64-dis.c (aarch64_ext_imm): New extractor.
(aarch64_ext_pstatefield): New extractor.
(aarch64_ext_sme_sm_za): New extractor.
* aarch64-opc.c (operand_general_constraint_met_p):
New pstatefield value for SME instructions.
(aarch64_print_operand): Printout for OPND_SME_SM_ZA.
(SR_SME): New register SVCR.
* aarch64-opc.h (F_REG_IN_CRM): New register endcoding.
* aarch64-opc.h (F_IMM_IN_CRM): New immediate endcoding.
(PSTATE_ENCODE_CRM): Encode CRm field.
(PSTATE_DECODE_CRM): Decode CRm field.
(PSTATE_ENCODE_CRM_IMM): Encode CRm immediate field.
(PSTATE_DECODE_CRM_IMM): Decode CRm immediate field.
(PSTATE_ENCODE_CRM_AND_IMM): Encode CRm and immediate
field.
* aarch64-tbl.h (struct aarch64_opcode): New SMSTART
and SMSTOP instructions.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
This patch is adding new loads and stores defined by SME instructions.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_address): New parser.
(parse_sme_za_hv_tiles_operand_with_braces): New parser.
(parse_sme_za_array): New parser.
(output_operand_error_record): Print error details if
present.
(parse_operands): Support new operands.
* testsuite/gas/aarch64/sme-5-illegal.d: New test.
* testsuite/gas/aarch64/sme-5-illegal.l: New test.
* testsuite/gas/aarch64/sme-5-illegal.s: New test.
* testsuite/gas/aarch64/sme-5.d: New test.
* testsuite/gas/aarch64/sme-5.s: New test.
* testsuite/gas/aarch64/sme-6-illegal.d: New test.
* testsuite/gas/aarch64/sme-6-illegal.l: New test.
* testsuite/gas/aarch64/sme-6-illegal.s: New test.
* testsuite/gas/aarch64/sme-6.d: New test.
* testsuite/gas/aarch64/sme-6.s: New test.
* testsuite/gas/aarch64/sme-7-illegal.d: New test.
* testsuite/gas/aarch64/sme-7-illegal.l: New test.
* testsuite/gas/aarch64/sme-7-illegal.s: New test.
* testsuite/gas/aarch64/sme-7.d: New test.
* testsuite/gas/aarch64/sme-7.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operands.
(enum aarch64_insn_class): Added sme_ldr and sme_str.
(AARCH64_OPDE_UNTIED_IMMS): New operand error kind.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_za_hv_tiles): New inserter.
(aarch64_ins_sme_za_list): New inserter.
(aarch64_ins_sme_za_array): New inserter.
(aarch64_ins_sme_addr_ri_u4xvl): New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): Added
ins_sme_za_list, ins_sme_za_array and ins_sme_addr_ri_u4xvl.
* aarch64-dis.c (aarch64_ext_sme_za_hv_tiles): New extractor.
(aarch64_ext_sme_za_list): New extractor.
(aarch64_ext_sme_za_array): New extractor.
(aarch64_ext_sme_addr_ri_u4xvl): New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): Added
ext_sme_za_list, ext_sme_za_array and ext_sme_addr_ri_u4xvl.
* aarch64-opc.c (operand_general_constraint_met_p):
(aarch64_match_operands_constraint): Handle sme_ldr, sme_str
and sme_misc.
(aarch64_print_operand): New operands supported.
* aarch64-tbl.h (OP_SVE_QUU): New qualifier.
(OP_SVE_QZU): New qualifier.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
This patch is adding ZERO (a list of 64-bit element ZA tiles)
instruction.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_list_of_64bit_tiles):
New parser.
(parse_operands): Handle OPND_SME_list_of_64bit_tiles.
* testsuite/gas/aarch64/sme-4-illegal.d: New test.
* testsuite/gas/aarch64/sme-4-illegal.l: New test.
* testsuite/gas/aarch64/sme-4-illegal.s: New test.
* testsuite/gas/aarch64/sme-4.d: New test.
* testsuite/gas/aarch64/sme-4.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_SME_list_of_64bit_tiles.
opcodes/ChangeLog:
* aarch64-opc.c (print_sme_za_list): New printing function.
(aarch64_print_operand): Handle OPND_SME_list_of_64bit_tiles.
* aarch64-opc.h (enum aarch64_field_kind): New bitfield
FLD_SME_zero_mask.
* aarch64-tbl.h (struct aarch64_opcode): New ZERO instruction.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
This patch is adding new MOV (alias) and MOVA SME instruction.
gas/ChangeLog:
* config/tc-aarch64.c (enum sme_hv_slice): new enum.
(struct reloc_entry): Added ZAH and ZAV registers.
(parse_sme_immediate): Immediate parser.
(parse_sme_za_hv_tiles_operand): ZA tile parser.
(parse_sme_za_hv_tiles_operand_index): Index parser.
(parse_operands): Added ZA tile parser calls.
(REGNUMS): New macro. Regs with suffix.
(REGSET16S): New macro. 16 regs with suffix.
* testsuite/gas/aarch64/sme-2-illegal.d: New test.
* testsuite/gas/aarch64/sme-2-illegal.l: New test.
* testsuite/gas/aarch64/sme-2-illegal.s: New test.
* testsuite/gas/aarch64/sme-2.d: New test.
* testsuite/gas/aarch64/sme-2.s: New test.
* testsuite/gas/aarch64/sme-2a.d: New test.
* testsuite/gas/aarch64/sme-2a.s: New test.
* testsuite/gas/aarch64/sme-3-illegal.d: New test.
* testsuite/gas/aarch64/sme-3-illegal.l: New test.
* testsuite/gas/aarch64/sme-3-illegal.s: New test.
* testsuite/gas/aarch64/sme-3.d: New test.
* testsuite/gas/aarch64/sme-3.s: New test.
* testsuite/gas/aarch64/sme-3a.d: New test.
* testsuite/gas/aarch64/sme-3a.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New enums
AARCH64_OPND_SME_ZA_HV_idx_src and
AARCH64_OPND_SME_ZA_HV_idx_dest.
(struct aarch64_opnd_info): New ZA tile vector struct.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_za_hv_tiles):
New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER):
New inserter ins_sme_za_hv_tiles.
* aarch64-dis.c (aarch64_ext_sme_za_hv_tiles):
New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR):
New extractor ext_sme_za_hv_tiles.
* aarch64-opc.c (aarch64_print_operand):
Handle SME_ZA_HV_idx_src and SME_ZA_HV_idx_dest.
* aarch64-opc.h (enum aarch64_field_kind): New enums
FLD_SME_size_10, FLD_SME_Q, FLD_SME_V and FLD_SME_Rv.
(struct aarch64_operand): Increase fields size to 5.
* aarch64-tbl.h (OP_SME_BHSDQ_PM_BHSDQ): New qualifiers
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Patch is adding new SME matrix instructions. Please note additional
instructions will be added in following patches.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_zada_operand):
New parser.
* config/tc-aarch64.c (parse_reg_with_qual):
New reg parser.
* config/tc-aarch64.c (R_ZA): New egister type.
(parse_operands): New parser.
* testsuite/gas/aarch64/sme-illegal.d: New test.
* testsuite/gas/aarch64/sme-illegal.l: New test.
* testsuite/gas/aarch64/sme-illegal.s: New test.
* testsuite/gas/aarch64/sme.d: New test.
* testsuite/gas/aarch64/sme.s: New test.
* testsuite/gas/aarch64/sme-f64.d: New test.
* testsuite/gas/aarch64/sme-f64.s: New test.
* testsuite/gas/aarch64/sme-i64.d: New test.
* testsuite/gas/aarch64/sme-i64.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operands
AARCH64_OPND_SME_ZAda_2b, AARCH64_OPND_SME_ZAda_3b and
AARCH64_OPND_SME_Pm.
(enum aarch64_insn_class): New instruction class sme_misc.
opcodes/ChangeLog:
* aarch64-opc.c (aarch64_print_operand):
Print OPND_SME_ZAda_2b and OPND_SME_ZAda_3b operands.
(verify_constraints): Handle OPND_SME_Pm.
* aarch64-opc.h (enum aarch64_field_kind):
New bit fields FLD_SME_ZAda_2b, FLD_SME_ZAda_3b and FLD_SME_Pm.
* aarch64-tbl.h (OP_SME_ZADA_PN_PM_ZN_S): New qualifier set.
(OP_SME_ZADA_PN_PM_ZN_D): New qualifier.
(OP_SME_ZADA_PN_PM_ZN_ZM): New qualifier.
(OP_SME_ZADA_S_PM_PM_S_S): New qualifier.
(OP_SME_ZADA_D_PM_PM_D_D): New qualifier.
(OP_SME_ZADA_S_PM_PM_H_H): New qualifier.
(OP_SME_ZADA_S_PM_PM_B_B): New qualifier.
(OP_SME_ZADA_D_PM_PM_H_H): New qualifier.
(SME_INSN): New instruction macro.
(SME_F64_INSN): New instruction macro.
(SME_I64_INSN): New instruction macro.
(SME_INSNC): New instruction macro.
(struct aarch64_opcode): New SME instructions.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
This series of patches (tagged [SME]) add support for the Scalable
Matrix Extension. Patch introduces new command line options: +sme, +sme-f64 and
+sme-i64 to -march command line options.
gas/ChangeLog:
* NEWS: Updated docs.
* config/tc-aarch64.c: New SME command line options.
* doc/c-aarch64.texi: Update docs.
include/ChangeLog:
* opcode/aarch64.h (AARCH64_FEATURE_SME): New flag.
(AARCH64_FEATURE_SME_F64): New flag.
(AARCH64_FEATURE_SME_I64): New flag.
opcodes/ChangeLog:
* aarch64-tbl.h (SME): New feature object.
PR 28452
bfd * elf.c (assign_file_positions_for_non_load_sections): Replace
assertion with a warning message.
ld * ldgram.y: Add support for PT_GNU_RELRO and PT_GNU_PROPERTY.
* ldgram.c: Regenerate.
Commit 345bd07cce ("gdb: fix gdbarch_tdep ODR violation") changes a
declaration in s390-tdep.h from
struct gdbarch_tdep { ... };
to
struct s390_gdbarch_tdep : gdbarch_tdep { ... };
and now requires that gdbarch_tdep has been declared before. Which is
usually the case, except when compiling s390-linux-nat.c, where
s390-tdep.h is included before gdbarch.h. Thus the s390x build errors out
with the compiler complaining about a missing class name after the colon.
Fix this in s390-linux-nat.c, by including gdbarch.h before s390-tdep.h.
Augment the register description XML to expose the BTI BTYPE field contained
in the CPSR register. It will be displayed like so:
cpsr 0x60001000 [ EL=0 BTYPE=0 SSBS C Z ]
2021-11-17 Jim Wilson <jimw@sifive.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
This patch is porting from the following riscv github,
https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x
And here is the vector spec,
https://github.com/riscv/riscv-v-spec
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules
of v, zve and zvl extensions.
(riscv_supported_std_ext): Updated verison of v to 1.0.
(riscv_supported_std_z_ext): Added zve and zvl extensions.
(riscv_parse_check_conflicts): The zvl extensions need to
enable either v or zve extension.
(riscv_multi_subset_supports): Check the subset list to know
if the INSN_CLASS_V and INSN_CLASS_ZVEF instructions are supported.
gas/
* config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_V.
(enum reg_class): Added RCLASS_VECR and RCLASS_VECM.
(validate_riscv_insn): Check whether the rvv operands are valid.
(md_begin): Initialize register hash for rvv registers.
(macro_build): Added rvv operands when expanding rvv pseudoes.
(vector_macro): Expand rvv macros into one or more instructions.
(macro): Likewise.
(my_getVsetvliExpression): Similar to my_getVsetvliExpression,
but used for parsing vsetvli operands.
(riscv_ip): Parse and encode rvv operands. Besides, The rvv loads
and stores with EEW 64 cannot be used when zve32x is enabled.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated -march
to rv32ifv_zkr.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg.s: Added rvv csr testcases.
* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/march-imply-v.d: New testcase.
* testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Likewise.
* testsuite/gas/riscv/vector-insns-fail-zve32xf.l: Likewise.
* testsuite/gas/riscv/vector-insns-fail-zvl.d: Likewise.
* testsuite/gas/riscv/vector-insns-fail-zvl.l: Likewise.
* testsuite/gas/riscv/vector-insns-vmsgtvx.d: Likewise.
* testsuite/gas/riscv/vector-insns-vmsgtvx.s: Likewise.
* testsuite/gas/riscv/vector-insns-zero-imm.d: Likewise.
* testsuite/gas/riscv/vector-insns-zero-imm.s: Likewise.
* testsuite/gas/riscv/vector-insns.d: Likewise.
* testsuite/gas/riscv/vector-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Defined mask/match encodings and csrs for rvv.
* opcode/riscv.h: Defined rvv immediate encodings and fields.
(enum riscv_insn_class): Added INSN_CLASS_V and INSN_CLASS_ZVEF.
(INSN_V_EEW64): Defined.
(M_VMSGE, M_VMSGEU): Added for the rvv pseudoes.
opcodes/
* riscv-dis.c (print_insn_args): Dump the rvv operands.
* riscv-opc.c (riscv_vecr_names_numeric): Defined rvv registers.
(riscv_vecm_names_numeric): Likewise.
(riscv_vsew): Likewise.
(riscv_vlmul): Likewise.
(riscv_vta): Likewise.
(riscv_vma): Likewise.
(match_vs1_eq_vs2): Added for rvv Vu operand.
(match_vd_eq_vs1_eq_vs2): Added for rvv Vv operand.
(riscv_opcodes): Added rvv v1.0 instructions.
On gcc-12 build fails as:
../../gdbserver/../gdb/nat/linux-osdata.c: In function 'void linux_xfer_osdata_processes(buffer*)':
../../gdbserver/../gdb/nat/linux-osdata.c:330:39: error:
'__builtin___sprintf_chk' may write a terminating nul past the end of the destination [-Werror=format-overflow=]
330 | sprintf (core_str, "%d", i);
| ^
It's an off-by-one case in an infeasible scenario for negative
huge core count. The change switches to std::string for memory
handling.
Tested by running 'info os processes' and checking CPU cores column.
Add aliases read_core_file_mappings_loop_ftype and
read_core_file_mappings_pre_loop_ftype. Intended for use with
read_core_file_mappings.
Also add build_id parameter to read_core_file_mappings_loop_ftype.
The common framework supports $srcdir & $subdir replacements already,
so replace the custom @srcdir@ logic with those. Since the replace
happens in slurp_options that cris already uses, we don't have any
logic to port over there. We have to duplicate that into the cris
slurp_rv helper though.
This tag is used to force tests to be built dynamically (i.e. without
-static linking). This is because cris-sim.exp in dejagnu turns on
static linking in ldflags.
The default configs and runtest flags shouldn't load these boards.
If these settings are still needed, we should figure out a different
way of suppressing the stock settings wholesale. We want these to
all pass out of the box with little to no configuration so that they
can run in a multitarget build.
With dropping "dynamic", it'll be easier to merge the custom cris
test logic with the common sim test logic.
On gcc-12 build fails as:
sim/cr16/interp.c: In function 'lookup_hash':
sim/cr16/interp.c:89:25: error:
the comparison will always evaluate as 'true'
for the address of 'mnimonic' will never be NULL [-Werror=address]
89 | if ((h->ops->mnimonic != NULL) &&
| ^~
'mnimonic' is a sharr array within ops. It can never be NULL.
While at it renamed 'mnimonic' to 'mnemonic'.
In commit 50888e42dc ("gdb: change functions returning value contents
to use gdb::array_view"), I believe I made a mistake with the length of
the array views returned by some functions. All functions return a view
of `TYPE_LENGTH (value_type (type))` length. This is not correct when
the value's enclosing type is larger than the value's type. In that
case, the value's contents buffer is of the size of the enclosing type,
and the value's actual contents is a slice of that (as returned by
value_contents). So, functions value_contents_all_raw,
value_contents_for_printing and value_contents_for_printing_const are
not correct. Since they are meant to return the value's contents buffer
as a whole, they should have the size of the enclosing type.
There is nothing that uses the returned array view size at the moment,
so this didn't cause a problem. But it became apparent when trying to
adjust some callers.
Change-Id: Ib4e8837e1069111d2b2784d3253d5f3002419e68
__func__ is standard C++11:
https://en.cppreference.com/w/cpp/language/function
Also, in C++11, __func__ expands to the demangled function name, so the
mention in the comment above FUNCTION_NAME doesn't apply anymore.
Finally, in places where FUNCTION_NAME is used, I think it's enough to
print the function name, no need to print the whole signature.
Therefore, I propose to just remove FUNCTION_NAME and update users to
use the standard __func__.
Change-Id: I778f28155422b044402442dc18d42d0cded1017d
The motivation is to reduce the number of places where unmanaged
pointers are returned from allocation type routines. All of the
callers are updated.
There should be no user visible changes after this commit.
In the next commit I'd like to reference gdb_unique_ptr within the
common-utils.h file. However, this requires that I include
gdb_unique_ptr.h, which requires that xfree be defined.
Interestingly, gdb_unique_ptr.h doesn't actually include anything that
defines xfree, but I was finding that when I added a gdb_unique_ptr.h
include to common-utils.h I was getting a dependency cycle; before my
change xfree was defined when gdb_unique_ptr.h was processed, while
after my change it was not, and this made g++ unhappy.
To break this cycle, I propose to move xfree into its own header file,
gdb-xfree.h, which I'll then include into gdb_unique_ptr.h and
common-utils.cc.
While reviewing this patch:
https://sourceware.org/pipermail/gdb-patches/2021-November/183227.html
I spotted that the patch could be improved if we threw
OPTIMIZED_OUT_ERROR rather than GENERIC_ERROR in a few places.
This commit updates error_value_optimized_out and
require_not_optimized_out to throw OPTIMIZED_OUT_ERROR.
I ran the testsuite and saw no regressions. This doesn't really
surprise me, we don't usually write code like:
catch (const gdb_exception_error &ex)
{
(if ex.error == GENERIC_ERROR)
...
else
...
}
There are a three places where we write something like:
catch (const gdb_exception_error &ex)
{
(if ex.error == OPTIMIZED_OUT_ERROR)
...
}
In frame.c:unwind_pc, stack.c:info_frame_command_core, and
value.c:value_optimized_out, but if we are hitting these cases then
it's not significantly changing GDB's behaviour.
PR gdb/28586 points out that "make distclean" fails to delete
config.cache from gdbserver/. This patch fixes the bug, and removes a
duplicate "Makefile" deletion that was also pointed out in the PR.
Test-case gdb.base/foll-vfork.exp has inferior output that is not needed, but
which makes the regexp matching more difficult (see commit 1f28b70def
"[gdb/testsuite] Fix regexp in gdb.base/foll-vfork.exp").
Remove the inferior output, and revert commit 1f28b70def to make the matching
more restrictive.
Tested on x86_64-linux.
Support the same syntax as other common utilities where env vars can
be specified before the program to be run without an explicit option.
This behavior can be suppressed by using the -- marker.
Provide explicit control over the program's environment with the
basic set/unset/clear options. These are a bit clunky to use,
but they're functional.
The env set operation is split out into a separate function as it'll
be used in the next commit.
With these in place, we can adjust the custom cris testsuite to use
the now standard options and not its one-off hack.
Now that we have access to the argv & envp strings, finish implementing
these syscalls. Delete unused variables, fix tbuf by incrementing the
pointer instead of setting to the length, and make sure we don't write
more data than the bufsize says is available.
We've been passing the environment strings to sim_create_inferior,
but most ports don't do anything with them. A few will use ad-hoc
logic to stuff the stack for user-mode programs, but that's it.
Let's formalize this across the board by storing the strings in the
normal sim state. This will allow (in future commits) supporting
more functionality in the run interface, and to unify some of the
libgloss syscalls.
Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from
zbb,zbc, we just change the class attribute to make them both support.
The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd
and Zkne extensions on rv64. Add new operand letter 'y' to present 'bs'
symbol and 'Y' to present 'rnum' symbolc for zkn instructions. Also add
a new Entropy Source CSR define 'seed' located at address 0x015.
bfd/
* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
crypto extension.
gas/
*config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_ZKR.
(riscv_csr_address): Checked for CSR_CLASS_ZKR.
(validate_riscv_insn): Added y and Y for bs and rnum operands.
(riscv_ip): Handle y and Y operands.
include/
* opcode/riscv-opc.h: Added encodings of crypto instructions.
Also defined new csr seed, which address is 0x15.
* opcode/riscv.h: Defined OP_* and INSN_CLASS_* for crypto.
opcodes/
* riscv-dis.c (print_insn_args): Recognized new y and Y operands.
* riscv-opc.c (riscv_opcodes): Added crypto instructions.
Minimal support of scalar crypto extension, add "k" in the
riscv_supported_std_ext, to make the order check right with
"zk" behind "zb".
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added implicit
rules for zk* extensions.
(riscv_supported_std_ext): Added entry for k.
(riscv_supported_std_z_ext): Added entries for zk*.
As discussed here [1], do some re-work in the "set debuginfod commands".
First, use "set debuginfod enabled on/off/ask" instead of "set
debuginfod on/off/ask". This is more MI-friendly, and it gives an
output that makes more sense in "info set", for example.
Then, make the show commands not call "error" when debuginfod support is
not compiled in. This makes the commands "show" and "show debuginfod"
stop early, breaking gdb.base/default.exp:
Running /home/smarchi/src/binutils-gdb/gdb/testsuite/gdb.base/default.exp ...
FAIL: gdb.base/default.exp: info set
FAIL: gdb.base/default.exp: show
- Make the "debuginfod enabled" setting default to "off" when debuginfod
support is not compiled in, and "ask" otherwise.
- Make the setter of "debuginfod enabled" error out when debuginfod
support is not compiled in, so that "debuginfod enabled" will always
remain "off" in that case.
- Make the setter of "debuginfod verbose" work in any case. I don't
see the harm in letting the user change that setting, since the user will
hit an error if they try to enable the use of debuginfod.
- I would do the same for the "debuginfod urls" setter, but because
this one needs to see the DEBUGINFOD_URLS_ENV_VAR macro, provided by
libdebuginfod, I made that one error out as well if debuginfod
support is not compiled it (otherwise, I would have left it like
"debuginfod verbose". Alternatively, we could hard-code
"DEBUGINFOD_URLS" in the code (in fact, it was prior to this patch,
but I think it was an oversight, as other spots use
DEBUGINFOD_URLS_ENV_VAR), or use a dummy string to store the setting,
but I don't really see the value in that.
Rename debuginfod_enable to debuginfod_enabled, just so it matches the
setting name.
[1] https://sourceware.org/pipermail/gdb-patches/2021-October/182937.html
Change-Id: I45fdb2993f668226a5639228951362b7800f09d5
Co-Authored-By: Aaron Merey <amerey@redhat.com>
Commit 345bd07cce ("gdb: fix gdbarch_tdep ODR violation") forgot to
update the gdbarch_tdep calls in the native files other than x86-64
Linux. This patch updates them all (to the best of my knowledge).
These are the files I was able to build-test:
aarch64-linux-nat.c
amd64-bsd-nat.c
arm-linux-nat.c
ppc-linux-nat.c
windows-nat.c
xtensa-linux-nat.c
And these are the ones I could not build-test:
aix-thread.c
arm-netbsd-nat.c
ppc-fbsd-nat.c
ppc-netbsd-nat.c
ia64-tdep.c (the part that needs libunwind)
ppc-obsd-nat.c
rs6000-nat.c
If there are still some build problems related to gdbarch_tdep in them,
they should be pretty obvious to fix.
Change-Id: Iaa3d791a850e4432973757598e634e3da6061428
