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Author SHA1 Message Date
Alan Modra
b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Naveen H.S
2c62985659 MIPS: Add Octeon 3 support 
binutils:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* readelf.c (print_mips_isa_ext): Print the value of Octeon3.

gas:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
	(mips_cpu_info_table): Octeon3 enables virt ase.
	* doc/c-mips.texi: Document octeon3 as an acceptable value for
	-march=.

gas/testsuite:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* gas/mips/mips.exp: Add support for Octeon3 architecture.
	Also add in support for running Octeon3 tests.
	* gas/mips/octeon3.d: New test.
	* gas/mips/octeon3.s: New test source.

opcodes:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* mips-dis.c (mips_arch_choices): Add octeon3.
	* mips-opc.c (IOCT): Include INSN_OCTEON3.
	(IOCT2): Likewise.
	(IOCT3): New define.
	(IVIRT): New define.
	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
	tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
	IVIRT instructions.
	Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
	operand for IOCT3.

bfd:
2014-10-31  Andrew Pinski  <apinski@cavium.com>
            Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

	* archures.c: Add octeon3 for mips target.
	* bfd-in2.h: Regenerate.
	* bfd/cpu-mips.c: Define I_mipsocteon3.
	nfo_struct): Add octeon3 support.
	* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
	octeon3.
	(mips_set_isa_flags): Add support for octeon3.
	(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
	(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
	extension of bfd_mach_mips_octeon2.
	(print_mips_isa_ext): Print the value of Octeon3.
 2014-10-31 13:50:10 -07:00
Andrew Bennett
7361da2c95 Add support for MIPS R6. 
bfd/
 	* aoutx.h (NAME (aout, machine_type)): Add mips32r6 and mips64r6.
 	* archures.c (bfd_architecture): Likewise.
 	* bfd-in2.h (bfd_architecture): Likewise.
 	(bfd_reloc_code_real): Add relocs BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
 	BFD_RELOC_MIPS_19_PCREL_S2.
 	* cpu-mips.c (arch_info_struct): Add mips32r6 and mips64r6.
 	* elf32-mips.c: Define relocs R_MIPS_PC21_S2, R_MIPS_PC26_S2
 	R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elf64-mips.c: Define REL, and RELA relocations R_MIPS_PC21_S2,
	R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2, R_MIPS_PCHI16
	and R_MIPS_PCLO16.
 	(mips_reloc_map): Add entries for BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	* elfn32-mips.c: Likewise.
 	* elfxx-mips.c (MIPSR6_P): New define.
 	(mipsr6_exec_plt_entry): New array.
	(hi16_reloc_p): Add support for R_MIPS_PCHI16.
	(lo16_reloc_p): Add support for R_MIPS_PCLO16.
 	(aligned_pcrel_reloc_p): New function.
 	(mips_elf_relocation_needs_la25_stub): Add support for relocs:
 	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
 	(mips_elf_calculate_relocation): Add support for relocs:
 	R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3, R_MIPS_PC19_S2,
 	R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(_bfd_elf_mips_mach): Add support for mips32r6 and mips64r6.
	(mips_elf_add_lo16_rel_addend): Add support for R_MIPS_PCHI16.
 	(_bfd_mips_elf_check_relocs): Add support for relocs:
	R_MIPS_PC21_S2 and R_MIPS_PC26_S2.
 	(_bfd_mips_elf_relocate_section): Add a check for unaligned
 	pc relative relocs.
 	(_bfd_mips_elf_finish_dynamic_symbol): Add support for MIPS r6
 	plt entry.
 	(mips_set_isa_flags): Add support for mips32r6 and mips64r6.
 	(_bfd_mips_elf_print_private_bfd_data): Likewise.
 	(mips_32bit_flags_p): Add support for mips32r6.
 	* libbfd.h (bfd_reloc_code_real_names): Add entries for
 	BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2,
 	BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2.
 	* reloc.c: Document relocs BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3 and
 	BFD_RELOC_MIPS_19_PCREL_S2.

binutils/
 	* readelf.c (get_machine_flags): Add support for mips32r6 and
 	mips64r6.

elfcpp/
 	* mips.h (E_MIPS_ARCH_32R6, E_MIPS_ARCH_64R6): New enum constants.

gas/
 	* config/tc-mips.c (mips_nan2008): New static global.
	(mips_flag_nan2008): Removed.
	(LL_SC_FMT): New define.
	(COP12_FMT): Updated.
	(ISA_IS_R6): New define.
 	(ISA_HAS_64BIT_REGS): Add mips64r6.
 	(ISA_HAS_DROR): Likewise.
 	(ISA_HAS_64BIT_FPRS): Add mips32r6 and mips64r6.
 	(ISA_HAS_ROR): Likewise.
 	(ISA_HAS_ODD_SINGLE_FPR): Likewise.
 	(ISA_HAS_MXHC1): Likewise.
 	(hilo_interlocks): Likewise.
 	(md_longopts): Likewise.
	(ISA_HAS_LEGACY_NAN): New define.
 	(options): Add OPTION_MIPS32R6 and OPTION_MIPS64R6.
 	(mips_ase): Add field rem_rev.
 	(mips_ases): Updated to add which ISA an ASE was removed in.
 	(mips_isa_rev): Add support for mips32r6 and mips64r6.
 	(mips_check_isa_supports_ase): Add support to check if an ASE
 	has been removed in the specified MIPS ISA revision.
 	(validate_mips_insn): Skip '-' character.
	(macro_build): Likewise.
	(mips_check_options): Prevent R6 working with fp32, mips16,
	micromips, or branch relaxation.
	(file_mips_check_options): Set R6 floating point registers to
	64 bit.  Also deal with the nan2008 option.
 	(limited_pcrel_reloc_p): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	(operand_reg_mask): Add support for OP_SAME_RS_RT, OP_CHECK_PREV
	and OP_NON_ZERO_REG.
 	(match_check_prev_operand): New static function.
 	(match_same_rs_rt_operand): New static function.
	(match_non_zero_reg_operand): New static function.
 	(match_operand): Added entries for: OP_SAME_RS_RT, OP_CHECK_PREV
	and OP_NON_ZERO_REG.
 	(insns_between): Added case to deal with forbidden slots.
 	(append_insn): Added support for relocs: BFD_RELOC_MIPS_21_PCREL_S2
 	and BFD_RELOC_MIPS_26_PCREL_S2.
 	(match_insn): Add support for operands -A, -B, +' and +".  Also
 	skip '-' character.
 	(mips_percent_op): Add entries for %pcrel_hi and %pcrel_lo.
 	(md_parse_option): Add support for mips32r6 and mips64r6.  Also
	update the nan option handling.
 	(md_pcrel_from): Add cases for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2.
 	(mips_force_relocation): Prevent forced relaxation for MIPS r6.
 	(md_apply_fix): Add support for relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
 	(s_mipsset): Add support for mips32r6 and mips64r6.
	(s_nan): Update to support the new nan2008 framework.
 	(tc_gen_reloc): Add relocs: BFD_RELOC_MIPS_21_PCREL_S2,
 	BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
 	BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_HI16_S_PCREL and
 	BFD_RELOC_LO16_PCREL.
	(mips_elf_final_processing): Updated to use the mips_nan2008.
 	(mips_cpu_info_table): Add entries for mips32r6 and mips64r6.
	(macro): Enable ldc2, sdc2, ll, lld, swc2, sc, scd, cache, pref
	macros for R6.
	(mips_fix_adjustable): Make PC relative R6 relocations relative
	to the symbol and not the section.
 	* configure.ac: Add support for mips32r6 and mips64r6.
 	* configure: Regenerate.
 	* doc/c-mips.texi: Document the -mips32r6 and -mips64r6 command line
 	options.
	* doc/as.texinfo: Likewise.

gas/testsuite/
	* gas/mips/24k-triple-stores-1.s: If testing for r6 prevent
	non-supported instructions from being tested.
	* gas/mips/24k-triple-stores-2.s: Likewise.
	* gas/mips/24k-triple-stores-3.s: Likewise.
	* gas/mips/24k-triple-stores-6.s: Likewise.
	* gas/mips/beq.s: Likewise.
	* gas/mips/eva.s: Likewise.
	* gas/mips/ld-zero-3.s: Likewise.
	* gas/mips/mips32-cp2.s: Likewise.
	* gas/mips/mips32.s: Likewise.
	* gas/mips/mips4.s: Likewise.
	* gas/mips/add.s: Don't test the add instructions if r6, and
	add padding.
	* gas/mips/add.d: Check for a triple dot not a nop at the end of the
	disassembly output.
	* gas/mips/micromips@add.d: Likewise.
	* gas/mips/mipsr6@24k-branch-delay-1.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-1.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-2-llsc.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-2.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-3.d: New file.
	* gas/mips/mipsr6@24k-triple-stores-6.d: New file.
	* gas/mips/mipsr6@add.d: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msingle-float.s: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-1-msoft-float.s: New file.
	* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.l: New file.
	* gas/mips/mipsr6@attr-gnu-4-2-mdouble-float.s: New file.
	* gas/mips/mipsr6@beq.d: New file.
	* gas/mips/mipsr6@bge.d: New file.
	* gas/mips/mipsr6@bgeu.d: New file.
	* gas/mips/mipsr6@blt.d: New file.
	* gas/mips/mipsr6@bltu.d: New file.
	* gas/mips/mipsr6@branch-misc-1.d: New file.
	* gas/mips/mipsr6@branch-misc-2-64.d: New file.
	* gas/mips/mipsr6@branch-misc-2pic-64.d: New file.
	* gas/mips/mipsr6@branch-misc-4-64.d: New file.
	* gas/mips/mipsr6@cache.d: New file.
	* gas/mips/mipsr6@eva.d: New file.
	* gas/mips/mipsr6@jal-svr4pic-noreorder.d: New file.
	* gas/mips/mipsr6@jal-svr4pic.d: New file.
	* gas/mips/mipsr6@ld-zero-2.d: New file.
	* gas/mips/mipsr6@ld-zero-3.d: New file.
	* gas/mips/mipsr6@loc-swap-dis.d: New file.
	* gas/mips/mipsr6@mips32-cp2.d: New file.
	* gas/mips/mipsr6@mips32-imm.d: New file.
	* gas/mips/mipsr6@mips32.d: New file.
	* gas/mips/mipsr6@mips32r2.d: New file.
	* gas/mips/mipsr6@mips4-fp.d: New file.
	* gas/mips/mipsr6@mips4-fp.l: New file.
	* gas/mips/mipsr6@mips4-fp.s: New file.
	* gas/mips/mipsr6@mips4.d: New file.
	* gas/mips/mipsr6@mips5-fp.d: New file.
	* gas/mips/mipsr6@mips5-fp.l: New file.
	* gas/mips/mipsr6@mips5-fp.s: New file.
	* gas/mips/mipsr6@mips64.d: New file.
	* gas/mips/mipsr6@msa-branch.d: New file.
	* gas/mips/mipsr6@msa.d: New file.
	* gas/mips/mipsr6@pref.d: New file.
	* gas/mips/mipsr6@relax-swap3.d: New file.
	* gas/mips/r6-64-n32.d: New file.
	* gas/mips/r6-64-n64.d: New file.
	* gas/mips/r6-64-removed.l: New file.
	* gas/mips/r6-64-removed.s: New file.
	* gas/mips/r6-64.s: New file.
	* gas/mips/r6-attr-none-double.d: New file.
	* gas/mips/r6-n32.d: New file.
	* gas/mips/r6-n64.d: New file.
	* gas/mips/r6-removed.l: New file.
	* gas/mips/r6-removed.s: New file.
	* gas/mips/r6.d: New file.
	* gas/mips/r6.s: New file.
	* gas/mips/mipsr6@mips32-dsp.d: New file.
	* gas/mips/mipsr6@mips32-dspr2.d: New file.
	* gas/mips/mipsr6@mips32r2-ill.l: New file.
	* gas/mips/mipsr6@mips32r2-ill.s: New file.
	* gas/mips/cache.s: Add r6 instruction varients.
	* gas/mips/mips.exp: Add support for the mips32r6 and mips64r6
	architectures.  Also prevent non r6 supported tests from running.
	Finally, add in support for running the new r6 tests.
	(run_dump_test_arch): Add support for mipsr6 tests.
	(run_list_test_arch): Add support for using files of the
	form arch@testname.l .

include/elf/
 	* mips.h: Add relocs: R_MIPS_PC21_S2, R_MIPS_PC26_S2, R_MIPS_PC18_S3,
 	R_MIPS_PC19_S2, R_MIPS_PCHI16 and R_MIPS_PCLO16.
 	(E_MIPS_ARCH_32R6): New define.
 	(E_MIPS_ARCH_64R6): New define.

include/opcode/
 	* mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
 	OP_CHECK_PREV and OP_NON_ZERO_REG.  Add descriptions for the MIPS R6
	instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
	 +I, +O, +R, +:, +\, +", +;
	(mips_check_prev_operand): New struct.
 	(INSN2_FORBIDDEN_SLOT): New define.
 	(INSN_ISA32R6): New define.
 	(INSN_ISA64R6): New define.
	(INSN_UPTO32R6): New define.
	(INSN_UPTO64R6): New define.
	(mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
 	(ISA_MIPS32R6): New define.
 	(ISA_MIPS64R6): New define.
 	(CPU_MIPS32R6): New define.
 	(CPU_MIPS64R6): New define.
 	(cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.

ld/
 	* ldmain.c (get_emulation): Add support for -mips32r6 and -mips64r6.

opcodes/
 	* mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 	mips64r6.
 	(parse_mips_dis_option): Allow MSA and virtualization support for
 	mips64r6.
 	(mips_print_arg_state): Add fields dest_regno and seen_dest.
 	(mips_seen_register): New function.
 	(print_insn_arg): Refactored code to use mips_seen_register
	function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
	OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
	the register rather than aborting.
 	(print_insn_args): Add length argument.  Add code to correctly
	calculate the instruction address for pc relative instructions.
	(validate_insn_args): New static function.
 	(print_insn_mips): Prevent jalx disassembling for r6.  Use
	validate_insn_args.
	(print_insn_micromips): Use validate_insn_args.
	all the arguments are valid.
	* mips-formats.h (PREV_CHECK): New define.
 	* mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 	-t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 	(RD_pc): New define.
 	(FS): New define.
 	(I37): New define.
 	(I69): New define.
 	(mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 	MIPS R6 instructions from MIPS R2 instructions.
 2014-09-15 12:15:55 +01:00
Maciej W. Rozycki
5575639b8d MIPS: Make the CODE10 operand code consistent between ISAs 
This change moves the microMIPS 10-bit uninterpreted immediate code
embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL
instructions from `B' over to `+J' which is the operand code used in
the standard MIPS instruction set for a similar code embedded at bits
20..11, currently used by HYPCALL only in that set.

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
	(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
	"sdbbp", "syscall" and "wait".

	include/opcode/
	* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
	over to `+J'.
 2014-08-26 13:44:34 +01:00
Matthew Fortune
43885403ed [MIPS] Rename COPROC related macros 
gas/

	* config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC
	and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout.

include/opcode/

	* mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
	(INSN_LOAD_COPROC): New define.
	(INSN_COPROC_MOVE_DELAY): Rename to...
	(INSN_COPROC_MOVE): New define.

opcodes/

	* micromips-opc.c (COD): Rename throughout to...
	(CM): New define, update to use INSN_COPROC_MOVE.
	(LCD): Rename throughout to...
	(LC): New define, update to use INSN_LOAD_COPROC.
	* mips-opc.c: Likewise.
 2014-07-29 13:58:54 +01:00
Andrew Bennett
ae52f48306 Add MIPS r3 and r5 support. 
This patch firstly adds support for mips32r3 mips32r5, mips64r3
and mips64r5.  Secondly it adds support for the eretnc instruction.

ChangeLog:

bfd/
	* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
	mips32r5 and mips64r5.
	* archures.c (bfd_architecture): Likewise.
	* bfd-in2.h (bfd_architecture): Likewise.
	* cpu-mips.c (arch_info_struct): Likewise.
	* elfxx-mips.c (mips_set_isa_flags): Likewise.

gas/
	* tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
	and mips64r5.
	(ISA_HAS_64BIT_FPRS): Likewise.
	(ISA_HAS_ROR): Likewise.
	(ISA_HAS_ODD_SINGLE_FPR): Likewise.
	(ISA_HAS_MXHC1): Likewise.
	(hilo_interlocks): Likewise.
	(md_longopts): Likewise.
	(ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
	(ISA_HAS_DROR): Likewise.
	(options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
	OPTION_MIPS64R5.
	(mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
	mips64r5.
	(md_parse_option): Likewise.
	(s_mipsset): Likewise.
	(mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
	and mips64r5.  Also change p5600 entry to be mips32r5.
	* configure.in: Add support for mips32r3, mips32r5, mips64r3 and
	mips64r5.
	* configure: Regenerate.
	* doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
	-mips64r5 command line options.
	* doc/as.texinfo: Likewise.

gas/testsuite/
	* gas/mips/mips.exp: Add MIPS32r5 tests.  Also add the mips32r3,
	mips32r5, mips64r3 and mips64r5 isas to the testsuite.
	* gas/mips/r5.s: New test.
	* gas/mips/r5.d: Likewise.

include/opcode/
	* mips.h (INSN_ISA_MASK): Updated.
	(INSN_ISA32R3): New define.
	(INSN_ISA32R5): New define.
	(INSN_ISA64R3): New define.
	(INSN_ISA64R5): New define.
	(INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
	INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
	(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
	mips64r5.
	(INSN_UPTO32R3): New define.
	(INSN_UPTO32R5): New define.
	(INSN_UPTO64R3): New define.
	(INSN_UPTO64R5): New define.
	(ISA_MIPS32R3): New define.
	(ISA_MIPS32R5): New define.
	(ISA_MIPS64R3): New define.
	(ISA_MIPS64R5): New define.
	(CPU_MIPS32R3): New define.
	(CPU_MIPS32R5): New define.
	(CPU_MIPS64R3): New define.
	(CPU_MIPS64R5): New define.

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
	(I34): New define.
	(I36): New define.
	(I66): New define.
	(I68): New define.
	* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
	mips64r5.
	(parse_mips_dis_option): Update MSA and virtualization support to
	allow mips64r3 and mips64r5.
 2014-05-07 11:47:29 +01:00
Richard Sandiford
3efe9ec51e include/opcode/ 
* mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
 2014-05-01 21:39:48 +01:00
Andrew Bennett
7d64c587c1 Add support for the MIPS eXtended Physical Address (XPA) ASE. 
ChangeLog:

binutils/
	* doc/binutils.texi: Document the disassemble MIPS XPA instructions
	command line option.

gas/
	* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
 	(md_longopts): Add xpa and no-xpa command line options.
 	(mips_ases): Add MIPS XPA ASE.
 	(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
 	* doc/as.texinfo: Document the MIPS XPA command line options.
 	* doc/c-mips.texi: Document the MIPS XPA command line options,
 	and assembler directives.

gas/testsuite/
 	* gas/mips/mips.exp: Add xpa tests.
 	* gas/mips/xpa.s: New test.
 	* gas/mips/xpa.d: Likewise.

include/
 	* opcode/mips.h (ASE_XPA): New define.

opcodes/
 	* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 	to allow the MIPS XPA ASE.
 	(parse_mips_dis_option): Process the -Mxpa option.
 	* mips-opc.c (XPA): New define.
 	(mips_builtin_opcodes): Add MIPS XPA instructions and move the
 	locations of the ctc0 and cfc0 instructions.
 2014-04-23 13:01:18 +01:00
Alan Modra
4b95cf5c0c Update copyright years 2014-03-05 22:16:15 +10:30
Andrew Bennett
e269fea784 Range of element index is too large on MIPS MSA element selection instructions. 
The element index range for the following MIPS MSA instructions: sldi, splati,
copy_s, copy_u, insert and insve is 1 bit too large.  This patch fixes this issue.

ChangeLog:

	gas/testsuite/gas/mips/
	* msa.s: Reduced maximum element index range for sldi, splati,
	copy_s, copy_u, insert and insve instructions.
	* msa64.s: Likewise.
	* micromips@msa.d: Likewise.
	* micromips@msa64.d: Likewise.
	* msa.d: Likewise.
	* msa64.d: Likewise.

	include/opcode/
	* mips.h: Updated description of +o, +u, +v and +w for MIPS and
	microMIPS.

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
	+v and +w.
	(micromips_opcodes): Reduced element index range for sldi, splati,
	copy_s, copy_u, insert and insve instructions.
	* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
	+v and +w.
	(mips_builtin_opcodes): Reduced element index range for sldi, splati,
	copy_s, copy_u, insert and insve instructions.
 2013-12-16 07:43:20 -08:00
Catherine Moore
67dc82bc51 2013-11-11 Catherine Moore <clm@codesourcery.com> 
gas/
	* config/mips/tc-mips.c (convert_reg_type): Use
	INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
	(reg_needs_delay): Likewise.
	(insns_between): Likewise.

	include/
	* opcode/mips.h (INSN_LOAD_MEMORY_DELAY): Rename to...
	(INSN_LOAD_MEMORY): ...this.

	opcodes/
	* mips-dis.c (print_insn_mips): Use
	INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
	(print_insn_micromips): Likewise.
	* mips-opc.c (LDD): Remove.
	(CLD): Include INSN_LOAD_MEMORY.
	(LM): New.
	(mips_builtin_opcodes): Use LM instead of LDD.
        Add LM to load instructions.
 2013-11-11 08:03:47 -08:00
Chao-ying Fu
387a82f124 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> 
* mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
	(mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
	For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
	+T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
	For MIPS, update extension character sequences after +.
	(ASE_MSA): New define.
	(ASE_MSA64): New define.
	For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
	+x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
	For microMIPS, update extension character sequences after +.
 2013-10-14 18:41:17 +00:00
Richard Sandiford
e423441da4 include/opcode/ 
* mips.h: Remove references to "+I" and imm2_expr.

gas/
	* config/tc-mips.c (imm2_expr): Delete.
	(md_assemble, match_insn, imm2_expr.X_op, mips_ip): Update accordingly.
 2013-08-19 19:56:44 +00:00
Richard Sandiford
5e0dc5bae9 include/opcode/ 
* mips.h (M_DEXT, M_DINS): Delete.

opcodes/
	* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
	macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
	Use +H rather than +C for the real "dext".
	* mips-opc.c (mips_builtin_opcodes): Likewise.

gas/
	* config/tc-mips.c (report_bad_range, report_bad_field): Delete.
	(macro): Remove M_DEXT and M_DINS handling.

gas/testsuite/
	* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
	error messages to have the same form as the EXT and INS ones.
	* gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d,
	gas/mips/micromips-trap.d, gas/mips/micromips.d,
	gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect
	"dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
 2013-08-19 19:54:41 +00:00
Richard Sandiford
0f35dbc4d9 include/opcode/ 
* mips.h (OP_OPTIONAL_REG): New mips_operand_type.
	(mips_optional_operand_p): New function.

opcodes/
	* mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
	* micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
	and OPTIONAL_MAPPED_REG.
	* mips-opc.c (decode_mips_operand): Likewise.
	* mips16-opc.c (decode_mips16_operand): Likewise.
	* mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.

gas/
	* config/tc-mips.c (operand_reg_mask, match_operand): Handle
	OP_OPTIONAL_REG.
	(mips_ip, mips16_ip): Use mips_optional_operand_p to check
	for optional operands.
 2013-08-19 18:57:00 +00:00
Richard Sandiford
14daeee3ae include/opcode/ 
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* mips.h: Document new VU0 operand characters.
	(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
	(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
	(OP_REG_R5900_ACC): New mips_reg_operand_types.
	(INSN2_VU0_CHANNEL_SUFFIX): New macro.
	(mips_vu0_channel_mask): Declare.

opcodes/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
	OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
	(print_vu0_channel): New function.
	(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
	(print_insn_args): Handle '#'.
	(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
	* mips-opc.c (mips_vu0_channel_mask): New constant.
	(decode_mips_operand): Handle new VU0 operand types.
	(VU0, VU0CH): New macros.
	(mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
	for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
	Use "+6" rather than "G" for QMFC2 and QMTC2.

gas/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
	(RWARN): Bump to 0x8000000.
	(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
	(RTYPE_R5900_ACC): New register types.
	(RTYPE_MASK): Include them.
	(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
	macros.
	(reg_names): Include them.
	(mips_parse_register_1): New function, split out from...
	(mips_parse_register): ...here.  Add a channels_ptr parameter.
	Look for VU0 channel suffixes when nonnull.
	(reg_lookup): Update the call to mips_parse_register.
	(mips_parse_vu0_channels): New function.
	(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
	(mips_operand_token): Add a "channels" field to the union.
	Extend the comment above "ch" to OT_DOUBLE_CHAR.
	(mips_parse_base_start): Match -- and ++.  Handle channel suffixes.
	(mips_parse_argument_token): Handle channel suffixes here too.
	(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
	Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
	Handle '#' formats.
	(md_begin): Register $vfN and $vfI registers.
	(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
	(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
	OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
	(match_vu0_suffix_operand): New function.
	(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
	(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
	(mips_lookup_insn): New function.
	(mips_ip): Use it.  Allow "+K" operands to be elided at the end
	of an instruction.  Handle '#' sequences.

gas/testsuite/
2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>

	* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
	coprocessor registers.
	* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
	gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
	gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
	* gas/mips/mips.exp: Run them.
 2013-08-04 07:31:39 +00:00
Richard Sandiford
3ccad066ac include/opcode/ 
* mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
	(mips_int_operand_min, mips_int_operand_max): New functions.
	(mips_decode_pcrel_operand): Use mips_decode_int_operand.

opcodes/
	* mips-formats.h (PCREL): Reorder parameters and update the definition
	to match new mips_pcrel_operand layout.
	(JUMP, JALX, BRANCH): Update accordingly.
	* mips16-opc.c (decode_mips16_operand): Likewise.

gas/
	* config/tc-mips.c (match_int_operand): Use mips_int_operand_min
	and mips_int_operand_max.
	(mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
	Delete.
	(mips16_immed_operand, mips16_immed_in_range_p): New functions.
	(mips16_immed, mips16_extended_frag): Use them.  Use mips_int_operand
	instead of mips16_immed_operand.
 2013-08-03 10:49:48 +00:00
Richard Sandiford
fc76e73056 include/opcode/ 
* mips.h (mips_decode_reg_operand): New function.
	(INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
	(INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
	(INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
	New macros.
	(INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
	(INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
	(INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
	(INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
	(INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
	(INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
	(INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
	(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
	(INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
	(INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete.  Renumber other
	macros to cover the gaps.
	(INSN2_MOD_SP): Replace with...
	(INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
	(MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
	(MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
	(MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
	(MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
	Delete.

opcodes/
	* mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
	New macros.
	(WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
	(WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
	(mips_builtin_opcodes): Use the new position-based read-write flags
	instead of field-based ones.  Use UDI for "udi..." instructions.
	* mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
	New macros.
	(WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
	(RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
	(WR_SP, RD_16): New macros.
	(RD_SP): Redefine as an INSN2_* flag.
	(MOD_SP): Redefine in terms of RD_SP and WR_SP.
	(mips16_opcodes): Use the new position-based read-write flags
	instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
	pinfo2 field.
	* micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
	New macros.
	(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
	(WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
	(WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
	(RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
	(micromips_opcodes): Use the new position-based read-write flags
	instead of field-based ones.
	* mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
	(print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
	of field-based flags.

gas/
	* config/tc-mips.c (MAX_OPERANDS): New macro.
	(mips_operand_array): New structure.
	(mips_operands, mips16_operands, micromips_operands): New arrays.
	(micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
	(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map)
	(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map)
	(micromips_to_32_reg_q_map): Delete.
	(insn_operands, insn_opno, insn_extract_operand): New functions.
	(validate_mips_insn): Take a mips_operand_array as argument and
	use it to build up a list of operands.  Extend to handle INSN_MACRO
	and MIPS16.
	(validate_mips16_insn): New function.
	(validate_micromips_insn): Take a mips_operand_array as argument.
	Handle INSN_MACRO.
	(md_begin): Initialize mips_operands, mips16_operands and
	micromips_operands.  Call validate_mips_insn and
	validate_micromips_insn for macro instructions too.
	Call validate_mips16_insn for MIPS16 instructions.
	(insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask):
	New functions.
	(gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use
	them.  Handle INSN_UDI.
	(get_append_method): Use gpr_read_mask.
 2013-08-01 20:55:25 +00:00
Richard Sandiford
265459441c include/opcode/ 
* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
	(MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
	(MIPS16_INSN_COND_BRANCH): Delete.

opcodes/
	* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
	(WR_SP): Replace with...
	(MOD_SP): ...this.
	(mips16_opcodes): Update accordingly.
	* mips-dis.c (print_insn_mips16): Likewise.

gas/
	* config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
	flags for MIPS16 and non-MIPS16 instructions.
	(gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
	(gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
	(gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
	(can_swap_branch_p, get_append_method): Use the same flags for MIPS16
	and non-MIPS16 instructions.  Fix formatting.
 2013-08-01 20:40:24 +00:00
Richard Sandiford
c3c0747817 include/opcode/ 
* mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
	OP_SAVE_RESTORE_LIST.
	(decode_mips16_operand): Declare.

opcodes/
	* mips16-opc.c: Include mips-formats.h.
	(reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
	static arrays.
	(decode_mips16_operand): New function.
	* mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
	(print_insn_arg): Handle OP_ENTRY_EXIT list.
	Abort for OP_SAVE_RESTORE_LIST.
	(print_mips16_insn_arg): Change interface.  Use mips_operand
	structures.  Delete GET_OP_S.  Move GET_OP definition to...
	(print_insn_mips16): ...here.  Call init_print_arg_state.
	Update the call to print_mips16_insn_arg.
 2013-07-14 13:36:51 +00:00
Richard Sandiford
ab90248154 include/opcode/ 
* mips.h (mips_operand_type, mips_reg_operand_type): New enums.
	(mips_operand, mips_int_operand, mips_mapped_int_operand)
	(mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
	(mips_pcrel_operand): New structures.
	(mips_insert_operand, mips_extract_operand, mips_signed_operand)
	(mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
	(decode_mips_operand, decode_micromips_operand): Declare.

opcodes/
	* mips-formats.h: New file.
	* mips-opc.c: Include mips-formats.h.
	(reg_0_map): New static array.
	(decode_mips_operand): New function.
	* micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
	(reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
	(reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
	(int_c_map): New static arrays.
	(decode_micromips_operand): New function.
	* mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
	(micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
	(micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
	(micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
	(micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
	(micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
	(micromips_imm_b_map, micromips_imm_c_map): Delete.
	(print_reg): New function.
	(mips_print_arg_state): New structure.
	(init_print_arg_state, print_insn_arg): New functions.
	(print_insn_args): Change interface and use mips_operand structures.
	Delete GET_OP_S.  Move GET_OP definition to...
	(print_insn_mips): ...here.  Update the call to print_insn_args.
	(print_insn_micromips): Use print_insn_args.

gas/
	* config/tc-mips.c (validate_mips_insn): Move further up file.
	Add insn_bits and decode_operand arguments.  Use the mips_operand
	fields to work out which bits an operand occupies.  Detect double
	definitions.
	(validate_micromips_insn): Move further up file.  Call into
	validate_mips_insn.
 2013-07-14 13:28:56 +00:00
Richard Sandiford
cc537e567a include/opcode/ 
* mips.h: Document MIPS16 "I" opcode.

opcodes/
	* mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
	in macros.

gas/
	* config/tc-mips.c (mips16_ip): Handle "I".
 2013-07-14 13:11:03 +00:00
Richard Sandiford
f2ae14a1cc include/opcode/ 
* mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
	(M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
	(M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
	(M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
	(M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
	(M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
	(M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
	(M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
	(M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
	(M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
	(M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
	(M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
	(M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
	Rename to...
	(M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
	(M_USD_AB): ...these.

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
	and SD A(B) macros up.
	* micromips-opc.c (micromips_opcodes): Likewise.

gas/
	* config/tc-mips.c (gprel16_reloc_p): New function.
	(macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are
	BFD_RELOC_UNUSED.
	(offset_high_part, small_offset_p): New functions.
	(nacro): Use them.  Remove *_OB and *_DOB cases.  For single-
	register load and store macros, handle the 16-bit offset case first.
	If a 16-bit offset is not suitable for the instruction we're
	generating, load it into the temporary register using
	ADDRESS_ADDI_INSN.  Make the M_LI_DD code fall through into the
	M_L_DAB code once the address has been constructed.  For double load
	and store macros, again handle the 16-bit offset case first.
	If the second register cannot be accessed from the same high
	part as the first, load it into AT using ADDRESS_ADDI_INSN.
	Fix the handling of LD in cases where the first register is the
	same as the base.  Also handle the case where the offset is
	not 16 bits and the second register cannot be accessed from the
	same high part as the first.  For unaligned loads and stores,
	fuse the offbits == 12 and old "ab" handling.  Apply this handling
	whenever the second offset needs a different high part from the first.
	Construct the offset using ADDRESS_ADDI_INSN where possible,
	for offbits == 16 as well as offbits == 12.  Use offset_reloc
	when constructing the individual loads and stores.
	(mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc
	and offset_reloc before matching against a particular opcode.
	Handle elided 'A' constants.  Allow 'A' constants to use
	relocation operators.

gas/testsuite/
	* gas/mips/ldstla-32.d: Avoid "lui at,0x0" sequences for
	truncated constants.
	* gas/mips/ldstla-32-shared.d: Likewise.
	* gas/mips/mcu.d: Use ADDIU in preference to LI+ADDU when adding
	16-bit constants to the base.
	* gas/mips/micromips@mcu.d: Likewise.
	* gas/mips/micromips@cache.d: Likewise.
	* gas/mips/micromips@pref.d: Likewise.
	* gas/mips/micromips.d, gas/mips/micromips-insn32.d,
	gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d: Likewise.
	Allow the full 16-bit offset range to be used for SB, LB and LBU in
	USH and ULH sequences.  Fix the expected output for LD and SD when
	the two LW and SW offsets need different high parts.
	* gas/mips/eva.s: Test PREFE with relocation operators.
	* gas/mips/eva.d: Use ADDIU in preference to LI+ADDU for 16-bit
	constants.  Update after eva.s change.
	* gas/mips/micromips@eva.d: Likewise.
	* gas/mips/ld-reloc.s, gas/mips/ld-reloc.d, gas/mips/l_d-reloc.s,
	gas/mips/l_d-reloc.d, gas/mips/ulw-reloc.s, gas/mips/ulw-reloc.d,
	gas/mips/micromips@ulw-reloc.d, gas/mips/ulh-reloc.s,
	gas/mips/ulh-reloc.d: New tests.
	* gas/mips/mips.exp: Run them.
 2013-07-07 11:32:32 +00:00
Richard Sandiford
5c324c169b include/opcode/ 
* mips.h: Remove documentation of "[" and "]".  Update documentation
	of "k" and the MDMX formats.

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
	MDMX-like instructions.
	* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
	printing "Q" operands for INSN_5400 instructions.

gas/
	* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
	(mips_ip): Likewise.  Do not set is_mdmx for INSN_5400 instructions.
	Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.

gas/testsuite/
	* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test.
	* gas/mips/mips.exp: Run it.
 2013-07-07 10:15:09 +00:00
Richard Sandiford
23e69e47b4 include/opcode/ 
* mips.h: Update documentation of "+s" and "+S".

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
	"+S" for "cins".
	* mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
	Combine cases.

gas/
	* config/tc-mips.c (mips_ip): Preserve the real bit number for "+p".
	Require the msb to be <= 31 for "+s".  Check that the size is <= 31
	for both "+s" and "+S".
 2013-07-07 10:00:43 +00:00
Richard Sandiford
27c5c572c9 include/opcode/ 
* mips.h: Document "+i".

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
	"jalx".
	* mips16-opc.c (mips16_opcodes): Likewise.
	* micromips-opc.c (micromips_opcodes): Likewise.
	* mips-dis.c (print_insn_args, print_mips16_insn_arg)
	(print_insn_mips16): Handle "+i".
	(print_insn_micromips): Likewise.  Conditionally preserve the
	ISA bit for "a" but not for "+i".

gas/
	* config/tc-mips.c (validate_mips_insn, validate_micromips_insn):
	(mips_ip, mips16_ip): Handle "+i".
 2013-07-07 09:50:43 +00:00
Richard Sandiford
e76ff5abe3 include/opcode/ 
* mips.h: Remove "mi" documentation.  Update "mh" documentation.
	(OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
	Delete.
	(INSN2_WRITE_GPR_MHI): Rename to...
	(INSN2_WRITE_GPR_MH): ...this.

opcodes/
	* micromips-opc.c (WR_mhi): Rename to..
	(WR_mh): ...this.
	(micromips_opcodes): Update "movep" entry accordingly.  Replace
	"mh,mi" with "mh".
	* mips-dis.c (micromips_to_32_reg_h_map): Rename to...
	(micromips_to_32_reg_h_map1): ...this.
	(micromips_to_32_reg_i_map): Rename to...
	(micromips_to_32_reg_h_map2): ...this.
	(print_micromips_insn): Remove "mi" case.  Print both registers
	in the pair for "mh".

gas/
	* config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
	(micromips_to_32_reg_h_map): Rename to...
	(micromips_to_32_reg_h_map1): ...this.
	(micromips_to_32_reg_i_map): Rename to...
	(micromips_to_32_reg_h_map2): ...this.
	(mips_lookup_reg_pair): New function.
	(gpr_write_mask, macro): Adjust after above renaming.
	(validate_micromips_insn): Remove "mi" handling.
	(mips_ip): Likewise.  Parse both registers in a pair for "mh".
 2013-07-07 09:41:04 +00:00
Richard Sandiford
fa7616a4c7 include/opcode/ 
* mips.h: Remove documentation of "+D" and "+T".

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
	* micromips-opc.c (micromips_opcodes): Likewise.
	* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
	and "+T" handling.  Check for a "0" suffix when deciding whether to
	use coprocessor 0 names.  In that case, also check for ",H" selectors.

gas/
	* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
	(mips_ip): Remove "+D" and "+T" handling.

gas/testsuite/
	* gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names
	for LWC0 and SWC0.
 2013-07-07 09:32:55 +00:00
Richard Sandiford
18870af79b include/opcode/ 
* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
	Use "source" rather than "destination" for microMIPS "G".

gas/
	* config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
 2013-06-26 07:04:57 +00:00
Maciej W. Rozycki
833794fc12 bfd/ 
* elfxx-mips.h (_bfd_mips_elf_insn32): New prototype.
	* elfxx-mips.c (mips_elf_link_hash_table): Add insn32 member.
	(STUB_MOVE32_MICROMIPS, STUB_JALR32_MICROMIPS): New macros.
	(MICROMIPS_INSN32_FUNCTION_STUB_NORMAL_SIZE): Likewise.
	(MICROMIPS_INSN32_FUNCTION_STUB_BIG_SIZE): Likewise.
	(micromips_insn32_o32_exec_plt0_entry): New variable.
	(micromips_insn32_o32_exec_plt_entry): Likewise.
	(_bfd_mips_elf_adjust_dynamic_symbol): Handle insn32 mode.
	(mips_elf_estimate_stub_size): Likewise.
	(_bfd_mips_elf_size_dynamic_sections): Likewise.
	(_bfd_mips_elf_finish_dynamic_symbol): Likewise.
	(mips_finish_exec_plt): Likewise.
	(_bfd_mips_elf_relax_section): Likewise.
	(_bfd_mips_elf_insn32): New function.
	(_bfd_mips_elf_get_synthetic_symtab): Handle insn32 PLT.

	gas/
	* config/tc-mips.c (mips_set_options): Add insn32 member.
	(mips_opts): Initialize it.
	(NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode.
	(options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values.
	(md_longopts): Add "minsn32" and "mno-insn32" options.
	(is_size_valid): Handle insn32 mode.
	(md_assemble): Pass instruction string down to macro.
	(brk_fmt): Add second dimension and insn32 mode initializers.
	(mfhl_fmt): Likewise.
	(BRK_FMT, MFHL_FMT): Handle insn32 mode.
	(macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding.
	(macro_build_jalr, move_register): Handle insn32 mode.
	(macro_build_branch_rs): Likewise.
	(macro): Handle insn32 mode.
	<M_JRADDIUSP>, <M_JRC>, <M_MOVEP>: New cases.
	(mips_ip): Handle insn32 mode.
	(md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32.
	(s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops.
	(mips_handle_align): Handle insn32 mode.
	(md_show_usage): Add -minsn32 and -mno-insn32.

	* doc/as.texinfo (Target MIPS options): Add -minsn32 and
	-mno-insn32 options.
	(-minsn32, -mno-insn32): New options.
	* doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32
	options.
	(MIPS assembly options): New node.  Document .set insn32 and
	.set noinsn32.
	(MIPS-Dependent): List the new node.

	gas/testsuite/
	* gas/mips/micromips-insn32.d: New test.
	* gas/mips/micromips-noinsn32.d: Likewise.
	* gas/mips/micromips.l: Rename to...
	* gas/mips/micromips-warn.l: ... this.
	* gas/mips/micromips.d: Update accordingly.
	* gas/mips/micromips-trap.d: Likewise.
	* gas/mips/micromips.l: New list test.
	* gas/mips/micromips.s: Add conditionals.
	* gas/mips/mips.exp: Run the new tests.

	include/opcode/
	* mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
	values.

	ld/
	* emultempl/mipself.em (insn32): New variable.
	(mips_create_output_section_statements): Handle insn32 mode.
	(PARSE_AND_LIST_PROLOGUE): New macro.
	(PARSE_AND_LIST_LONGOPTS): Likewise.
	(PARSE_AND_LIST_OPTIONS): Likewise.

	* gen-doc.texi: Set MIPS.
	* ld.texinfo: Likewise.
	(Options specific to MIPS targets): New section.
	(ld and MIPS family): New node.
	(Top, Machine Dependent): List the new node.

	opcodes/
	* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
	and "movep" macros.
 2013-06-25 18:02:34 +00:00
Richard Sandiford
c3678916c6 include/opcode/ 
* mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.

gas/
	* config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
 2013-06-23 20:12:53 +00:00
Catherine Moore
7f3c40729d 2013-06-17 Catherine Moore <clm@codesourcery.com> 
Maciej W. Rozycki  <macro@codesourcery.com>
	    Chao-Ying Fu  <fu@mips.com>

	gas/testsuite/
	* gas/mips/mips.exp: Run new tests.
	* gas/mips/eva.d: New.
	* gas/mips/eva.s: New.
	* gas/mips/micromips@eva.d: New.

	gas/
	* config/tc-mips.c (mips_set_options): Add ase_eva.
	(mips_set_options mips_opts): Add ase_eva.
	(file_ase_eva): Declare.
	(ISA_SUPPORTS_EVA_ASE): Define.
	(IS_SEXT_9BIT_NUM): Define.
	(MIPS_CPU_ASE_EVA): Define.
	(is_opcode_valid): Add support for ase_eva.
	(macro_build): Likewise.
	(macro): Likewise.
	(validate_mips_insn): Likewise.
	(validate_micromips_insn): Likewise.
	(mips_ip): Likewise.
	(options): Add OPTION_EVA and OPTION_NO_EVA.
	(md_longopts): Add -meva and -mno-eva.
	(md_parse_option): Process new options.
	(mips_after_parse_args): Check for valid EVA combinations.
	(s_mipsset): Likewise.

	include/
	* opcode/mips.h (OP_SH_EVAOFFSET): Define.
	(OP_MASK_EVAOFFSET): Define.
	(INSN_ASE_MASK): Delete.
	(ASE_EVA): Define.
	(M_CACHEE_AB, M_CACHEE_OB): New.
	(M_LBE_OB, M_LBE_AB): New.
	(M_LBUE_OB, M_LBUE_AB): New.
	(M_LHE_OB, M_LHE_AB): New.
	(M_LHUE_OB, M_LHUE_AB): New.
	(M_LLE_AB, M_LLE_OB): New.
	(M_LWE_OB, M_LWE_AB): New.
	(M_LWLE_AB, M_LWLE_OB): New.
	(M_LWRE_AB, M_LWRE_OB): New.
	(M_PREFE_AB, M_PREFE_OB): New.
	(M_SCE_AB, M_SCE_OB): New.
	(M_SBE_OB, M_SBE_AB): New.
	(M_SHE_OB, M_SHE_AB): New.
	(M_SWE_OB, M_SWE_AB): New.
	(M_SWLE_AB, M_SWLE_OB): New.
	(M_SWRE_AB, M_SWRE_OB): New.
	(MICROMIPSOP_SH_EVAOFFSET): Define.
	(MICROMIPSOP_MASK_EVAOFFSET): Define.

	opcodes/
	* micromips-opc.c (EVA): Define.
	(TLBINV): Define.
	(micromips_opcodes): Add EVA opcodes.
	* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
	(print_insn_args): Handle EVA offsets.
	(print_insn_micromips): Likewise.
	* mips-opc.c (EVA): Define.
	(TLBINV): Define.
	(mips_builtin_opcodes): Add EVA opcodes.
 2013-06-17 22:59:10 +00:00
Richard Sandiford
d301a56b40 gas/ 
2013-06-08  Catherine Moore  <clm@codesourcery.com>

	* config/tc-mips.c (is_opcode_valid):  Build ASE mask.
	(is_opcode_valid_16): Pass ase value to opcode_is_member.
	(append_insn): Change INSN_xxxx to ASE_xxxx.

include/
2013-06-08  Catherine Moore  <clm@codesourcery.com>

	* opcode/mips.h (mips_opcode): Add ase field.
	(INSN_ASE_MASK): Delete.
	(INSN_DSP): Rename to ASE_DSP.  Provide new value.
	(INSN_DSPR2): Rename to ASE_DSPR2.  Provide new value.
	(INSN_MCU): Rename to ASE_MCU.  Provide new value.
	(INSN_MDMX): Rename to ASE_MDMX.  Provide new value.
	(INSN_MIPS3d): Rename to ASE_MIPS3D.  Provide new value.
	(INSN_MT): Rename to ASE_MT.  Provide new value.
	(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS.  Provide new value.
	(INSN_VIRT): Rename to ASE_VIRT.  Provide new value.
	(INSN_VIRT64): Rename to ASE_VIRT64.  Provide new value.
	(opcode_is_member): Add ase argument.  Check ase.

opcodes/
2013-06-08  Catherine Moore  <clm@codesourcery.com>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* micromips-opc.c (D32, D33, MC): Update definitions.
 	(micromips_opcodes):  Initialize ase field.
	* mips-dis.c (mips_arch_choice): Add ase field.
	(mips_arch_choices): Initialize ase field.
	(set_default_mips_dis_options): Declare and setup mips_ase.
	* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
	MT32, MC): Update definitions.
	(mips_builtin_opcodes): Initialize ase field.
 2013-06-08 10:22:55 +00:00
Richard Sandiford
c77c0862b2 include/opcode/ 
2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips.h (M_LQC2_AB, M_SQC2_AB): New macros.

opcodes/
2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.

gas/
2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>

	* config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB.

gas/testsuite/
2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>

	* gas/mips/r5900-full.s, gas/mips/r5900-full.d: Add tests for LQ
	and SQ macros.
	* gas/mips/r5900-vu0.s, gas/mips/r5900-vu0.d: New test.
	* gas/mips/mips.exp: Run it.
 2013-05-22 18:08:26 +00:00
Andrew Pinski
b015e599c7 binutils/ChangeLog: 
* doc/binutils.texi: Document -Mvirt disassembler option.

gas/ChangeLog:
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
(mips_opts): Update for the new field.
(file_ase_virt): New variable.
(ISA_SUPPORTS_VIRT_ASE): New macro.
(ISA_SUPPORTS_VIRT64_ASE): New macro.
(MIPS_CPU_ASE_VIRT): New define.
(is_opcode_valid): Handle ase_virt.
(macro_build): Handle "+J".
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
(md_longopts): Add mvirt and mnovirt
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
(mips_after_parse_args): Handle ase_virt field.
(s_mipsset): Handle "virt" and "novirt".
(mips_elf_final_processing): Add a comment about virt ASE might need a new flag.
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
* doc/c-mips.texi: Document -mvirt and -mno-virt.
Document ".set virt" and ".set novirt".

gas/testsuite/ChangeLog:
* gas/mips/mips.exp: Run virt and virt64 testcases.
* gas/mips/virt.d: New file.
* gas/mips/virt.s: New file.
* gas/mips/virt64.d: New file.
* gas/mips/virt64.s: New file.

include/opcode/ChangeLog:
* mips.h (OP_MASK_CODE10): Correct definition.
(OP_SH_CODE10): Likewise.
Add a comment that "+J" is used now for OP_*CODE10.
(INSN_ASE_MASK): Update.
(INSN_VIRT): New macro.
(INSN_VIRT64): New macro

opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 .
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
 2013-05-10 01:08:48 +00:00
Nick Clifton
e407c74b5b * archures.c: Add support for MIPS r5900 
* bfd-in2.h: Add support for MIPS r5900
	* config.bfd: Add support for Sony Playstation 2
	* cpu-mips.c: Add support for MIPS r5900
	* elfxx-mips.c: Add support for MIPS r5900 (extension of r4000)

	* config/tc-mips.c: Add support for MIPS r5900
	Add M_LQ_AB and M_SQ_AB to support large values for instructions lq and sq.
	* config/tc-mips.c (can_swap_branch_p, get_append_method): Detect some conditional short loops to fix a bug on the r5900 by NOP in the branch delay slot.
	* config/tc-mips.c (M_MUL): Support 3 operands in multu on r5900.
	* config/tc-mips.c (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I.
	* config/tc-mips.c (s_mipsset): Force 32 bit floating point on r5900.
	* configure.in: Detect CPU type when target string contains r5900 (e.g. mips64r5900el-linux-gnu).

	* config/tc-mips.c (mips_ip): Check parameter range of instructions mfps and mtps on r5900.

	* elf/mips.h: Add MIPS machine variant number for r5900 which is compatible with old Playstation 2 software.
	* opcode/mips.h: Add support for r5900 instructions including lq and sq.

	* configure.tgt: Support ELF files for Sony Playstation 2 (for ps2dev and ps2sdk).
	* emulparams/elf32lr5900n32.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI n32.
	* emulparams/elf32lr5900.sh: Create linker script for Sony Playstation 2 ELF files using MIPS ABI o32.
	* Makefile.am: Add linker scripts for Sony Playstation 2 ELF files.

	* opcodes/mips-dis.c: Add names for CP0 registers of r5900.
	* opcodes/mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for instructions sq and lq.

	* opcodes/mips-opc.c: Add support for MIPS r5900 CPU.
	Add support for 128 bit MMI (Multimedia Instructions).
	Add support for EE instructions (Emotion Engine).
	Disable unsupported floating point instructions (64 bit and undefined compare operations).
	Enable instructions of MIPS ISA IV which are supported by r5900.
	Disable 64 bit co processor instructions.
	Disable 64 bit multiplication and division instructions.
	Disable instructions for co-processor 2 and 3, because these are not supported (preparation for later VU0 support (Vector Unit)).
	Disable cvt.w.s because this behaves like trunc.w.s and the correct execution can't be ensured on r5900.
	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This will confuse less developers and compilers.
 2013-01-04 17:22:53 +00:00
Maciej W. Rozycki
35d0a16941 include/opcode/ 
* mips.h (mips_opcode): Add the exclusions field.
	(OPCODE_IS_MEMBER): Remove macro.
	(cpu_is_member): New inline function.
	(opcode_is_member): Likewise.

	opcodes/
	* micromips-opc.c (micromips_opcodes): Update comment.
	* mips-opc.c (mips_builtin_opcodes): Likewise.  Mark coprocessor
	instructions for IOCT as appropriate.
	* mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
	opcode_is_member.
	* configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
	the result of a check for the -Wno-missing-field-initializers
	GCC option.
	* Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
	(mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
	compilation.
	(mips16-opc.lo): Likewise.
	(micromips-opc.lo): Likewise.
	* aclocal.m4: Regenerate.
	* configure: Regenerate.
	* Makefile.in: Regenerate.

	gas/
	* config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.
	(is_opcode_valid): Remove coprocessor instruction exclusions.
	Replace OPCODE_IS_MEMBER with opcode_is_member.
	(is_opcode_valid_16): Replace OPCODE_IS_MEMBER with
	opcode_is_member.
	(macro): Remove coprocessor instruction exclusions.
 2012-08-13 14:26:14 +00:00
Maciej W. Rozycki
03f66e8a8f include/opcode/ 
* mips.h: Document microMIPS DSP ASE usage.
	(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
	microMIPS DSP ASE support.
	(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
	(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
	(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
	(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
	(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
	(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
	(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.

	gas/
	* config/tc-mips.c (macro_build) <'2'>: Handle microMIPS.
	(macro) <M_BALIGN>: Update error handling.
	(validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases.
	<'7', '8', '0', '@', '^'>: Likewise.
	(mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS.
	<'9'>: Fix formatting.
	<'0', '@'>: Handle microMIPS.
	<'^'>: New case.

	gas/testsuite/
	* gas/mips/micromips@mips32-dsp.d: New.
	* gas/mips/micromips@mips32-dspr2.d: New.
	* gas/mips/mips32-dsp.d: Remove -mips32r2.
	* gas/mips/mips32-dspr2.d: Likewise.
	* gas/mips/mips.exp: (mips_create_arch): Use -mips64r2
	for micromips.  Use run_dump_test_arches to run dsp tests.

	opcodes/
	* micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
	(DSP_VOLA): Likewise.
	(D32, D33): Likewise.
	(micromips_opcodes): Add DSP ASE instructions.
	* micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
	<'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
 2012-07-31 21:38:54 +00:00
Maciej W. Rozycki
9d7b4c23ac * mips.h: Fix a typo in description. 2012-07-06 14:20:22 +00:00
Andrew Pinski
432233b359 bfd: 
2011-12-08  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

	* archures.c (bfd_mach_mips_octeon2): New macro
	* bfd-in2.h: Regenerate.
	* cpu-mips.c (I_mipsocteon2): New enum value.
	(arch_info_struct): Add bfd_mach_mips_octeon2.
	* elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2.
	(mips_set_isa_flags): Add bfd_mach_mips_octeon2.
	(mips_mach_extensions): Add bfd_mach_mips_octeon2.

gas:
2011-12-08  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

        * tc-mips.c (CPU_IS_OCTEON): Add Octeon2.
        (mips_cpu_info_table): Add Octeon2.
        * doc/c-mips.texi: Document octeon2 as an acceptable value for -march=.

gas/testsuite:
2011-12-08  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

        * gas/mips/mips.exp: Add Octeon2 for an architecture.
        Run octeon2 test.
        * gas/mips/octeon2.d: New file.
        * gas/mips/octeon2.s: New file.

include/opcode:
2011-12-08  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

        * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
        (INSN_OCTEON2): New macro.
        (CPU_OCTEON2): New macro.
        (OPCODE_IS_MEMBER): Add Octeon2.

opcodes:
2011-12-08  Andrew Pinski  <apinski@cavium.com>
            Adam Nemet  <anemet@caviumnetworks.com>

	* mips-dis.c (mips_arch_choices): Add Octeon2.
	For "octeon+", just include OcteonP for the insn.
	* mips-opc.c (IOCT): Include Octeon2.
	(IOCTP): Include Octeon2.
	(IOCT2): New macro.
	(mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
	"ladd", "lai", "laid", "las", "lasd", "law", "lawd".
	Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
	loads are, and add IOCT2 to them.
	Add "lbx" and "lhux".
	Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
	"qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
	Add "zcb" and "zcbt".
 2011-12-08 20:47:27 +00:00
Andrew Pinski
dd6a37e700 opcode/ 
2011-11-29  Andrew Pinski  <apinski@cavium.com>

        * mips-dis.c (mips_arch_choices): Add Octeon+.
        * mips-opc.c (IOCT): Include Octeon+.
        (IOCTP): New macro.
        (mips_builtin_opcodes): Add "saa" and "saad".
bfd/
2011-11-29  Andrew Pinski  <apinski@cavium.com>

        * archures.c (bfd_mach_mips_octeonp): New macro.
        * bfd-in2.h: Regenerate.
        * bfd/cpu-mips.c (I_mipsocteonp): New enum value.
        (arch_info_struct): Add bfd_mach_mips_octeonp.
        * elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp.
        (mips_mach_extensions): Add bfd_mach_mips_octeonp.
include/opcodes/
2011-11-29  Andrew Pinski  <apinski@cavium.com>

        * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
        (INSN_OCTEONP): New macro.
        (CPU_OCTEONP): New macro.
        (OPCODE_IS_MEMBER): Add Octeon+.
        (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
gas/
2011-11-29  Andrew Pinski  <apinski@cavium.com>

        * config/tc-mips.c (CPU_IS_OCTEON): New macro function.
        (CPU_HAS_SEQ): Change to use CPU_IS_OCTEON.
        (NO_ISA_COP): Likewise.
        (macro) <ld_st>: Add support when off0 is true.
        Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB.
        (mips_cpu_info_table): Add octeon+.
        * doc/c-mips.texi: Document octeon+ as an acceptable value for -march=.
gas/testsuite/
2011-11-29  Andrew Pinski  <apinski@cavium.com>

        * gas/mips/mips.exp: Add octeon+ for an architecture.
        Run octeon-saa-saad test.
        (run_dump_test_arch): For Octeon architectures, also try octeon@.
        * gas/mips/octeon-pref.d: Remove -march=octeon from command line.
        * gas/mips/octeon.d: Likewise.
        * gas/mips/octeon-saa-saad.d: New file.
        * gas/mips/octeon-saa-saad.s: New file
 2011-11-29 20:28:55 +00:00
Maciej W. Rozycki
26f85d7a30 * mips.h: Fix a typo in description. 2011-10-24 14:21:41 +00:00
Maciej W. Rozycki
dec0624dcd gas/ 
* config/tc-mips.c (mips_set_options): Add ase_mcu.
	(mips_opts): Initialise ase_mcu to -1.
	(ISA_SUPPORTS_MCU_ASE): New macro.
	(MIPS_CPU_ASE_MCU): Likewise.
	(is_opcode_valid): Handle MCU.
	(macro_build, macro): Likewise.
	(validate_mips_insn, validate_micromips_insn): Likewise.
	(mips_ip): Likewise.
	(options): Add OPTION_MCU and OPTION_NO_MCU.
	(md_longopts): Add mmcu and mno-mcu.
	(md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU.
	(mips_after_parse_args): Handle MCU.
	(s_mipsset): Likewise.
	(md_show_usage): Handle MCU options.

	* doc/as.texinfo: Document -mmcu and -mno-mcu options.
	* doc/c-mips.texi: Likewise, and document ".set mcu" and
	".set nomcu" directives.

	gas/testsuite/
	* gas/mips/micromips@mcu.d: New test.
	* gas/mips/mcu.d: Likewise.
	* gas/mips/mcu.s: New test source.
	* gas/mips/mips.exp: Run the new tests.

	include/opcode/
	* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
	(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
	(INSN_ASE_MASK): Add the MCU bit.
	(INSN_MCU): New macro.
	(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
	(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.

	opcodes/
	* mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
	and "mips64r2".
	(print_insn_args, print_insn_micromips): Handle MCU.
	* micromips-opc.c (MC): New macro.
	(micromips_opcodes): Add "aclr", "aset" and "iret".
	* mips-opc.c (MC): New macro.
	(mips_builtin_opcodes): Add "aclr", "aset" and "iret".
 2011-08-09 15:20:03 +00:00
Maciej W. Rozycki
2b0c8b40ed include/opcode/ 
* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
	(INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
	(INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
	(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
	(INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
	(INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
	(INSN2_READ_GPR_MMN): Likewise.
	(INSN2_READ_FPR_D): Change the bit used.
	(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
	(INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
	(INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
	(INSN2_COND_BRANCH): Likewise.
	(INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
	(INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
	(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
	(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
	(INSN2_MOD_GPR_MN): Likewise.

	gas/
	* config/tc-mips.c (gpr_mod_mask): Remove INSN2_MOD_GPR_MB,
	INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG,
	INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MM,
	INSN2_MOD_GPR_MN, INSN2_MOD_GPR_MP and INSN2_MOD_GPR_MQ opcode
	register use checks.
	(gpr_read_mask): Add INSN2_READ_GPR_MC, INSN2_READ_GPR_ME
	INSN2_READ_GPR_MG, INSN2_READ_GPR_MJ, INSN2_READ_GPR_MMN,
	INSN2_READ_GPR_MP and INSN2_READ_GPR_MQ opcode register use
	checks.
	(gpr_write_mask): Replace INSN2_WRITE_GPR_S opcode register
	use flag with INSN_WRITE_GPR_S.  Add INSN2_WRITE_GPR_MB,
	INSN2_WRITE_GPR_MHI, INSN2_WRITE_GPR_MJ and INSN2_WRITE_GPR_MP
	opcode register use checks.
	(can_swap_branch_p): Enable microMIPS branch swapping.
	(append_insn): Likewise.

	gas/testsuite/
	* gas/mips/micromips.d: Update according to changes to enable
	microMIPS branch swapping.
	* gas/mips/micromips-trap.d: Likewise.
	* gas/mips/micromips@jal-svr4pic.d: Likewise.
	* gas/mips/micromips@loc-swap.d: Likewise.
	* gas/mips/micromips@loc-swap-dis.d: Likewise.

	opcodes/
	* micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
	(MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
	(MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
	(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
	(RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
	(RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
	(WR_s): Update macro.
	(micromips_opcodes): Update register use flags of: "addiu",
	"addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
	"and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
	"jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
	"lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
	"nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
	"swm" and "xor" instructions.
 2011-08-09 14:25:29 +00:00
Maciej W. Rozycki
7c176fa823 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the 
order of flags documented.
 2011-08-03 21:09:46 +00:00
Maciej W. Rozycki
2309ddf222 bfd/ 
* elfxx-mips.c: Adjust comments throughout.
	(mips_elf_relax_delete_bytes): Reshape code.
	(_bfd_mips_elf_relax_section): Remove check for
	R_MICROMIPS_GPREL16 relocations.  Reshape code.

	gas/
	* config/tc-mips.c: Adjust comments throughout.
	(reglist_lookup): Reshape code.
	(jmp_reloc_p, jalr_reloc_p): Reformat.
	(got16_reloc_p, hi16_reloc_p, lo16_reloc_p): Handle microMIPS
	relocations.
	(gpr_mod_mask): Remove unused variable.
	(gpr_read_mask, gpr_write_mask): Reshape code.
	(fpr_read_mask, fpr_write_mask): Likewise.
	(nops_for_vr4130): Ensure non-microMIPS mode.
	(can_swap_branch_p): Correct pinfo2 reference.  Reshape code.
	(append_insn): Skip Loongson 2F workaround in MIPS16 mode.  Use
	the outermost operator of a compound relocation to determines
	the relocated field.  Fix formatting.
	(md_convert_frag): Reshape code.

	include/opcode/
	* mips.h: Clarify the description of microMIPS instruction
	manipulation macros.
	(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 2011-07-29 22:46:29 +00:00
Richard Sandiford
df58fc944d bfd/ 
2011-02-25  Chao-ying Fu  <fu@mips.com>
            Ilie Garbacea  <ilie@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>
            Joseph Myers  <joseph@codesourcery.com>
            Catherine Moore  <clm@codesourcery.com>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* archures.c (bfd_mach_mips_micromips): New macro.
	* cpu-mips.c (I_micromips): New enum value.
	(arch_info_struct): Add bfd_mach_mips_micromips.
	* elfxx-mips.h (_bfd_mips_elf_is_target_special_symbol): New
	prototype.
	(_bfd_mips_elf_relax_section): Likewise.
	(_bfd_mips16_elf_reloc_unshuffle): Rename to...
	(_bfd_mips_elf_reloc_unshuffle): ... this.  Handle microMIPS
	ASE.
	(_bfd_mips16_elf_reloc_shuffle): Rename to...
	(_bfd_mips_elf_reloc_shuffle): ... this.  Handle microMIPS ASE.
	(gprel16_reloc_p): Handle microMIPS ASE.
	(literal_reloc_p): New function.
	* elf32-mips.c (elf_micromips_howto_table_rel): New variable.
	(_bfd_mips_elf32_gprel16_reloc): Handle microMIPS ASE.
	(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
	and _bfd_mips_elf_reloc_shuffle changes.
	(mips_elf_gprel32_reloc): Update comment.
	(micromips_reloc_map): New variable.
	(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
	(mips_elf32_rtype_to_howto): Likewise.
	(mips_info_to_howto_rel): Likewise.
	(bfd_elf32_bfd_is_target_special_symbol): Define.
	(bfd_elf32_bfd_relax_section): Likewise.
	* elf64-mips.c (micromips_elf64_howto_table_rel): New variable.
	(micromips_elf64_howto_table_rela): Likewise.
	(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
	and _bfd_mips_elf_reloc_shuffle changes.
	(micromips_reloc_map): Likewise.
	(bfd_elf64_bfd_reloc_type_lookup): Handle microMIPS ASE.
	(bfd_elf64_bfd_reloc_name_lookup): Likewise.
	(mips_elf64_rtype_to_howto): Likewise.
	(bfd_elf64_bfd_is_target_special_symbol): Define.
	* elfn32-mips.c (elf_micromips_howto_table_rel): New variable.
	(elf_micromips_howto_table_rela): Likewise.
	(mips16_gprel_reloc): Update for _bfd_mips_elf_reloc_unshuffle
	and _bfd_mips_elf_reloc_shuffle changes.
	(micromips_reloc_map): Likewise.
	(bfd_elf32_bfd_reloc_type_lookup): Handle microMIPS ASE.
	(bfd_elf32_bfd_reloc_name_lookup): Likewise.
	(mips_elf_n32_rtype_to_howto): Likewise.
	(bfd_elf32_bfd_is_target_special_symbol): Define.
	* elfxx-mips.c (LA25_LUI_MICROMIPS_1): New macro.
	(LA25_LUI_MICROMIPS_2): Likewise.
	(LA25_J_MICROMIPS_1, LA25_J_MICROMIPS_2): Likewise.
	(LA25_ADDIU_MICROMIPS_1, LA25_ADDIU_MICROMIPS_2): Likewise.
	(TLS_RELOC_P): Handle microMIPS ASE.
	(mips_elf_create_stub_symbol): Adjust value of stub symbol if
	target is a microMIPS function.
	(micromips_reloc_p): New function.
	(micromips_reloc_shuffle_p): Likewise.
	(got16_reloc_p, call16_reloc_p): Handle microMIPS ASE.
	(got_disp_reloc_p, got_page_reloc_p): New functions.
	(got_ofst_reloc_p): Likewise.
	(got_hi16_reloc_p, got_lo16_reloc_p): Likewise.
	(call_hi16_reloc_p, call_lo16_reloc_p): Likewise.
	(hi16_reloc_p, lo16_reloc_p, jal_reloc_p): Handle microMIPS ASE.
	(micromips_branch_reloc_p): New function.
	(tls_gd_reloc_p, tls_ldm_reloc_p): Likewise.
	(tls_gottprel_reloc_p): Likewise.
	(_bfd_mips16_elf_reloc_unshuffle): Rename to...
	(_bfd_mips_elf_reloc_unshuffle): ... this.  Handle microMIPS
	ASE.
	(_bfd_mips16_elf_reloc_shuffle): Rename to...
	(_bfd_mips_elf_reloc_shuffle): ... this.  Handle microMIPS ASE.
	(_bfd_mips_elf_lo16_reloc): Handle microMIPS ASE.
	(mips_tls_got_index, mips_elf_got_page): Likewise.
	(mips_elf_create_local_got_entry): Likewise.
	(mips_elf_relocation_needs_la25_stub): Likewise.
	(mips_elf_calculate_relocation): Likewise.
	(mips_elf_perform_relocation): Likewise.
	(_bfd_mips_elf_symbol_processing): Likewise.
	(_bfd_mips_elf_add_symbol_hook): Likewise.
	(_bfd_mips_elf_link_output_symbol_hook): Likewise.
	(mips_elf_add_lo16_rel_addend): Likewise.
	(_bfd_mips_elf_check_relocs): Likewise.
	(mips_elf_adjust_addend): Likewise.
	(_bfd_mips_elf_relocate_section): Likewise.
	(mips_elf_create_la25_stub): Likewise.
	(_bfd_mips_vxworks_finish_dynamic_symbol): Likewise.
	(_bfd_mips_elf_gc_sweep_hook): Likewise.
	(_bfd_mips_elf_is_target_special_symbol): New function.
	(mips_elf_relax_delete_bytes): Likewise.
	(opcode_descriptor): New structure.
	(RA): New macro.
	(OP32_SREG, OP32_TREG, OP16_VALID_REG): Likewise.
	(b_insns_32, bc_insn_32, bz_insn_32, bzal_insn_32): New variables.
	(beq_insn_32): Likewise.
	(b_insn_16, bz_insn_16): New variables.
	(BZC32_REG_FIELD): New macro.
	(bz_rs_insns_32, bz_rt_insns_32): New variables.
	(bzc_insns_32, bz_insns_16):Likewise.
	(BZ16_REG, BZ16_REG_FIELD): New macros.
	(jal_insn_32_bd16, jal_insn_32_bd32): New variables.
	(jal_x_insn_32_bd32): Likewise.
	(j_insn_32, jalr_insn_32): Likewise.
	(ds_insns_32_bd16, ds_insns_32_bd32): Likewise.
	(jalr_insn_16_bd16, jalr_insn_16_bd32, jr_insn_16): Likewise.
	(JR16_REG): New macro.
	(ds_insns_16_bd16): New variable.
	(lui_insn): Likewise.
	(addiu_insn, addiupc_insn): Likewise.
	(ADDIUPC_REG_FIELD): New macro.
	(MOVE32_RD, MOVE32_RS): Likewise.
	(MOVE16_RD_FIELD, MOVE16_RS_FIELD): Likewise.
	(move_insns_32, move_insns_16): New variables.
	(nop_insn_32, nop_insn_16): Likewise.
	(MATCH): New macro.
	(find_match): New function.
	(check_br16_dslot, check_br32_dslot): Likewise.
	(check_br16, check_br32): Likewise.
	(IS_BITSIZE): New macro.
	(check_4byte_branch): New function.
	(_bfd_mips_elf_relax_section): Likewise.
	(_bfd_mips_elf_merge_private_bfd_data): Disallow linking MIPS16
	and microMIPS modules together.
	(_bfd_mips_elf_print_private_bfd_data):	Handle microMIPS ASE.
	* reloc.c (BFD_RELOC_MICROMIPS_7_PCREL_S1): New relocation.
	(BFD_RELOC_MICROMIPS_10_PCREL_S1): Likewise.
	(BFD_RELOC_MICROMIPS_16_PCREL_S1): Likewise.
	(BFD_RELOC_MICROMIPS_GPREL16): Likewise.
	(BFD_RELOC_MICROMIPS_JMP, BFD_RELOC_MICROMIPS_HI16): Likewise.
	(BFD_RELOC_MICROMIPS_HI16_S): Likewise.
	(BFD_RELOC_MICROMIPS_LO16): Likewise.
	(BFD_RELOC_MICROMIPS_LITERAL): Likewise.
	(BFD_RELOC_MICROMIPS_GOT16): Likewise.
	(BFD_RELOC_MICROMIPS_CALL16): Likewise.
	(BFD_RELOC_MICROMIPS_GOT_HI16): Likewise.
	(BFD_RELOC_MICROMIPS_GOT_LO16): Likewise.
	(BFD_RELOC_MICROMIPS_CALL_HI16): Likewise.
	(BFD_RELOC_MICROMIPS_CALL_LO16): Likewise.
	(BFD_RELOC_MICROMIPS_SUB): Likewise.
	(BFD_RELOC_MICROMIPS_GOT_PAGE): Likewise.
	(BFD_RELOC_MICROMIPS_GOT_OFST): Likewise.
	(BFD_RELOC_MICROMIPS_GOT_DISP): Likewise.
	(BFD_RELOC_MICROMIPS_HIGHEST): Likewise.
	(BFD_RELOC_MICROMIPS_HIGHER): Likewise.
	(BFD_RELOC_MICROMIPS_SCN_DISP): Likewise.
	(BFD_RELOC_MICROMIPS_JALR): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_GD): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_LDM): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_GOTTPREL): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_TPREL_HI16): Likewise.
	(BFD_RELOC_MICROMIPS_TLS_TPREL_LO16): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

binutils/
2011-02-25  Chao-ying Fu  <fu@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	* readelf.c (get_machine_flags): Handle microMIPS ASE.
	(get_mips_symbol_other): Likewise.

gas/
2011-02-25  Maciej W. Rozycki  <macro@codesourcery.com>
            Chao-ying Fu  <fu@mips.com>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* config/tc-mips.h (mips_segment_info): Add one bit for
	microMIPS.
	(TC_LABEL_IS_LOCAL): New macro.
	(mips_label_is_local): New prototype.
	* config/tc-mips.c (S0, S7): New macros.
	(emit_branch_likely_macro): New variable.
	(mips_set_options): Add micromips.
	(mips_opts): Initialise micromips to -1.
	(file_ase_micromips): New variable.
	(CPU_HAS_MICROMIPS): New macro.
	(hilo_interlocks): Set for microMIPS too.
	(gpr_interlocks): Likewise.
	(cop_interlocks): Likewise.
	(cop_mem_interlocks): Likewise.
	(HAVE_CODE_COMPRESSION): New macro.
	(micromips_op_hash): New variable.
	(micromips_nop16_insn, micromips_nop32_insn): New variables.
	(NOP_INSN): Handle microMIPS ASE.
	(mips32_to_micromips_reg_b_map): New macro.
	(mips32_to_micromips_reg_c_map): Likewise.
	(mips32_to_micromips_reg_d_map): Likewise.
	(mips32_to_micromips_reg_e_map): Likewise.
	(mips32_to_micromips_reg_f_map): Likewise.
	(mips32_to_micromips_reg_g_map): Likewise.
	(mips32_to_micromips_reg_l_map): Likewise.
	(mips32_to_micromips_reg_n_map): Likewise.
	(mips32_to_micromips_reg_h_map): New variable.
	(mips32_to_micromips_reg_m_map): Likewise.
	(mips32_to_micromips_reg_q_map): Likewise.
	(micromips_to_32_reg_h_map): New variable.
	(micromips_to_32_reg_i_map): Likewise.
	(micromips_to_32_reg_m_map): Likewise.
	(micromips_to_32_reg_q_map): Likewise.
	(micromips_to_32_reg_b_map): New macro.
	(micromips_to_32_reg_c_map): Likewise.
	(micromips_to_32_reg_d_map): Likewise.
	(micromips_to_32_reg_e_map): Likewise.
	(micromips_to_32_reg_f_map): Likewise.
	(micromips_to_32_reg_g_map): Likewise.
	(micromips_to_32_reg_l_map): Likewise.
	(micromips_to_32_reg_n_map): Likewise.
	(micromips_imm_b_map, micromips_imm_c_map): New macros.
	(RELAX_DELAY_SLOT_16BIT): New macro.
	(RELAX_DELAY_SLOT_SIZE_FIRST): Likewise.
	(RELAX_DELAY_SLOT_SIZE_SECOND): Likewise.
	(RELAX_MICROMIPS_ENCODE, RELAX_MICROMIPS_P): New macros.
	(RELAX_MICROMIPS_TYPE, RELAX_MICROMIPS_AT): Likewise.
	(RELAX_MICROMIPS_U16BIT, RELAX_MICROMIPS_UNCOND): Likewise.
	(RELAX_MICROMIPS_COMPACT, RELAX_MICROMIPS_LINK): Likewise.
	(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16): Likewise.
	(RELAX_MICROMIPS_MARK_TOOFAR16): Likewise.
	(RELAX_MICROMIPS_CLEAR_TOOFAR16): Likewise.
	(RELAX_MICROMIPS_TOOFAR32): Likewise.
	(RELAX_MICROMIPS_MARK_TOOFAR32): Likewise.
	(RELAX_MICROMIPS_CLEAR_TOOFAR32): Likewise.
	(INSERT_OPERAND, EXTRACT_OPERAND): Handle microMIPS ASE.
	(mips_macro_warning): Add delay_slot_16bit_p, delay_slot_32bit_p,
	fsize and insns.
	(mips_mark_labels): New function.
	(mips16_small, mips16_ext): Remove variables, replacing with...
	(forced_insn_size): ... this.
	(append_insn, mips16_ip): Update accordingly.
	(micromips_insn_length): New function.
	(insn_length): Return the length of microMIPS instructions.
	(mips_record_mips16_mode): Rename to...
	(mips_record_compressed_mode): ... this.  Handle microMIPS ASE.
	(install_insn): Handle microMIPS ASE.
	(reglist_lookup): New function.
	(is_size_valid, is_delay_slot_valid): Likewise.
	(md_begin): Handle microMIPS ASE.
	(md_assemble): Likewise.  Update for append_insn interface change.
	(micromips_reloc_p): New function.
	(got16_reloc_p): Handle microMIPS ASE.
	(hi16_reloc_p): Likewise.
	(lo16_reloc_p): Likewise.
	(jmp_reloc_p): New function.
	(jalr_reloc_p): Likewise.
	(matching_lo_reloc): Handle microMIPS ASE.
	(insn_uses_reg, reg_needs_delay): Likewise.
	(mips_move_labels): Likewise.
	(mips16_mark_labels): Rename to...
	(mips_compressed_mark_labels): ... this.  Handle microMIPS ASE.
	(gpr_mod_mask): New function.
	(gpr_read_mask, gpr_write_mask): Handle microMIPS ASE.
	(fpr_read_mask, fpr_write_mask): Likewise.
	(insns_between, nops_for_vr4130, nops_for_insn): Likewise.
	(fix_loongson2f_nop, fix_loongson2f_jump): Likewise.
	(MICROMIPS_LABEL_CHAR): New macro.
	(micromips_target_label, micromips_target_name): New variables.
	(micromips_label_name, micromips_label_expr): New functions.
	(micromips_label_inc, micromips_add_label): Likewise.
	(mips_label_is_local): Likewise.
	(micromips_map_reloc): Likewise.
	(can_swap_branch_p): Handle microMIPS ASE.
	(append_insn): Add expansionp argument.  Handle microMIPS ASE.
	(start_noreorder, end_noreorder): Handle microMIPS ASE.
	(macro_start, macro_warning, macro_end): Likewise.
	(brk_fmt, cop12_fmt, jalr_fmt, lui_fmt): New variables.
	(mem12_fmt, mfhl_fmt, shft_fmt, trap_fmt): Likewise.
	(BRK_FMT, COP12_FMT, JALR_FMT, LUI_FMT): New macros.
	(MEM12_FMT, MFHL_FMT, SHFT_FMT, TRAP_FMT): Likewise.
	(macro_build): Handle microMIPS ASE.  Update for append_insn
	interface change.
	(mips16_macro_build): Update for append_insn interface change.
	(macro_build_jalr): Handle microMIPS ASE.
	(macro_build_lui): Likewise.  Simplify.
	(load_register): Handle microMIPS ASE.
	(load_address): Likewise.
	(move_register): Likewise.
	(macro_build_branch_likely): New function.
	(macro_build_branch_ccl): Likewise.
	(macro_build_branch_rs): Likewise.
	(macro_build_branch_rsrt): Likewise.
	(macro): Handle microMIPS ASE.
	(validate_micromips_insn): New function.
	(expr_const_in_range): Likewise.
	(mips_ip): Handle microMIPS ASE.
	(options): Add OPTION_MICROMIPS and OPTION_NO_MICROMIPS.
	(md_longopts): Add mmicromips and mno-micromips.
	(md_parse_option): Handle OPTION_MICROMIPS and
	OPTION_NO_MICROMIPS.
	(mips_after_parse_args): Handle microMIPS ASE.
	(md_pcrel_from): Handle microMIPS relocations.
	(mips_force_relocation): Likewise.
	(md_apply_fix): Likewise.
	(mips_align): Handle microMIPS ASE.
	(s_mipsset): Likewise.
	(s_cpload, s_cpsetup, s_cpreturn): Use relocation wrappers.
	(s_dtprel_internal): Likewise.
	(s_gpword, s_gpdword): Likewise.
	(s_insn): Handle microMIPS ASE.
	(s_mips_stab): Likewise.
	(relaxed_micromips_32bit_branch_length): New function.
	(relaxed_micromips_16bit_branch_length): New function.
	(md_estimate_size_before_relax): Handle microMIPS ASE.
	(mips_fix_adjustable): Likewise.
	(tc_gen_reloc): Handle microMIPS relocations.
	(mips_relax_frag): Handle microMIPS ASE.
	(md_convert_frag): Likewise.
	(mips_frob_file_after_relocs): Likewise.
	(mips_elf_final_processing): Likewise.
	(mips_nop_opcode): Likewise.
	(mips_handle_align): Likewise.
	(md_show_usage): Handle microMIPS options.
	* symbols.c (TC_LABEL_IS_LOCAL): New macro.
	(S_IS_LOCAL): Add a TC_LABEL_IS_LOCAL check.

	* doc/as.texinfo (Target MIPS options): Add -mmicromips and
	-mno-micromips.
	(-mmicromips, -mno-micromips): New options.
	* doc/c-mips.texi (-mmicromips, -mno-micromips): New options.
	(MIPS ISA): Document .set micromips and .set nomicromips.
	(MIPS insn): Update for microMIPS support.

gas/testsuite/
2011-02-25  Maciej W. Rozycki  <macro@codesourcery.com>
            Chao-ying Fu  <fu@mips.com>
	    Richard Sandiford  <rdsandiford@googlemail.com>

	* gas/mips/micromips.d: New test.
	* gas/mips/micromips-branch-delay.d: Likewise.
	* gas/mips/micromips-branch-relax.d: Likewise.
	* gas/mips/micromips-branch-relax-pic.d: Likewise.
	* gas/mips/micromips-size-1.d: Likewise.
	* gas/mips/micromips-trap.d: Likewise.
	* gas/mips/micromips.l: New stderr output.
	* gas/mips/micromips-branch-delay.l: Likewise.
	* gas/mips/micromips-branch-relax.l: Likewise.
	* gas/mips/micromips-branch-relax-pic.l: Likewise.
	* gas/mips/micromips-size-0.l: New list test.
	* gas/mips/micromips-size-1.l: New stderr output.
	* gas/mips/micromips.s: New test source.
	* gas/mips/micromips-branch-delay.s: Likewise.
	* gas/mips/micromips-branch-relax.s: Likewise.
	* gas/mips/micromips-size-0.s: Likewise.
	* gas/mips/micromips-size-1.s: Likewise.
	* gas/mips/mips.exp: Run the new tests.

	* gas/mips/dli.s: Use .p2align.
	* gas/mips/elf_ase_micromips.d: New test.
	* gas/mips/elf_ase_micromips-2.d: Likewise.
	* gas/mips/micromips@abs.d: Likewise.
	* gas/mips/micromips@add.d: Likewise.
	* gas/mips/micromips@alnv_ps-swap.d: Likewise.
	* gas/mips/micromips@and.d: Likewise.
	* gas/mips/micromips@beq.d: Likewise.
	* gas/mips/micromips@bge.d: Likewise.
	* gas/mips/micromips@bgeu.d: Likewise.
	* gas/mips/micromips@blt.d: Likewise.
	* gas/mips/micromips@bltu.d: Likewise.
	* gas/mips/micromips@branch-likely.d: Likewise.
	* gas/mips/micromips@branch-misc-1.d: Likewise.
	* gas/mips/micromips@branch-misc-2-64.d: Likewise.
	* gas/mips/micromips@branch-misc-2.d: Likewise.
	* gas/mips/micromips@branch-misc-2pic-64.d: Likewise.
	* gas/mips/micromips@branch-misc-2pic.d: Likewise.
	* gas/mips/micromips@branch-misc-4-64.d: Likewise.
	* gas/mips/micromips@branch-misc-4.d: Likewise.
	* gas/mips/micromips@branch-self.d: Likewise.
	* gas/mips/micromips@cache.d: Likewise.
	* gas/mips/micromips@daddi.d: Likewise.
	* gas/mips/micromips@dli.d: Likewise.
	* gas/mips/micromips@elf-jal.d: Likewise.
	* gas/mips/micromips@elf-rel2.d: Likewise.
	* gas/mips/micromips@elfel-rel2.d: Likewise.
	* gas/mips/micromips@elf-rel4.d: Likewise.
	* gas/mips/micromips@jal-svr4pic.d: Likewise.
	* gas/mips/micromips@jal-svr4pic-noreorder.d: Likewise.
	* gas/mips/micromips@lb-svr4pic-ilocks.d: Likewise.
	* gas/mips/micromips@li.d: Likewise.
	* gas/mips/micromips@loc-swap-dis.d: Likewise.
	* gas/mips/micromips@loc-swap.d: Likewise.
	* gas/mips/micromips@mips1-fp.d: Likewise.
	* gas/mips/micromips@mips32-cp2.d: Likewise.
	* gas/mips/micromips@mips32-imm.d: Likewise.
	* gas/mips/micromips@mips32-sf32.d: Likewise.
	* gas/mips/micromips@mips32.d: Likewise.
	* gas/mips/micromips@mips32r2-cp2.d: Likewise.
	* gas/mips/micromips@mips32r2-fp32.d: Likewise.
	* gas/mips/micromips@mips32r2-sync.d: Likewise.
	* gas/mips/micromips@mips32r2.d: Likewise.
	* gas/mips/micromips@mips4-branch-likely.d: Likewise.
	* gas/mips/micromips@mips4-fp.d: Likewise.
	* gas/mips/micromips@mips4.d: Likewise.
	* gas/mips/micromips@mips5.d: Likewise.
	* gas/mips/micromips@mips64-cp2.d: Likewise.
	* gas/mips/micromips@mips64.d: Likewise.
	* gas/mips/micromips@mips64r2.d: Likewise.
	* gas/mips/micromips@pref.d: Likewise.
	* gas/mips/micromips@relax-at.d: Likewise.
	* gas/mips/micromips@relax.d: Likewise.
	* gas/mips/micromips@rol-hw.d: Likewise.
	* gas/mips/micromips@uld2-eb.d: Likewise.
	* gas/mips/micromips@uld2-el.d: Likewise.
	* gas/mips/micromips@ulh2-eb.d: Likewise.
	* gas/mips/micromips@ulh2-el.d: Likewise.
	* gas/mips/micromips@ulw2-eb-ilocks.d: Likewise.
	* gas/mips/micromips@ulw2-el-ilocks.d: Likewise.
	* gas/mips/cache.d: Likewise.
	* gas/mips/daddi.d: Likewise.
	* gas/mips/mips32-imm.d: Likewise.
	* gas/mips/pref.d: Likewise.
	* gas/mips/elf-rel27.d: Handle microMIPS ASE.
	* gas/mips/l_d.d: Likewise.
	* gas/mips/l_d-n32.d: Likewise.
	* gas/mips/l_d-n64.d: Likewise.
	* gas/mips/ld.d: Likewise.
	* gas/mips/ld-n32.d: Likewise.
	* gas/mips/ld-n64.d: Likewise.
	* gas/mips/s_d.d: Likewise.
	* gas/mips/s_d-n32.d: Likewise.
	* gas/mips/s_d-n64.d: Likewise.
	* gas/mips/sd.d: Likewise.
	* gas/mips/sd-n32.d: Likewise.
	* gas/mips/sd-n64.d: Likewise.
	* gas/mips/mips32.d: Update immediates.
	* gas/mips/micromips@mips32-cp2.s: New test source.
	* gas/mips/micromips@mips32-imm.s: Likewise.
	* gas/mips/micromips@mips32r2-cp2.s: Likewise.
	* gas/mips/micromips@mips64-cp2.s: Likewise.
	* gas/mips/cache.s: Likewise.
	* gas/mips/daddi.s: Likewise.
	* gas/mips/mips32-imm.s: Likewise.
	* gas/mips/elf-rel4.s: Handle microMIPS ASE.
	* gas/mips/lb-pic.s: Likewise.
	* gas/mips/ld.s: Likewise.
	* gas/mips/mips32.s: Likewise.
	* gas/mips/mips.exp: Add the micromips arch.  Exclude mips16e
	from micromips.  Run mips32-imm.

	* gas/mips/jal-mask-11.d: New test.
	* gas/mips/jal-mask-12.d: Likewise.
	* gas/mips/micromips@jal-mask-11.d: Likewise.
	* gas/mips/jal-mask-1.s: Source for the new tests.
	* gas/mips/jal-mask-21.d: New test.
	* gas/mips/jal-mask-22.d: Likewise.
	* gas/mips/micromips@jal-mask-12.d: Likewise.
	* gas/mips/jal-mask-2.s: Source for the new tests.
	* gas/mips/mips.exp: Run the new tests.

	* gas/mips/mips16-e.d: Add --special-syms to `objdump'.
	* gas/mips/tmips16-e.d: Likewise.
	* gas/mips/mipsel16-e.d: Likewise.
	* gas/mips/tmipsel16-e.d: Likewise.

	* gas/mips/and.s: Adjust padding.
	* gas/mips/beq.s: Likewise.
	* gas/mips/bge.s: Likewise.
	* gas/mips/bgeu.s: Likewise.
	* gas/mips/blt.s: Likewise.
	* gas/mips/bltu.s: Likewise.
	* gas/mips/branch-misc-2.s: Likewise.
	* gas/mips/jal.s: Likewise.
	* gas/mips/li.s: Likewise.
	* gas/mips/mips4.s: Likewise.
	* gas/mips/mips4-fp.s: Likewise.
	* gas/mips/relax.s: Likewise.
	* gas/mips/and.d: Update accordingly.
	* gas/mips/elf-jal.d: Likewise.
	* gas/mips/jal.d: Likewise.
	* gas/mips/li.d: Likewise.
	* gas/mips/relax-at.d: Likewise.
	* gas/mips/relax.d: Likewise.

include/elf/
2011-02-25  Chao-ying Fu  <fu@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	* mips.h (R_MICROMIPS_min): New relocations.
	(R_MICROMIPS_26_S1): Likewise.
	(R_MICROMIPS_HI16, R_MICROMIPS_LO16): Likewise.
	(R_MICROMIPS_GPREL16, R_MICROMIPS_LITERAL): Likewise.
	(R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1): Likewise.
	(R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1): Likewise.
	(R_MICROMIPS_CALL16, R_MICROMIPS_GOT_DISP): Likewise.
	(R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST): Likewise.
	(R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16): Likewise.
	(R_MICROMIPS_SUB, R_MICROMIPS_HIGHER): Likewise.
	(R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16): Likewise.
	(R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP): Likewise.
	(R_MICROMIPS_JALR, R_MICROMIPS_HI0_LO16): Likewise.
	(R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM): Likewise.
	(R_MICROMIPS_TLS_DTPREL_HI, R_MICROMIPS_TLS_DTPREL_LO): Likewise.
	(R_MICROMIPS_TLS_GOTTPREL): Likewise.
	(R_MICROMIPS_TLS_TPREL_HI16): Likewise.
	(R_MICROMIPS_TLS_TPREL_LO16): Likewise.
	(R_MICROMIPS_GPREL7_S2, R_MICROMIPS_PC23_S2): Likewise.
	(R_MICROMIPS_max): Likewise.
	(EF_MIPS_ARCH_ASE_MICROMIPS): New macro.
	(STO_MIPS_ISA, STO_MIPS_FLAGS): Likewise.
	(ELF_ST_IS_MIPS_PLT, ELF_ST_SET_MIPS_PLT): Likewise.
	(STO_MICROMIPS): Likewise.
	(ELF_ST_IS_MICROMIPS, ELF_ST_SET_MICROMIPS): Likewise.
	(ELF_ST_IS_COMPRESSED): Likewise.
	(STO_MIPS_PLT, STO_MIPS_PIC): Rework.
	(ELF_ST_IS_MIPS_PIC, ELF_ST_SET_MIPS_PIC): Likewise.
	(STO_MIPS16, ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): Likewise.

include/opcode/
2011-02-25  Chao-ying Fu  <fu@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
	(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
	(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
	(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
	(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
	(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
	(OP_MASK_RS3, OP_SH_RS3): Likewise.
	(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
	(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
	(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
	(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
	(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
	(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
	(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
	(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
	(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
	(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
	(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
	(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
	(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
	(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
	(INSN_WRITE_GPR_S): New macro.
	(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
	(INSN2_READ_FPR_D): Likewise.
	(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
	(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
	(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
	(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
	(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
	(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
	(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
	(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
	(CPU_MICROMIPS): New macro.
	(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
	(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
	(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
	(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
	(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
	(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
	(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
	(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
	(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
	(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
	(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
	(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
	(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
	(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
	(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
	(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
	(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
	(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
	(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
	(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
	(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
	(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
	(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
	(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
	(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
	(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
	(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
	(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
	(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
	(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
	(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
	(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
	(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
	(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
	(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
	(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
	(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
	(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
	(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
	(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
	(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
	(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
	(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
	(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
	(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
	(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
	(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
	(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
	(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
	(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
	(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
	(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
	(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
	(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
	(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
	(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
	(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
	(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
	(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
	(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
	(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
	(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
	(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
	(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
	(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
	(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
	(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
	(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
	(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
	(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
	(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
	(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
	(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
	(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
	(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
	(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
	(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
	(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
	(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
	(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
	(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
	(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
	(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
	(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
	(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
	(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
	(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
	(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
	(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
	(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
	(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
	(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
	(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
	(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
	(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
	(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
	(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
	(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
	(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
	(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
	(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
	(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
	(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
	(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
	(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
	(micromips_opcodes): New declaration.
	(bfd_micromips_num_opcodes): Likewise.

ld/testsuite/
2011-02-25  Catherine Moore  <clm@codesourcery.com>
            Chao-ying Fu  <fu@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	* lib/ld-lib.exp (run_dump_test): Support distinct assembler
	flags for the same source named multiple times.
	* ld-mips-elf/jalx-1.s: New test source.
	* ld-mips-elf/jalx-1.d: New test output.
	* ld-mips-elf/jalx-1.ld: New test linker script.
	* ld-mips-elf/jalx-2-main.s: New test source.
	* ld-mips-elf/jalx-2-ex.s: Likewise.
	* ld-mips-elf/jalx-2-printf.s: Likewise.
	* ld-mips-elf/jalx-2.dd: New test output.
	* ld-mips-elf/jalx-2.ld: New test linker script.
	* ld-mips-elf/mips16-and-micromips.d: New test.
	* ld-mips-elf/mips-elf.exp: Run the new tests

opcodes/
2011-02-25  Chao-ying Fu  <fu@mips.com>
            Maciej W. Rozycki  <macro@codesourcery.com>

	* micromips-opc.c: New file.
	* mips-dis.c (micromips_to_32_reg_b_map): New array.
	(micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
	(micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
	(micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
	(micromips_to_32_reg_q_map): Likewise.
	(micromips_imm_b_map, micromips_imm_c_map): Likewise.
	(micromips_ase): New variable.
	(is_micromips): New function.
	(set_default_mips_dis_options): Handle microMIPS ASE.
	(print_insn_micromips): New function.
	(is_compressed_mode_p): Likewise.
	(_print_insn_mips): Handle microMIPS instructions.
	* Makefile.am (CFILES): Add micromips-opc.c.
	* configure.in (bfd_mips_arch): Add micromips-opc.lo.
	* Makefile.in: Regenerate.
	* configure: Regenerate.

	* mips-dis.c (micromips_to_32_reg_h_map): New variable.
	(micromips_to_32_reg_i_map): Likewise.
	(micromips_to_32_reg_m_map): Likewise.
	(micromips_to_32_reg_n_map): New macro.
 2011-07-24 14:20:15 +00:00
Richard Sandiford
bcd530a713 include/opcode/ 
2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips.h (INSN_TRAP): Rename to...
	(INSN_NO_DELAY_SLOT): ... this.
	(INSN_SYNC): Remove macro.

gas/
2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>

	* config/tc-mips.c (can_swap_branch_p): Adjust for the rename of
	INSN_TRAP to INSN_NO_DELAY_SLOT.  Remove the check for INSN_SYNC
	as well as explicit checks for ERET and DERET when scheduling
	branch delay slots.

opcodes/
2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-opc.c (NODS): New macro.
	(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
	(DSP_VOLA): Likewise.
	(mips_builtin_opcodes): Add NODS annotation to "deret" and
	"eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
	place of TRAP for "wait", "waiti" and "yield".
	* mips16-opc.c (NODS): New macro.
	(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
	(mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
	"restore" and "save".
 2011-07-24 14:04:51 +00:00
Maciej W. Rozycki
3eebd5eb03 gas/ 
* config/tc-mips.c (macro): Handle M_PREF_AB.

	include/opcode/
	* mips.h (M_PREF_AB): New enum value.

	opcodes/
	* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 2011-02-28 16:06:51 +00:00
Richard Sandiford
1bec78e97d include/opcode/ 
* mips.h: Update commentary after last commit.
 2010-12-18 11:28:25 +00:00