I did an experiment with importing the regex module in gnulib, and trying to
build gdb.
The first problem I ran into was that:
- regoff_t was defined as long int, and
- the address of a regoff_t variable i in ui_file_style::parse was passed
as int * to function extended_color.
Fix this by changing the types of some function parameters of functions
read_semi_number and extended_color from int * to regoff_t *.
Tested on x86_64-linux.
gdb/ChangeLog:
2021-04-13 Tom de Vries <tdevries@suse.de>
* ui-style.c (read_semi_number, extended_color): Change idx parameter
type to regoff_t *.
Replace use of %lx with %s.
gdb/ChangeLog:
2021-04-13 Luis Machado <luis.machado@linaro.org>
* rs6000-tdep.c (ppc_displaced_step_fixup): Use %s to print
hex values.
git commit b95a0a3177 changed a "return FALSE" to "continue", and
missed updating the while loop iterator.
* xcofflink.c (xcoff_link_check_ar_symbols): Update esym earlier.
NT_NETBSD_PAX was defined in commit be3b926d8d.
binutils/ChangeLog:
* readelf.c (process_netbsd_elf_note): Remove now unneeded #ifdef
check for NT_NETBSD_PAX.
bfd/
* elfnn-riscv.c (riscv_version_mismatch): Do not report the warning
when the version of input or output is RISCV_UNKNOWN_VERSION, since
the extension is added implicitly.
* elfxx-riscv.c: Updated the obsolete comments.
(RISCV_UNKNOWN_VERSION): Moved to elfxx-riscv.h.
* elfxx-riscv.h (RISCV_UNKNOWN_VERSION): Added.
Hi,
This test exercise updates to the F* and VS* registers
and verifies updates to the same. Note that the registers
overlap; the doubleword[1] portion of any VS0-VS31
register contains the F0-F31 register contents, so any updates
to one can be measured in the other.
Per a brief investigation, we see that dl_main() currently
uses some VSX instructions, so the VS* values are not
going to be zero when this testcase reaches main, where these
tests begin. The test harness does not explicitly
initialize the full VS* values, so the first test loop
that updates the F* values means our VS* values are
uninitalized and will fail the first set of checks.
This update explicitly initializes the doubleword[0] portion
of the VS* registers, to allow this test to succeed.
2021-04-12 Will Schmidt <will_schmidt@vnet.ibm.com>
gdb/testsuite/ChangeLog:
* gdb.arch/vsx-regs.exp: Initialize vs* doublewords.
Hi,
This is based on a patch originally written by Alan Modra.
Powerpc / Power10 ISA 3.1 adds prefixed instructions, which
are 8 bytes in length. This is in contrast to powerpc previously
always having 4 byte instruction length. This patch implements
changes to allow GDB to better detect prefixed instructions, and
handle single stepping across the 8 byte instructions.
Added #defines to help test for PNOP and prefix instructions.
Update ppc_displaced_step_copy_insn() to handle pnop and prefixed
instructions whem R=0 (non-pc-relative).
Updated ppc_displaced_step_fixup() to properly handle the offset
value matching the current instruction size
Updated the for-loop within ppc_deal_with_atomic_sequence() to
count instructions properly in case we have a mix of 4-byte and
8-byte instructions within the atomic_sequence_length.
Added testcase and harness to exercise pc-relative load/store
instructions with R=0.
2021-04-12 Will Schmidt <will_schmidt@vnet.ibm.com>
gdb/ChangeLog:
* rs6000-tdep.c: Add support for single-stepping of
prefixed instructions.
gdb/testsuite/ChangeLog:
* gdb.arch/powerpc-plxv-nonrel.s: Testcase using
non-relative plxv instructions.
* gdb.arch/powerpc-plxv-nonrel.exp: Testcase harness.
This addresses PR gdb/27525. The lnia and other variations
of the addpcis instruction write the value of the NIA into a target register.
If we are single-stepping across a breakpoint, the instruction is executed
from a displaced location, and thusly the written value of the PC/NIA
will be incorrect. The changes here will measure the displacement
offset, and adjust the target register value to compensate.
YYYY-MM-DD Will Schmidt <will_schmidt@vnet.ibm.com>
gdb/ChangeLog:
* rs6000-tdep.c (ppc_displaced_step_fixup): Update to handle
the addpcis/lnia instruction.
gdb/testsuite/ChangeLog:
* gdb.arch/powerpc-addpcis.exp: Testcase harness to
exercise single-stepping over subpcis,lnia,addpcis instructions
with displacement.
* gdb.arch/powerpc-addpcis.s: Testcase with stream
of addpcis/lnia/subpcis instructions.
* gdb.arch/powerpc-lnia.exp: Testcase harness to exercise
single-stepping over lnia instructions with displacement.
* gdb.arch/powerpc-lnia.s: Testcase with stream of
lnia instructions.
Inspired by the existing powerpc-power9.exp test, this is a
new test to cover the power10 instruction disassembly.
gdb/testsuite/ChangeLog:
2021-04-12 Will Schmidt <will_schmidt@vnet.ibm.com>
* gdb.arch/powerpc-power10.s: New test for instructions.
* gdb.arch/powerpc-power10.exp: Harness to run the test.
Writing to a potentially read-only source directory is not good.
* testsuite/gas/m68hc11/m68hc11.exp (gas_m68hc11_message): Don't
write to $srcdir. Use gas_host_run and read output file rather
than gas_start/gas_finish.
This patch adds a floating point 128-bit composite field to the vsx
register type. When printing the register with p/f the float128 field will
be printed as a 128-bit floating point value. A test case to verify the new
vsx register field is visible and correctly prints out the value of a 128-bit
floating point value is also added.
gdb/ChangeLog:
* rs6000-tdep.c (rs6000_builtin_type_vec128): Add t_float128 variable.
(rs6000_builtin_type_vec128): Add append_composite_type_field for
float128.
gdb/testsuite/ChangeLog:
* gdb.arch/vsx-vsr-float128.c: New test file.
* gdb.arch/vsx-vsr-float128.exp: New expect file.
The support for WinCE was removed with commit 84b300de36 ("gdbserver:
remove support for ARM/WinCE"). There is some leftover code for WinCE
support, guarded by the _WIN32_WCE macro, which I didn't know of at the
time.
I didn't remove the _WIN32_WCE references in the tests, because in
theory we still support the WinCE architecture in GDB (when debugging
remotely). So someone could run a test with that (although I'd be
really surprised).
gdb/ChangeLog:
* nat/windows-nat.c: Remove all code guarded by _WIN32_WCE.
* nat/windows-nat.h: Likewise.
gdbserver/ChangeLog:
* win32-low.cc: Remove all code guarded by _WIN32_WCE.
* win32-low.h: Likewise.
Change-Id: I7a871b897e2135dc195b10690bff2a01d9fac05a
In gdb.btrace/reconnect.exp, we test that we can disconnect and reconnect
again to a GDB session that is recording with the btrace recording format.
It does not really matter what we are recording.
The test assumed that stepping from _start will bring us into an area
without debug information. This is not correct on all systems.
Relax the expected output to also support systems where we do have debug
information for that code.
elf_backend_archive_symbol_lookup might be called when the linker hash
table has entries of type generic_link_hash_entry. This happens for
instance when running the mmix target linker testsuite where the
output is mmo but input is elf64-mmix.
* elf-bfd.h (struct elf_backend_data): Return bfd_link_hash_entry*
from elf_backend_archive_symbol_lookup.
(_bfd_elf_archive_symbol_lookup): Return bfd_link_hash_entry*.
* elf64-ppc.c (ppc64_elf_archive_symbol_lookup): Likewise. Check
we have a ppc_hash_table before accessing ppc_link_hash_entry
fields.
* elflink.c (_bfd_elf_archive_symbol_lookup): Return
bfd_link_hash_entry*.
(elf_link_add_archive_symbols): Adjust to suit.
Fix the wrong version of i-ext when expanding g-ext. This was changed by
the previous patch accidently.
bfd/
* elfxx-riscv.c (riscv_parse_std_ext): Fixed the wrong versions of
i-ext when expanding g-ext.
The linker does not care the default versions of the extensions, since
it does not have the default ISA spec setting. Therefore, linker won't
insert the implicit extensions for the input objects. But we used to
insert the i-ext as the explicit extension, even if the e-ext is set.
This causes linker to report "cannot find default versions of the ISA
extension `i'" errors when linking the input objects with e-ext.
This patch fixes the above linker problem, and also remove the confused
riscv_ext_dont_care_version function. Unless these "dont care" extensions
are set in the input architecture explicitly, otherwise we always insert
them as the implicit ones. Afterwards, let riscv_arch_str1 surpress them
not to output to the architecture string if their versions are
RISCV_UNKNOWN_VERSION.
bfd/
* elfxx-riscv.c (riscv_ext_dont_care_version): Removed.
(riscv_parse_add_subset): Always add the implicit extensions, even if
their versions are RISCV_UNKNOWN_VERSION.
(riscv_parse_std_ext): Delay to add i-ext as the implicit extension
in the riscv_parse_add_implicit_subsets. Besides, add g-ext as the
implicit extension after it has been expanded.
(riscv_parse_add_implicit_subsets): Updated.
When built on a 32-bit host without --enable-64-bit-bfd, powerpc-linux
and other 32-bit powerpc targeted binutils fail to assemble some
power10 prefixed instructions with 34-bit fields. A typical error
seen when running the testsuite is
.../gas/testsuite/gas/ppc/prefix-pcrel.s:10: Error: bignum invalid
In practice this doesn't matter for addresses: 32-bit programs don't
need or use the top 2 bits of a d34 field when calculating addresses.
However it may matter when loading or adding 64-bit constants with
paddi. A power10 processor in 32-bit mode still has 64-bit wide GPRs.
So this patch enables limited support for O_big PowerPC operands, and
corrects sign extension of 32-bit constants using X_extrabit.
* config/tc-ppc.c (insn_validate): Use uint64_t for operand values.
(md_assemble): Likewise. Handle bignum operands.
(ppc_elf_suffix): Handle O_big. Remove unnecessary input_line_pointer
check.
* expr.c: Delete unnecessary forward declarations.
(generic_bignum_to_int32): Return uint32_t.
(generic_bignum_to_int64): Return uint64_t. Compile always.
(operand): Twiddle X_extrabit for unary '~'. Set X_unsigned and
clear X_extrabit for unary '!'.
* expr.h (generic_bignum_to_int32): Declare.
(generic_bignum_to_int64): Declare.
* testsuite/gas/ppc/prefix-pcrel.s,
* testsuite/gas/ppc/prefix-pcrel.d: Add more instructions.
It's not enough to test that the output is ELF before casting
bfd_link_hash_entry to elf_link_hash_entry. Some ELF targets (d30v,
dlx, pj, s12z, xgate) use the generic linker support in bfd/linker.c
and thus their symbols are of type generic_link_hash_entry.
Not all of the places this patch touches can result in wrong accesses,
but I thought it worth ensuring that all occurrences of
elf_link_hash_entry in ld/ were obviously correct.
PR 27719
* ldlang.c (lang_mark_undefineds, undef_start_stop): Test that
the symbol hash table is the correct type before accessing
elf_link_hash_entry symbols.
* plugin.c (is_visible_from_outside): Likewise.
* emultempl/armelf.em (ld${EMULATION_NAME}_finish): Likewise.
* emultempl/solaris2.em (elf_solaris2_before_allocation): Likewise.
The original discussion is as follows,
https://github.com/riscv/riscv-isa-manual/issues/637
I never considered the prefixes may have multiple letters, like zxm.
But the ISA spec has been updated for a long time that I haven't noticed.
This patch rewrites the part of architecture parser to support parsing
the multi-letter prefixes. Besides, I also improve the parser to report
errors in details. One of the most obvious improvement is - Do not parse
the prefixed extensions according to the orders in the parse_config.
If we do so, then we used to get "unexpected ISA string at end" errors,
but the message is a little bit hard to know what is happening. I Remove
the confused message, and let riscv_parse_prefixed_ext to report the details.
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Moved forward.
(riscv_std_s_ext_strtab): Likewise.
(riscv_std_h_ext_strtab): Likewise.
(riscv_std_zxm_ext_strtab): Added for the zxm prefix.
(enum riscv_prefix_ext_class): Moved forward and renamed from
riscv_isa_ext_class. Reorder them according to the parsing order,
since the enum values are used to check the orders in the
riscv_compare_subsets.
(struct riscv_parse_prefix_config): Moved forward and renamed from
riscv_parse_config_t. Also removed the ext_valid_p field, the
related functions are replaced by riscv_valid_prefixed_ext.
(parse_config): Moved forward and updated. The more letters of the
prefix string, the more forward it must be defined. Otherwise, we
will get the wrong mapping when using strncmp in riscv_get_prefix_class.
(riscv_get_prefix_class): Moved forward. Support to parse the
multi-letter prefix, like zxm.
(riscv_known_prefixed_ext): New function, check if the prefixed
extension is supported according to the right riscv_std_*_ext_strtab.
(riscv_valid_prefixed_ext): New function, used to replace the
riscv_ext_*_valid_p functions.
(riscv_init_ext_order): Do not set the values for prefix keywords
since they may have multiple letters for now.
(riscv_compare_subsets): Set the order values of prefix keywords
to negative numbers according to the riscv_prefix_ext_class.
(riscv_parse_std_ext): Call riscv_get_prefix_class to see if we
have parsed the prefixed extensions.
(riscv_parse_prefixed_ext): Updated and removed the parameter config.
Report error when the prefix is unknown.
(riscv_parse_subset): Do not parse the prefixed extensions according
to the orders in the parse_config. Remove the confused message and
let riscv_parse_prefixed_ext to report the details.
* elfxx-riscv.h (enum riscv_isa_ext_class): Moved to elfxx-riscv.c.
(riscv_get_prefix_class): Removed to static.
gas/
* testsuite/gas/riscv/march-fail-order-x-std.d: Renamed from
march-fail-porder-x-std.d.
* testsuite/gas/riscv/march-fail-order-z-std.d: Renamed from
march-fail-porder-z-std.d.
* testsuite/gas/riscv/march-fail-order-x-z.d: Renamed from
march-fail-porder-x-z.d.
* testsuite/gas/riscv/march-fail-order-zx-std.l: Added to replace
march-fail-porder.l.
* testsuite/gas/riscv/march-fail-order-x-z.l: Likewise.
* testsuite/gas/riscv/march-fail-order-x.l: Updated.
* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
* testsuite/gas/riscv/march-fail-single-prefix-h.d: Renamed from
march-fail-single-char-h.d.
* testsuite/gas/riscv/march-fail-single-prefix-s.d: Renamed from
march-fail-single-char-s.d.
* testsuite/gas/riscv/march-fail-single-prefix-x.d: Renamed from
march-fail-single-char-x.d.
* testsuite/gas/riscv/march-fail-single-prefix-z.d: Renamed from
march-fail-single-char-z.d.
* testsuite/gas/riscv/march-fail-single-prefix-zmx.d: Added.
* testsuite/gas/riscv/march-fail-single-prefix.l: Added to replace
march-fail-single-prefix.l.
* testsuite/gas/riscv/march-fail-unknown-zxm.d: Added.
* testsuite/gas/riscv/march-fail-unknown-std.l: Updated.
* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
This fixes win32-low.cc in the same way as a recent change in
windows-nat.c did for GDB: if the lpImageName member of the load-DLL
debug event doesn't allow us to find the file name of the DLL, then
loop over all the DLLs mapped into the inferior to find the one loaded
at the same base address as given by the lpBaseOfDll member of the
debug event.
gdbserver/ChangeLog:
2021-04-11 Eli Zaretskii <eliz@gnu.org>
* win32-low.cc (win32_add_dll): New function, with body almost
identical to what win32_add_all_dlls did. Accepts one argument;
if that is non-NULL, returns the file name of the DLL that is
loaded at the base address equal to that argument, or NULL if not
found. If the argument is NULL, add all the DLLs loaded by the
inferior to the list of solibs and return NULL.
(win32_add_all_dlls): Now a thin wrapper around win32_add_dll.
(windows_nat::handle_load_dll) [!_WIN32_WCE]: If get_image_name
failed to glean the file name of the DLL, call win32_add_dll to
try harder using the lpBaseOfDll member of the load-DLL event.
This patch makes handling a DLL load at run time (using LoadLibrary)
much more reliable when its file name cannot be obtained using the
lpImageName pointer provided by the DLL load debug event. The
solution is to enumerate all the DLLs loaded by the inferior, looking
for the DLL that's loaded at base address provided by the lpBaseOfDll
pointer of the debug event. Correctly resolving the DLL file name is
important, because without that GDB doesn't record the DLL in the list
of solibs, and then later is unable to show functions in that DLL in
the backtraces, which produces corrupted and truncated backtraces.
See this thread for the problems that causes:
https://sourceware.org/pipermail/gdb-patches/2021-March/177022.html
gdb/ChangeLog:
2021-04-10 Eli Zaretskii <eliz@gnu.org>
* windows-nat.c (windows_nat::handle_load_dll): Call
windows_add_dll if get_image_name failed to glean the name of the
DLL by using the lpImageName pointer.
(windows_add_all_dlls): Now a thin wrapper around windows_add_dll.
(windows_add_dll): Now does what windows_add_all_dlls did before,
but also accepts an argument LOAD_ADDR, which, if non-NULL,
specifies the address where the DLL was loaded into the inferior,
and looks for the single DLL loaded at that address.
Similarly to commit 665af52ec2, fix a build
failure seen with an updated glibc, due to the enum/constant mismatch.
The old include file order eventually makes asm/ptrace.h get included before
sys/ptrace.h.
This patch fixes it. Seems fairly obvious and I'll push it shortly.
gdb/ChangeLog:
2021-04-09 Luis Machado <luis.machado@linaro.org>
* nat/aarch64-mte-linux-ptrace.c: Update include file order.
On a 32-bit build, I ran into the following:
sim/rx/fpu.c:789:6: error: "*((void *)&a+8)" may be used uninitialized in this function [-Werror=maybe-uninitialized]
rv = fp_implode (&a);
To silence this, just initialize the struct with 0's.
sim/rx/ChangeLog:
2021-04-09 Luis Machado <luis.machado@linaro.org>
* fpu.c (rxfp_itof): Initialize structure.
A summary of what this patch set fixes:
For instructions
STXR w0,x2,[x0]
STLXR w0,x2,[x0]
The warning we emit currently is misleading:
Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]'
Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]'
it ought to be:
Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]'
Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]'
For instructions:
ldaxp x0,x0,[x0]
ldxp x0,x0,[x0]
The warning we emit is incorrect
Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]'
Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]'
it ought to be:
Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]'
Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]'
For instructions
stlxp w0, x2, x2, [x0]
stxp w0, x2, x2, [x0]
We don't emit any warning when it ought to be:
Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]'
Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]'
gas/ChangeLog:
2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
* config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages
for LD/ST Exclusive instructions.
* testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP.
* testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
Patch 1: Fix diagnostics for exclusive load/stores and reclassify
Armv8.7-A ST/LD64 Atomics.
Following upstream pointing out some inconsistencies in diagnostics,
https://sourceware.org/pipermail/binutils/2021-February/115356.html
attached is a patch set that fixes the issues. I believe a combination
of two patches mainly contributed to these bugs:
https://sourceware.org/pipermail/binutils/2020-November/113961.htmlhttps://sourceware.org/pipermail/binutils/2018-June/103322.html
A summary of what this patch set fixes:
For instructions
STXR w0,x2,[x0]
STLXR w0,x2,[x0]
The warning we emit currently is misleading:
Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]'
Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]'
it ought to be:
Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]'
Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]'
For instructions:
ldaxp x0,x0,[x0]
ldxp x0,x0,[x0]
The warning we emit is incorrect
Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]'
Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]'
it ought to be:
Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]'
Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]'
For instructions
stlxp w0, x2, x2, [x0]
stxp w0, x2, x2, [x0]
We don't emit any warning when it ought to be:
Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]'
Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]'
For instructions:
st64bv x0, x2, [x0]
st64bv x2, x0, [x0]
We incorrectly warn when its not necessary. This is because we classify them
incorrectly as ldstexcl when it should be lse_atomics in the opcode table.
The incorrect classification makes it pick up the warnings from warning on
exclusive load/stores.
Patch 2: Reclassify Armv8.7-A ST/LD64 Atomics.
This patch reclassifies ST64B{V,V0}, LD64B as lse_atomics rather than ldstexcl
according to their encoding class as specified in the architecture. This also
has the fortunate side-effect of spurious unpredictable warnings getting
eliminated.
For eg. For instruction:
st64bv x0, x2, [x0]
We incorrectly warn when its not necessary:
Warning: unpredictable: identical transfer and status registers --`st64bv x0,x2,[x0]'
This is because we classify them incorrectly as ldstexcl when it should be
lse_atomics in the opcode table. The incorrect classification makes it pick
up the warnings from warning on exclusive load/stores. This patch fixes it
by reclassifying it and no warnings are issued for this instruction.
opcodes/ChangeLog:
2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
* aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
LD64/ST64 instructions to lse_atomic instead of ldstexcl.
This adds some annotation to Power10 pcrel instructions, displaying
the target address (ie. pc + D34 field) plus a symbol if there is one
at exactly that target address. pld from the .got or .plt will also
look up the entry and display it, symbolically if there is a dynamic
relocation on the entry.
include/
* dis-asm.h (struct disassemble_info): Add dynrelbuf and dynrelcount.
binutils/
* objdump.c (struct objdump_disasm_info): Delete dynrelbuf and
dynrelcount.
(find_symbol_for_address): Adjust for dynrelbuf and dynrelcount move.
(disassemble_section, disassemble_data): Likewise.
opcodes/
* ppc-dis.c (struct dis_private): Add "special".
(POWERPC_DIALECT): Delete. Replace uses with..
(private_data): ..this. New inline function.
(disassemble_init_powerpc): Init "special" names.
(skip_optional_operands): Add is_pcrel arg, set when detecting R
field of prefix instructions.
(bsearch_reloc, print_got_plt): New functions.
(print_insn_powerpc): For pcrel instructions, print target address
and symbol if known, and decode plt and got loads too.
gas/
* testsuite/gas/ppc/prefix-pcrel.d: Update expected output.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
* gas/testsuite/gas/ppc/vsx_32byte.d: Likewise.
ld/
* testsuite/ld-powerpc/inlinepcrel-1.d: Update expected output.
* testsuite/ld-powerpc/inlinepcrel-2.d: Likewise.
* testsuite/ld-powerpc/notoc2.d: Likewise.
* testsuite/ld-powerpc/notoc3.d: Likewise.
* testsuite/ld-powerpc/pcrelopt.d: Likewise.
* testsuite/ld-powerpc/startstop.d: Likewise.
* testsuite/ld-powerpc/tlsget.d: Likewise.
* testsuite/ld-powerpc/tlsget2.d: Likewise.
* testsuite/ld-powerpc/tlsld.d: Likewise.
* testsuite/ld-powerpc/weak1.d: Likewise.
* testsuite/ld-powerpc/weak1so.d: Likewise.
GCC gives a -Wsequence-point warning for this code in the h8300 sim.
The bug is that memory_size is both assigned and used in the same
expression. The fix is to assign after the print.
sim/h8300/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* compile.c (init_pointers): Fix sequence point warning.
This updates various parts of the sim to include missing system
headers. I made the includes unconditional, because other parts of
the tree are already doing this.
2021-04-08 Tom Tromey <tom@tromey.com>
* traps.c: Include stdlib.h.
* cris-tmpl.c: Include stdlib.h.
sim/erc32/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* func.c: Include sys/time.h.
sim/frv/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* traps.c: Include stdlib.h.
* registers.c: Include stdlib.h.
* profile.c: Include stdlib.h.
* memory.c: Include stdlib.h.
* interrupts.c: Include stdlib.h.
* frv.c: Include stdlib.h.
* cache.c: Include stdlib.h.
sim/iq2000/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* iq2000.c: Include stdlib.h.
sim/m32r/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* traps.c: Include stdlib.h.
* m32r.c: Include stdlib.h.
sim/ppc/ChangeLog
2021-04-08 Tom Tromey <tom@tromey.com>
* emul_unix.c: Include time.h.
I ran into a build failure with --enable-targets=all due to the fact that
the moxie sim expects to be able to use the dtc tool. If it isn't available,
the builds fails.
The following patch adds a prebuilt dtb file to the tree. That file is the one
that is used for installations.
The patch also enables (re-)generation of the dtb file through maintainer
mode, if it needs to be updated due to a change in the dts file.
Tested on aarch64-linux/x86_64-linux.
sim/moxie/ChangeLog:
2021-04-08 Luis Machado <luis.machado@linaro.org>
* Makefile.in (moxie-gdb.dtb): Add maintainer mode dependency.
(install-dtb): Install prebuilt dtb file.
* moxie-gdb.dtb: New prebuilt file.
The igen/dgen and opc2c tools leak their heap-allocated memory (on
purpose) at program exit, which makes AddressSanitizer fail the tool
execution. This breaks the build, as it makes the tool return a
non-zero exit code.
Fix that by disabling leak detection through the setting of that
environment variable.
I also changed the opc2c rules for m32c to go through a temporary file.
What happened is that the failing opc2c would produce an incomplete file
(probably because ASan exits the process before stdout is flushed).
This meant that further make attempts didn't try to re-create the file,
as it already existed. A "clean" was therefore necessary. This can
also happen in regular builds if the user interrupts the build (^C) in
the middle of the opc2c execution and tries to resume it. Going to a
temporary file avoids this issue.
sim/m32c/ChangeLog:
* Makefile.in: Set ASAN_OPTIONS when running opc2c.
sim/mips/ChangeLog:
* Makefile.in: Set ASAN_OPTIONS when running igen.
sim/mn10300/ChangeLog:
* Makefile.in: Set ASAN_OPTIONS when running igen.
sim/ppc/ChangeLog:
* Makefile.in: Set ASAN_OPTIONS when running igen.
sim/v850/ChangeLog:
* Makefile.in: Set ASAN_OPTIONS when running igen.
Change-Id: I00f21d4dc1aff0ef73471925d41ce7c23e83e082
The next-gen Intel Fortran compiler isn't flang-based, but emits
prologue_end in the same manner. As do the newer Intel C/C++ compilers.
This allows prologue detection based on dwarf for all newer Intel compilers.
The cut-off version was not chosen for any specific reason other than the
effort to test this.
gdb/Changelog:
2021-04-08 Felix Willgerodt <felix.willgerodt@intel.com>
* i386-tdep.c (i386_skip_prologue): Use symbol table to find the
prologue end for Intel compilers.
* amd64-tdep.c (amd64_skip_prologue): Likewise.
* producer.c (producer_is_icc_ge_19): New function.
* producer.h (producer_is_icc_ge_19): New declaration.
The main goal of this patch is to get rid of a warning for the new Fortran
compiler:
(gdb) b 9
warning: Could not recognize version of Intel Compiler in: "Intel(R) Fortran 21.0-2087b"
Breakpoint 1 at 0x4048cf: file comp.f90, line 9.
While trying to fix this I analyzed DW_AT_producer of all latest Intel
compilers for C, C++ and Fortran. They do no longer necessarily start with
"Intel (R)" nor do they follow the internal and external version number
scheme that the original patch for this check assumed. Some newer compilers
even contradict the "intermediate" digit in the old version scheme and have
the MINOR number as the second digit, even when having 3 or 4 digits overall.
Therefore I rewrote the check to consider the first MAJOR.MINOR string found
as the version number. This might not be 100% correct for some older
internal compilers, but the only current user of this function is only
checking for the major version anyway. Hence this should be reliable enough
and extendable enough going forward.
gdb/ChangeLog:
2021-04-08 Felix Willgerodt <felix.willgerodt@intel.com>
* producer.c: (producer_is_icc): Update for new version scheme.
(producer_parsing_tests): Update names and expected results.
* producer.h: (producer_is_icc): Update comment accordingly.
Exit status 77 is common (including the autotools world) to indicate
"skip this test". Add support for mapping that to "unsupported" as
that's the closest in the dejagnu world.
If the port hasn't been enabled, don't try to run its tests. Making
this dynamic simplifies the test harnesses and avoids duplicating a
bunch of target tuple checks.
