SFrame is supported for ELF only. Keep the definitions and declarations
guarded with OBJ_ELF consistently.
ChangeLog:
* gas/config/tc-aarch64.h: Guard SFrame related definitions
with OBJ_ELF.
This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Currently supported for x86_64 and aarch64 only.
[PS: Currently, the compiler has not been adapted to generate
".cfi_sections" with ".sframe" in it. The newly added command line
option of --gsframe provides an easy way to try out .sframe support
in the toolchain.]
gas interprets the CFI directives to generate DWARF-based .eh_frame
info. These internal DWARF structures are now consumed by
gen-sframe.[ch] sub-system to, in turn, create the SFrame unwind
information. These internal DWARF structures are read-only for the
purpose of SFrame unwind info generation.
SFrame unwind info generation does not impact .eh_frame unwind info
generation. Both .eh_frame and .sframe can co-exist in an ELF file,
if so desired by the user.
Recall that SFrame unwind information only contains the minimal
necessary information to generate backtraces and does not provide
information to recover all callee-saved registers. The reason being
that callee-saved registers other than FP are not needed for stack
unwinding, and hence are not included in the .sframe section.
Consequently, gen-sframe.[ch] only needs to interpret a subset of
DWARF opcodes in gas. More details follow.
[Set 1, Interpreted] The following opcodes are interpreted:
- DW_CFA_advance_loc
- DW_CFA_def_cfa
- DW_CFA_def_cfa_register
- DW_CFA_def_cfa_offset
- DW_CFA_offset
- DW_CFA_remember_state
- DW_CFA_restore_state
- DW_CFA_restore
[Set 2, Bypassed] The following opcodes are acknowledged but are not
necessary for generating SFrame unwind info:
- DW_CFA_undefined
- DW_CFA_same_value
Anything else apart from the two above-mentioned sets is skipped
altogether. This means that any function containing a CFI directive not
in Set 1 or Set 2 above, will not have any SFrame unwind information
generated for them. Holes in instructions covered by FREs of a single
FDE are not representable in the SFrame unwind format.
As few examples, following opcodes are not processed for .sframe
generation, and are skipped:
- .cfi_personality*
- .cfi_*lsda
- .cfi_escape
- .cfi_negate_ra_state
- ...
Not processing .cfi_escape, .cfi_negate_ra_state will cause SFrame
unwind information to be absent for SFrame FDEs that contain these CFI
directives, hence affecting the asynchronicity.
x86-64 and aarch64 backends need to have a few new definitions and
functions for .sframe generation. These provide gas with architecture
specific information like the SP/FP/RA register numbers and an
SFrame-specific ABI marker.
Lastly, the patch also implements an optimization for size, where
specific fragments containing SFrame FRE start address and SFrame FDE
function are fixed up. This is similar to other similar optimizations
in gas, where fragments are sized and fixed up when the associated
symbols can be resolved. This optimization is controlled by a #define
SFRAME_FRE_TYPE_SELECTION_OPT and should be easy to turn off if needed.
The optimization is on by default for both x86_64 and aarch64.
ChangeLog:
* gas/Makefile.am: Include gen-sframe.c and sframe-opt.c.
* gas/Makefile.in: Regenerated.
* gas/as.h (enum _relax_state): Add new state rs_sframe.
(sframe_estimate_size_before_relax): New function.
(sframe_relax_frag): Likewise.
(sframe_convert_frag): Likewise.
* gas/config/tc-aarch64.c (aarch64_support_sframe_p): New
definition.
(aarch64_sframe_ra_tracking_p): Likewise.
(aarch64_sframe_cfa_ra_offset): Likewise.
(aarch64_sframe_get_abi_arch): Likewise.
(md_begin): Set values of sp/fp/ra registers.
* gas/config/tc-aarch64.h (aarch64_support_sframe_p): New
declaration.
(support_sframe_p): Likewise.
(SFRAME_CFA_SP_REG): Likewise.
(SFRAME_CFA_FP_REG): Likewise.
(SFRAME_CFA_RA_REG): Likewise.
(aarch64_sframe_ra_tracking_p): Likewise.
(sframe_ra_tracking_p): Likewise.
(aarch64_sframe_cfa_ra_offset): Likewise.
(sframe_cfa_ra_offset): Likewise.
(aarch64_sframe_get_abi_arch): Likewise.
(sframe_get_abi_arch): Likewise.
* gas/config/tc-i386.c (x86_support_sframe_p): New definition.
(x86_sframe_ra_tracking_p): Likewise.
(x86_sframe_cfa_ra_offset): Likewise.
(x86_sframe_get_abi_arch): Likewise.
* gas/config/tc-i386.h (x86_support_sframe_p): New declaration.
(support_sframe_p): Likewise.
(SFRAME_CFA_SP_REG): Likewise.
(SFRAME_CFA_FP_REG): Likewise.
(x86_sframe_ra_tracking_p): Likewise.
(sframe_ra_tracking_p): Likewise.
(x86_sframe_cfa_ra_offset): Likewise.
(sframe_cfa_ra_offset): Likewise.
(x86_sframe_get_abi_arch): Likewise.
(sframe_get_abi_arch): Likewise.
* gas/config/tc-xtensa.c (unrelaxed_frag_max_size): Add case for
rs_sframe.
* gas/doc/as.texi: Add .sframe to the documentation for
.cfi_sections.
* gas/dw2gencfi.c (cfi_finish): Create a .sframe section.
* gas/dw2gencfi.h (CFI_EMIT_sframe): New definition.
* gas/write.c (cvt_frag_to_fill): Handle rs_sframe.
(relax_segment): Likewise.
* gas/gen-sframe.c: New file.
* gas/gen-sframe.h: New file.
* gas/sframe-opt.c: New file.
When --gsframe is specified, the assembler will generate a .sframe
section from the CFI directives in the assembly.
ChangeLog:
* gas/as.c (parse_args): Parse args and set flag_gen_sframe.
* gas/as.h: Introduce skeleton for --gsframe.
* gas/doc/as.texi: document --gsframe.
Without commit b66e671854, this:
.p2align 4
nop
.p2align 3
nop
results in an error when coff_frob_section attempts to pad out the
section to a 16-byte boundary. Due to miscalculating the pad pattern
repeat count, write.c:write_contents attempts to shove 16 bytes of
padding into the remaining 4 bytes of the .text section.
* config/obj-coff.c (coff_frob_section): Correct fill count.
Don't pad after errors.
Attributes which aren't used together in any single insn template can be
converted from individual booleans to a single enum, as was done for a few
other attributes before. This is more space efficient. Collect together
all attributes which express special operand constraints (and which fit
the criteria for folding).
This patch adds the assembler support for the new unwinder
directive ".pacspval" and encodes this directives with opcode
"0xb5". This opcode indicates the unwinder to use effective
vsp as modifier for PAC validation.
gas/ChangeLog:
2022-11-07 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* doc/c-arm.texi: Document directive.
* config/tc-arm.c (s_arm_unwind_pacspval): Define function.
(md_pseudo_table): Add entry for pacspval directive.
* testsuite/gas/arm/ehabi-pacbti-m.d: New test.
* testsuite/gas/arm/ehabi-pacbti-m.s: Likewise.
This tidies SEC_RELOC handling in bfd, in the process fixing a bug
with objcopy when renaming sections.
bfd/
* reloc.c (_bfd_generic_set_reloc): Set/clear SEC_RELOC depending
on reloc count.
* elf64-sparc.c (elf64_sparc_set_reloc): Likewise.
binutils/
* objcopy.c (copy_relocations_in_section): Remove now unnecessary
clearing of SEC_RELOC.
* testsuite/binutils-all/rename-section-01.d: New test.
* testsuite/binutils-all/objcopy.exp: Run it.
gas/
* write.c (size_seg): Remove unneccesary twiddle of SEC_RELOC.
(write_relocs): Likewise. Always call bfd_set_reloc.
On a testcase like
pla 8,foo@pcrel
disassembled with -Mpower10 results in
0: 00 00 10 06 pla r8,0 # 0
4: 00 00 00 39
0: R_PPC64_PCREL34 foo
but with -Mpower10 -Mraw
0: 00 00 10 06 .long 0x6100000
0: R_PPC64_PCREL34 foo
4: 00 00 00 39 addi r8,0,0
The instruction is unrecognised due to the hack we have in
extract_pcrel0 in order to disassemble paddi with RA0=0 and R=1 as
pla. I could have just added "&& !(dialect & PPC_OPCODE_RAW)" to the
condition in extract_pcrel0 under which *invalid is set, but went for
this larger patch that reorders the extended insn pla to the more
usual place before its underlying machine insn. (la is after addi
because we never disassemble to la.)
gas/
* testsuite/gas/ppc/raw.d,
* testsuite/gas/ppc/raw.s: Add pla.
opcodes/
* ppc-opc.c (extract_pcrel1): Rename from extract_pcrel0 and
invert *invalid logic.
(PCREL1): Rename from PCREL0.
(prefix_opcodes): Sort pla before paddi, adjusting R operand
for pla, paddi and psubi.
While .linefile is generally intended for gas internal use only, its use
in a source file would better not result in an internal error. Give use
of it outside of any macro(-like) construct the meaning of restoring the
original (physical) input file name.
(%dx) isn't a valid memory address in any modes. It is used as a special
memory operand for input/output port address in AT&T syntax and should
only be used with input/output instructions. Update i386_att_operand to
set i.input_output_operand to true for (%dx) and issue an error if (%dx)
is used with non-input/output instructions.
PR gas/29751
* config/tc-i386.c (_i386_insn): Add input_output_operand.
(md_assemble): Issue an error if input/output memory operand is
used with non-input/output instructions.
(i386_att_operand): Set i.input_output_operand to true for
(%dx).
* testsuite/gas/i386/inval.l: Updated.
* testsuite/gas/i386/x86-64-inval.l: Likewise.
* testsuite/gas/i386/inval.s: Add tests for invalid (%dx) usage.
* testsuite/gas/i386/x86-64-inval.s: Likewise.
Operand swapping was mistakenly suppressed when the first two operands
were immediate ones, not taking into account overall operand count. This
way EXTRQ / INSERTQ would have been accepted also with kind-of-AT&T
operand order.
For the testcase being extended, in order to not move around "GAS
LISTING" expectations, suppress pagination.
Although the encoding for scalar and fp registers is identical,
we should follow common pratice and use fp register names
when referencing fp registers.
The xtheadmemidx extension consists of indirect load/store instructions
which all load to or store from fp registers.
Let's use fp register names in this case and adjust the test cases
accordingly.
gas/
* testsuite/gas/riscv/x-thead-fmemidx-fail.l: Updated since rd need to
be float register.
* testsuite/gas/riscv/x-thead-fmemidx-fail.s: Likewise.
* testsuite/gas/riscv/x-thead-fmemidx.d: Likewise.
* testsuite/gas/riscv/x-thead-fmemidx.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated since rd need to be float register.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas uses ZSTD_compressStream2 which is only available with libzstd >=
1.4.0, leading to build errors when an older version is installed.
This patch updates the check libzstd presence to check its version is
>= 1.4.0. However, since gas seems to be the only component requiring
such a recent version this may imply that we disable ZSTD support for
all components although some would still benefit from an older
version.
I ran 'autoreconf -f' in all directories containing a configure.ac
file, using vanilla autoconf-2.69 and automake-1.15.1. I noticed
several errors from autoheader in readline, as well as warnings in
intl, but they are unrelated to this patch.
This should fix some of the buildbots.
OK for trunk?
Thanks,
Christophe
Despite that the RISC-V ISA Manual version 2.2 prohibited "RV32EF", later
versions beginning with the version 20190608-Base-Ratified removed this
restriction. Because the 'E' extension is still a draft, the author chose
to *just* remove the conflict (not checking the ISA version).
Note that, because RV32E is only used with a soft-float calling convention,
there's no valid official ABI for RV32EF. It means, even if we can assemble
a program with -march=rv32ef -mabi=ilp32e, floating-point registers are kept
in an unmanaged state (outside ABI management).
The purpose of this commit is to suppress unnecessary errors while parsing
an ISA string and/or disassembling, not to allow hard-float with RVE.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Accept RV32EF
because only older specifications disallowed it.
gas/ChangeLog:
* testsuite/gas/riscv/march-fail-rv32ef.d: Remove as not directly
prohibited.
* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
This patch is based on MULTIPLE_FRAME_SECTIONS and EH_FRAME_LINKONCE,
it allows backend to enable this feature and use '--gc-sections' simply.
* gas/dw2gencfi.h (TARGET_MULTIPLE_EH_FRAME_SECTIONS): New.
(MULTIPLE_FRAME_SECTIONS): Add TARGET_MULTIPLE_EH_FRAME_SECTIONS.
* gas/dw2gencfi.c (EH_FRAME_LINKONCE): Add TARGET_MULTIPLE_EH_FRAME_SECTIONS.
(is_now_linkonce_segment): Likewise.
(get_cfi_seg): Create relocation info between .eh_frame.* and .text.* section.
* bfd/elf-bfd.h (elf_backend_can_make_multiple_eh_frame): New.
* bfd/elfxx-target.h (elf_backend_can_make_multiple_eh_frame): Likewise.
* bfd/elflink.c (_bfd_elf_default_action_discarded): Add checking for
elf_backend_can_make_multiple_eh_frame.
Comparing the sum of the relevant .imm<N> fields against a constant imo
makes more obvious what is actually meant. It allows dropping of two
static variables, with a 3rd drop requiring two more minor adjustments
elsewhere, utilizing that "i" is zeroed first thing in md_assemble().
This also increases the chances of the compiler doing the calculations
all in registers.
Consider the case,
.option arch, rv32i
.option norelax
.option arch, +c
.byte 1
.align 2
addi a0, zero, 1
Assembler adds $d for the odd .byte, and then adds $x+arch for the
alignment. Since norelax, riscv_add_odd_padding_symbol will add the
$d and $x for the odd alignment, but accidently remove the $x+arch because
it has the same address as $d. Therefore, we will get the unexpected result
before applying this patch,
.byte 1 # $d
.align 2 # odd alignment, $xrv32ic replaced by $d + $x
After this patch, the expected result should be,
.byte 1 # $d
.align 2 # odd alignment, $xrv32ic replaced by $d + $xrv32ic
gas/
* config/tc-riscv.c (make_mapping_symbol): If we are adding mapping symbol
for odd alignment, then we probably will remove the $x+arch by accidently
when it has the same address of $d. Try to add the removed $x+arch back
after the $d rather than just $x.
(riscv_mapping_state): Updated since parameters of make_mapping_symbol are
changed.
(riscv_add_odd_padding_symbol): Likewise.
(riscv_remove_mapping_symbol): Removed and moved the code into the
riscv_check_mapping_symbols.
(riscv_check_mapping_symbols): Updated.
* testsuite/gas/riscv/mapping-dis.d: Updated and added new testcase.
* testsuite/gas/riscv/mapping-symbols.d: Likewise.
* testsuite/gas/riscv/mapping.s: Likewise.
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.
I then spotted a couple of places where there was no ';', but instead,
just a '@' character. I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.
Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator. Thus this:
nop ;@ comment
is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.
This:
nop @ comment
is a single 'nop' instruction followed by a comment. And finally,
this:
nop ; comment
is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.
Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.
The question then is how should the disassembler style the three cases
above?
As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment. But what about ';' in
the second example? Style as text? Style as a comment?
And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic? Style as text? Style as a comment?
I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.
Then, in the next commit, it's obvious what to do.
There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
Earlier tidying still missed an opportunity: There's no need for the
"anyimm" static variable. Instead of using it in the loop to mask
"allowed" (which is necessary to satisfy operand_type_or()'s assertions)
simply use "mask", requiring it to be calculated first. That way the
post-loop masking by "mask" ahead of the operand_type_all_zero() can be
dropped.
Silence GCC 12 warning on tc-i386.c:
gas/config/tc-i386.c: In function ‘md_assemble’:
gas/config/tc-i386.c:5039:16: error: too many arguments for format [-Werror=format-extra-args]
5039 | as_warn (_("only support RIP-relative address"), i.tm.name);
* config/tc-i386.c (md_assemble): Print mnemonic in RIP-relative
warning.
* estsuite/gas/i386/x86-64-prefetchi-warn.l: Updated.
Before figuring out the suppress rule of mapping symbol with architecture
(changed back to $x), always generate them at the start of the sections.
gas/
* config/tc-riscv.c (need_arch_map_symbol): Removed.
(riscv_mapping_state): Updated.
(riscv_check_mapping_symbols): Updated.
* testsuite/gas/riscv/mapping-non-arch.d: Removed.
* testsuite/gas/riscv/mapping-non-arch.s: Likewise.
We don't support instructions longer than 64-bits yet. Still, we can
modify validate_riscv_insn function to prevent unexpected behavior by
limiting the "length" of an instruction to 64-bit (or less).
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Fix function
description comment based on current spec. Limit instruction
length up to 64-bit for now. Make sure that required_bits does
not corrupt even if unsigned long long is longer than 64-bit.
