Commit Graph

3815 Commits

Author SHA1 Message Date
Jim Wilson
8ecbe595e6 Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.
sim/aarch64/
	* simulator.c (mul64hi): Shift carry left by 32.
	(smulh): Change signum to negate.  If negate, invert result, and add
	carry bit if low part of multiply result is zero.

	sim/testsuite/sim/aarch64/
	* sumov.s: Correct compare test values.
	* sumulh.s: New.
2017-03-03 13:10:45 -08:00
Jim Wilson
152e1e1bc9 Add missing smov support, and clean up existing umov support.
sim/aarch64/
	* simulator.c (do_vec_SMOV_into_scalar): New.
	(do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
	Rewritten.
	(do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
	(do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
	do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
	do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.

	sim/testsuite/sim/aarch64/
	* sumov.s: New.
2017-02-25 20:06:36 -08:00
Jim Wilson
ac189e7bf8 Add missing cnt (popcount) instruction support.
sim/aarch64/
	* simulator.c (popcount): New.
	(do_vec_CNT): New.
	(do_vec_op1): Add do_vec_CNT call.

	sim/testsuite/sim/aarch64/
	* cnt.s: New.
2017-02-25 20:04:09 -08:00
Jim Wilson
2e7e5e2890 Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.
sim/aarch64/
	* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
	with type set to input type size.
	(do_vec_xtl): Change bias from 3 to 4 for byte case.

	sim/testsuite/sim/aarch64/
	* bit.s: Change cmp immediates to account for addv bug fix.
	* cmtst.s, ldn_single.s, stn_single.s: Likewise.
	* xtl.s: New.
2017-02-19 13:16:56 -08:00
Jim Wilson
742e3a7781 Add self to aarch64 maintainers. Fix mla instruction.
sim/
	* MAINTAINTERS (aarch64): Add myself.

	sim/aarch64/
	* simulator.c (do_vec_MLA): Rewrite switch body.

	sim/testsuite/sim/aarch64/
	* mla.s: New.
2017-02-14 15:23:12 -08:00
Jim Wilson
bf25e9a0f1 Fix bit/bif instructions.
sim/aarch64/
	* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
	2.  Move test_false if inside loop.  Fix logic for computing result
	stored to vd.

	sim/testsuite/sim/aarch64
	* bit.s: New.
2017-02-14 14:35:57 -08:00
Jim Wilson
e8f42b5e36 Add ldn/stn single support, fix ldnr support.
sim/aarch64/
	* simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
	(do_vec_LDn_single, do_vec_STn_single): New.
	(do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
	loop over nregs using new var n.  Add n times size to address in loop.
	Add n to vd in loop.
	(do_vec_load_store): Add comment for instruction bit 24.  New var
	single to hold instruction bit 24.  Add new code to use single.  Move
	ldnr support inside single if statements.  Fix ldnr register counts
	inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.

	sim/testsuite/sim/aarch64/
	* ldn_single.s: New.
	* ldnr.s: New.
	* stn_single.s: New.
2017-02-14 14:31:03 -08:00
Mike Frysinger
13a590ca65 sim: use ARRAY_SIZE instead of ad-hoc sizeof calculations 2017-02-13 01:26:21 -05:00
Jim Wilson
fbf32f638c Add support for cmtst.
sim/aarch64/
	* simulator.c (do_vec_compare): Add case 0x23 for CMTST.

	sim/testsuite/sim/aarch64/
	* cmtst.s: New.
2017-01-23 17:26:53 -08:00
Jim Wilson
05b3d79d26 Fixes for addv and xtn2 instructions.
sim/aarch64/
	* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
	aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
	case 3, call HALT_UNALLOC unconditionally.
	(do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
	i + 2.  Delete if on bias, change index to i + bias * X.

	sim/testsuite/sim/aarch64/
	* addv.s: New.
	* xtn.s: New.
2017-01-17 16:11:09 -08:00
Jim Wilson
a4fb5981b7 Fix problems with the implementation of the uzp1 and uzp2 instructions.
sim/aarch64/
	* simulator.c (do_vec_UZP): Rewrite.
	sim/testsuite/sim/aarch64/
	* uzp.s: New.
2017-01-09 15:44:57 -08:00
Jim Wilson
c0386d4d54 Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.
sim/aarch64/
	* cpustate.c: Include math.h.
	(aarch64_set_FP_float): Use signbit to check for signed zero.
	(aarch64_set_FP_double): Likewise.
	* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
	(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
	args same size as third arg.
	(fmaxnm): Use isnan instead of fpclassify.
	(fminnm, dmaxnm, dminnm): Likewise.
	(do_vec_MLS): Reverse order of subtraction operands.
	(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
	aarch64_get_FP_float to get source register contents.
	(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
	DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
	DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
	(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
	raise_exception calls.

	sim/testsuite/sim/aarch64/
	* fcsel.s: New.
	* fcvtz.s: New.
	* fminnm.s: New.
	* mls.s: New.
	* mul.s: New.
2017-01-04 16:07:50 -08:00
Joel Brobecker
61baf725ec update copyright year range in GDB files
This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.

gdb/ChangeLog:

        Update copyright year range in all GDB files.
2017-01-01 10:52:34 +04:00
Jim Wilson
87903eafb0 Fix bugs with float compare and Inf operands.
sim/aarch64/
	* simulator.c (set_flags_for_float_compare): Add code to handle Inf.
	Add comment to document NaN issue.
	(set_flags_for_double_compare): Likewise.

	sim/testsuite/sim/aarch64/
	* fcmp.s: New.
2016-12-21 12:33:12 -08:00
Maciej W. Rozycki
cadf97cf20 MAINTAINERS: Add myself as a MIPS maintainer
* MAINTAINERS (Maintainers for particular sims): Add myself as
	a MIPS maintainer.
2016-12-14 22:19:08 +00:00
Jim Wilson
963201cf5d Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.
sim/aarch64
	* simulator.c (NEG, POS): Move before set_flags_for_add64.
	(set_flags_for_add64): Replace with a modified copy of
	set_flags_for_sub64.

	sim/testsuite/sim/aarch64
	* testutils.inc (pass): Move .Lpass to start.
	(fail): Move .Lfail to start.  Return 1 instead of 0.
	(start): Moved .Lpass and .Lfail to here.
	* adds.s: New.
	* fstur.s: New.
	* tbnz.s: New.
2016-12-13 08:44:31 -08:00
Jim Wilson
668650d58d Fix bugs with tbnz/tbz instructions.
sim/aarch64
	* simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
	(dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
2016-12-03 17:29:44 -08:00
Jim Wilson
88256e713c Fix typo in ChangeLog entry. 2016-12-01 09:07:55 -08:00
Jim Wilson
88ddd4a1ef Fix bug with FP stur instructions.
sim/aarch64
	* simulator.c (fsturs): Switch use of rn and st variables.
	(fsturd, fsturq): Likewise
2016-12-01 09:06:07 -08:00
Mike Frysinger
6cb2202baa sim: mips: add PR info to ChangeLog 2016-11-12 01:02:23 -05:00
Mike Frysinger
91588b3af8 sim: mips: fix dv-tx3904cpu build error
When building for mipstx39-rtems4.12 targets, some funcs use SD and CPU
implicitly.  Restore the defines for these to the local sd and cpu vars.

This was broken by the clean up in commit d47f5b30d8.

Reported-by: Joel Sherrill <joel.sherrill@oarcorp.com>
2016-11-11 01:29:21 -05:00
Mike Frysinger
e04659e860 sim: mips: fix builds for r3900 cpus due to missing check_u64 2016-11-11 01:28:36 -05:00
Mike Frysinger
333ec25d7e sim: avr: move changelog entries to subdir 2016-10-18 01:04:53 -04:00
Mike Frysinger
fa0843f502 sim: m68hc11: use standard STATIC_INLINE helper
Rather than redefine inline locally, use the common STATIC_INLINE.
2016-08-16 06:12:39 -07:00
Mike Frysinger
5357150c97 sim: unify symbol table handling
The common sim tracing code already handles loading and tracking of
symbols from the target program so that it can show symbol info in
trace/disassembly calls.  Once we touch up the trace code and add a
few API callbacks, ports don't need to do loading and searching of
symbol tables themselves anymore.
2016-08-15 07:00:11 -07:00
Mike Frysinger
6f64fd48c5 sim: m68hc11: standardize sim_cpu naming
We use "sim_cpu *cpu" in the sim code base, not "struct _sim_cpu" or
the name "proc", so clean up this sim to follow along.
2016-08-13 22:54:05 -07:00
Mike Frysinger
527aaa4a31 sim: m68hc11: fix up various prototype related warnings
A few funcs are only used locally, so mark them static to avoid warnings
due to -Wmissing-prototypes.

Some funcs cast the return value wrong, so drop them (and let void * just
work by default).

Update some prototypes to be new style.
2016-08-13 22:46:27 -07:00
Mike Frysinger
4c171e25a8 sim: cgen: constify mode_names 2016-08-13 22:38:04 -07:00
Mike Frysinger
6b97945424 sim: cgen: drop unused argv/envp definitions
The common argv/envp are used now by all ports, so drop this old
cgen fragment.
2016-08-13 13:47:27 -07:00
Mike Frysinger
474a2d9f5f sim: bfin: split out common mach/model defines into arch.h [PR sim/20438]
The current machs.h mixes common enums with Blackfin-specific defines.
This causes us troubles with header inclusion order such that we can't
drop the old SIM_CPU typedef (which is duplicated in common code).  By
splitting the two up, we can unwind this dependency chain, and drop the
old typedef.  It also fixes building with older gcc versions.
2016-08-13 12:47:11 -07:00
Nick Clifton
b14bdb3bab Undo the previous change to the aarch64 sim - exporting aarch64_step() - and instead make aarch64_run correctly process sim events.
* simulator.c (aarch64_step): Revert pervious delta.
	(aarch64_run): Call sim_events_tick after each
	instruction is simulated, and if necessary call
	sim_events_process.
	* simulator.h: Revert previous delta.
2016-08-12 11:35:32 +01:00
Nick Clifton
6a2775793d Export the single step function from the AArch64 simulator.
* interp.c (sim_create_inferior): Allow for being called with a
	NULL abfd parameter.  If a bfd is provided, initialise the sim
	with that start address.
	* simulator.c (HALT_NYI): Just print out the numeric value of the
	instruction when not tracing.
	(aarch64_step): Change from static to global.
	* simulator.h: Add a prototype for aarch64_step().
2016-08-11 15:04:40 +01:00
Alan Modra
293acfae4e Wean gdb and sim off private libbfd.h header
The major reason this header was needed, bfd_default_set_arch_mach,
has now moved to bfd.h.

gdb/
	* amd64-darwin-tdep.c: Don't include libbfd.h.
	* i386-darwin-tdep.c: Likewise.
	* rs6000-nat.c: Likewise.
	* rs6000-tdep.c: Likewise.
sim/aarch64/
	* memory.c: Don't include libbfd.h.
sim/rl78/
	* load.c: Don't include libbfd.h.
	(rl78_load): Don't use private iovec seek or read.
sim/rx/
	* load.c: Don't include libbfd.h.
	(rx_load): Don't use private iovec seek or read.
2016-07-27 09:01:45 +09:30
Nick Clifton
0c66ea4c5e Fix typo fsqrt -> sqrtf. 2016-07-21 09:23:16 +01:00
Nick Clifton
0f118bc7a6 Use fsqrt() to calculate float (rather than double) square root.
* simulator.c (fsqrts): Use fsqrt rather than sqrt.
2016-07-21 09:19:24 +01:00
Denis Chertykov
59f48f5a45 Update PC when simulate break instruction.
PR target/ 19401
	* avr/interp.c (step_once): Pass break instruction address to
	sim_engine_halt function which writes that to PC. Remove code that
	follows that function call as it is unreachable.
2016-07-19 09:47:23 +03:00
Nick Clifton
7df94786e4 Small improvements to the ARM simulator to cope with illegal binaries.
* armemu.c (Multiply64): Only issue error messages about invalid
	arguments if debugging is enabled.
	* armos.c (ARMul_OSHandleSWI): Ignore invalid flags.
2016-07-14 10:38:07 +01:00
Jim Wilson
c7be441465 Add support for simulating big-endian AArch64 binaries.
* cpustate.h: Include config.h.
	(union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
	use anonymous structs to align members.
	* simulator.c (aarch64_step): Use sim_core_read_buffer and
	endian_le2h_4 to read instruction from pc.
2016-06-30 09:10:41 +01:00
Nick Clifton
fd7ed446fb Add support for FMLA (by element) to AArch64 sim.
* simulator.c (do_FMLA_by_element): New function.
	(do_vec_op2): Call it.
2016-05-06 10:35:33 +01:00
Nick Clifton
7881f69ee9 Fix a typo in the check for SNANs in the RX simulator.
PR target/20000
	* fpu.c (check_exceptions): Fix typo checking for signalling
	NANs.
2016-04-27 12:37:11 +01:00
Nick Clifton
2cdad34c4f Add support for the --trace-decode option to the AArch64 simulator.
* simulator.c: Add TRACE_DECODE statements to all emulation
	functions.
2016-04-27 11:39:14 +01:00
Oleg Endo
93e6fe04cc Fix primary reason why the SH simulation hasn't been working on 64 bit hosts.
sim/sh/
	* interp.c (dmul): Split into dmul_s and dmul_u.  Use explicit integer
	width types and simplify implementation.
	* gencode.c (dmuls.l, dmulu.l): Use new functions dmul_s and dmul_u.
2016-04-10 11:02:47 +09:00
Oleg Endo
ba442f0f41 Move ChangeLog entries from sim/ChangeLog to sim/sh/ChangeLog. 2016-04-10 10:53:20 +09:00
Oleg Endo
417a667c4a Adjust default memory size and stack base address for SH simulator.
ld/ChangeLog:
	* sh/interp.c (sim_memory_size): Default init to 30.
	(parse_and_set_memory_size): Adjust upper bound to 31.

sim/ChangeLog:
	* sh/interp.c (sim_memory_size): Default init to 30.
	(parse_and_set_memory_size): Adjust upper bound to 31.
2016-04-09 10:24:00 +09:00
Nick Clifton
67f101eece Ignore DWARF debug information with a version of 0 - assume that it is padding.
PR 19872
bfd	* dwarf2.c (parse_comp_unit): Skip warning about unrecognised
	version number if the version is zero.

bin	* dwarf.c (display_debug_aranges): Skip warning about unrecognised
	version number if the version is zero.
2016-04-04 12:53:33 +01:00
Nick Clifton
7517e550ce Fix more bugs in AArch64 simulator.
* cpustate.c (aarch64_set_reg_s32): New function.
	(aarch64_set_reg_u32): New function.
	(aarch64_get_FP_half): Place half precision value into the correct
	slot of the union.
	(aarch64_set_FP_half): Likewise.
	* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
	aarch64_set_reg_u32.
	* memory.c (FETCH_FUNC): Cast the read value to the access type
	before converting it to the return type.  Rename to FETCH_FUNC64.
	(FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
	accesses.  Use for 32-bit memory access functions.
	* simulator.c (ldrsb_wb): Use sign extension not zero extension.
	(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
	(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
	(ldrsh_scale_ext, ldrsw_abs): Likewise.
	(ldrh32_abs): Store 32 bit value not 64-bits.
	(ldrh32_wb, ldrh32_scale_ext): Likewise.
	(do_vec_MOV_immediate): Fix computation of val.
	(do_vec_MVNI): Likewise.
	(DO_VEC_WIDENING_MUL): New macro.
	(do_vec_mull): Use new macro.
	(do_vec_mul): Use new macro.
	(do_vec_MLA): Read values before writing.
	(do_vec_xtl): Likewise.
	(do_vec_SSHL): Select correct shift value.
	(do_vec_USHL): Likewise.
	(do_scalar_UCVTF): New function.
	(do_scalar_vec): Call new function.
	(store_pair_u64): Treat reads of SP as reads of XZR.
2016-03-30 10:29:04 +01:00
Nick Clifton
ef0d8ffc45 Tidy up AArch64 simulator code.
* cpustate.c: Remove space after asterisk in function parameters.
	* decode.h (greg): Delete unused function.
	(vreg, shift, extension, scaling, writeback, condcode): Likewise.
	* simulator.c: Use INSTR macro in more places.
	(HALT_NYI): Use sim_io_eprintf in place of fprintf.
	Remove extraneous whitespace.
2016-03-29 11:34:22 +01:00
Nick Clifton
5ab6d79e70 More AArch64 simulator improvements.
* cpustate.c (aarch64_get_FP_half): New function.  Read a vector
	register as a half precision floating point number.
	(aarch64_set_FP_half): New function.  Similar, but for setting
	a half precision register.
	(aarch64_get_thread_id): New function.  Returns the value of the
	CPU's TPIDR register.
	(aarch64_get_FPCR): New function.  Returns the value of the CPU's
	floating point control register.
	(aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
	register.
	* cpustate.h: Add prototypes for new functions.
	* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
	* memory.c: Use unaligned core access functions for all memory
	reads and writes.
	* simulator.c (HALT_NYI): Generate an error message if tracing
	will not tell the user why the simulator is halting.
	(HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
	(INSTR): New time-saver macro.
	(fldrb_abs): New function.  Loads an 8-bit value using a scaled
	offset.
	(fldrh_abs): New function.  Likewise for 16-bit values.
	(do_vec_SSHL): Allow for negative shift values.
	(do_vec_USHL): Likewise.
	(do_vec_SHL): Correct computation of shift amount.
	(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
	shifts and computation of shift value.
	(clz): New function.  Counts leading zero bits.
	(do_vec_CLZ): New function.  Implements CLZ (vector).
	(do_vec_MOV_element): Call do_vec_CLZ.
	(dexSimpleFPCondCompare): Implement.
	(do_FCVT_half_to_single): New function.  Implements one of the
	FCVT operations.
	(do_FCVT_half_to_double): New function.  Likewise.
	(do_FCVT_single_to_half): New function.  Likewise.
	(do_FCVT_double_to_half): New function.  Likewise.
	(dexSimpleFPDataProc1Source): Call new FCVT functions.
	(do_scalar_SHL): Handle negative shifts.
	(do_scalar_shift): Handle SSHR.
	(do_scalar_USHL): New function.
	(do_double_add): Simplify to just performing a double precision
	add operation.  Move remaining code into...
	(do_scalar_vec): ... New function.
	(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
	functions.
	(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
	registers.
	(system_set): New function.
	(do_MSR_immediate): New function.  Stub for now.
	(do_MSR_reg): New function.  Likewise. Partially implements MSR
	instruction.
	(do_SYS): New function.  Stub for now,
	(dexSystem): Call new functions.
2016-03-23 17:37:30 +00:00
Nick Clifton
87bba7a5e0 Fix thinko in new GET_VEC_ELEMENT macro.
* cpustate.c: (GET_VEC_ELEMENT): And fix thinko using macro arguments.
2016-03-18 17:08:27 +00:00
Nick Clifton
4c0ca98e58 Fix code to check for illegal element numbers when accessing AArch64 vector registers in AArch64 sim.
* cpustate.c (GET_VEC_ELEMENT): Fix off by one error checking
	for an invalid element index.
	(SET_VEC_ELEMENT): Likewise.
2016-03-18 14:46:42 +00:00