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191 Commits

Author SHA1 Message Date
H.J. Lu
6b6b680700 x86: Add {rex} pseudo prefix 
Add {rex} pseudo prefix to generate a REX byte for integer and legacy
vector instructions if possible.  Note that this differs from the rex
prefix which generates REX prefix unconditionally.

gas/

	* config/tc-i386.c (_i386_insn): Add rex_encoding.
	(md_assemble): When i.rex_encoding is true, generate a REX byte
	if possible.
	(parse_insn): Set i.rex_encoding for {rex}.
	* doc/c-i386.texi: Document {rex}.
	* testsuite/gas/i386/x86-64-pseudos.s: Add {rex} tests.
	* testsuite/gas/i386/x86-64-pseudos.d: Updated.

opcodes/

	* i386-opc.tbl: Add {rex},
	* i386-tbl.h: Regenerated.
 2018-02-22 06:18:39 -08:00
Igor Tsimbalist
be3a8dca2d Enable Intel PCONFIG instruction. 
Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

This patch enables Intel PCONFIG instruction.

gas/
	* config/tc-i386.c (cpu_arch): Add .pconfig.
	* doc/c-i386.texi: Document .pconfig.
	* testsuite/gas/i386/i386.exp: Add PCONFIG tests.
	* testsuite/gas/i386/pconfig-intel.d: New test.
	* testsuite/gas/i386/pconfig.d: Likewise.
	* testsuite/gas/i386/pconfig.s: Likewise.
	* testsuite/gas/i386/x86-64-pconfig-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-pconfig.d: Likewise.
	* testsuite/gas/i386/x86-64-pconfig.s: Likewise.
opcodes/
	* i386-dis.c (enum): Add pconfig.
	* i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
	(cpu_flags): Add CpuPCONFIG.
	* i386-opc.h (enum): Add CpuPCONFIG.
	(i386_cpu_flags): Add cpupconfig.
	* i386-opc.tbl: Add PCONFIG instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-01-23 20:09:35 +03:00
Igor Tsimbalist
3233d7d074 Enable Intel WBNOINVD instruction. 
Intel has disclosed a set of new instructions for Icelake processor.
The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

This patch enables Intel WBNOINVD instruction.

gas/
	* config/tc-i386.c (cpu_arch): Add .wbnoinvd.
	* doc/c-i386.texi: Document .wbnoinvd.
	* testsuite/gas/i386/i386.exp: Add WBNOINVD tests.
	* testsuite/gas/i386/wbnoinvd-intel.d: New test.
	* testsuite/gas/i386/wbnoinvd.d: Likewise.
	* testsuite/gas/i386/wbnoinvd.s: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd.d: Likewise.
	* testsuite/gas/i386/x86-64-wbnoinvd.s: Likewise.
opcodes/
	* i386-dis.c (enum): Add PREFIX_0F09.
	* i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
	(cpu_flags): Add CpuWBNOINVD.
	* i386-opc.h (enum): Add CpuWBNOINVD.
	(i386_cpu_flags): Add cpuwbnoinvd.
	* i386-opc.tbl: Add WBNOINVD instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-01-23 20:05:33 +03:00
Igor Tsimbalist
d777820bf5 Replace CET bit with IBT and SHSTK bits. 
The latest specification for Intel CET technology defined two
new bits instead of previously used CET bit. These are IBT and
SHSTK bits. The patch replaces CET bit with IBT and SHSTK bits.

gas/
	* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
	(cpu_noarch): Add noibt, noshstk.
	(parse_insn): Change cpucet to cpuibt.
	* doc/c-i386.texi: Delete .cet. Add .ibt, .shstk.
	* testsuite/gas/i386/cet-ibt-inval.l: New test.
	* testsuite/gas/i386/cet-ibt-inval.s: Likewise.
	* testsuite/gas/i386/cet-shstk-inval.l: Likewise.
	* testsuite/gas/i386/cet-shstk-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-ibt-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-cet-ibt-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-shstk-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-cet-shstk-inval.s: Likewise.

opcodes/
	* i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS,
	CpuCET. Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
	CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
	(cpu_flags): Add CpuIBT, CpuSHSTK.
	* i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
	(i386_cpu_flags): Add cpuibt, cpushstk.
	* i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2018-01-17 19:48:28 +03:00
Igor Tsimbalist
888a89da7f Remove VL variants for 4FMAPS and 4VNNIW insns. 
AVX512_4FMAPS and AVX512_4VNNIW insns are marked as having AVX512VL
variants.  That is wrong as SDM doesn't define such instructions. The
patch removes these VL variants.

gas/
	* testsuite/gas/i386/avx512_4fmaps-warn.l: Change xmm to zmm.
	* testsuite/gas/i386/avx512_4fmaps-warn.s: Likewise.
	* testsuite/gas/i386/avx512_4fmaps_vl-intel.d: Delete.
	* testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Likewise.
	* testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Likewise.
	* testsuite/gas/i386/avx512_4fmaps_vl.d: Likewise.
	* testsuite/gas/i386/avx512_4fmaps_vl.s: Likewise.
	* testsuite/gas/i386/avx512_4vnniw_vl-intel.d: Likewise.
	* testsuite/gas/i386/avx512_4vnniw_vl.d: Likewise.
	* testsuite/gas/i386/avx512_4vnniw_vl.s: Likewise.
	* testsuite/gas/i386/i386.exp: Delete _vl tests for 4fmaps an
	4vnniw tests.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Delete.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Likewise.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512_4vnniw_vl-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512_4vnniw_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512_4vnniw_vl.s: Likewise.

opcodes/
	* i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW
	insns.
	* i386-tbl.h: Regenerate.
 2018-01-11 03:09:47 +03:00
Jan Beulich
cbda583ada x86: fix Disp8 handling for scalar AVX512_4FMAPS insns 
Just like their packed counterparts the memory operand is always 16
bytes wide, and the Disp8 scaling is the same for all of them. (As a
side note: I'm also surprised by there being AVX512VL variants of
these as well as the AVX512_4VNNIW ones - the SDM doesn't define any
such.)

Adjust the test cases also for the packed forms to actually live up to
their promise of testing correct Disp8 encoding.
 2018-01-10 14:53:43 +01:00
Jan Beulich
c9e9227878 x86: fix Disp8 handling for AVX512VL VPCMP*{B,W} variants 
In commit 2645e1d079 ("x86: add support for AVX-512 VPCMP*{B,W}
pseudo-ops") I screwed up the Disp8MemShift values of the AVX512VL
variants.
 2018-01-10 14:53:05 +01:00
H.J. Lu
704a705d7a x86: Properly encode vmovd with 64-bit memeory 
For historical reason, we allow movd/vmovd with 64-bit register and
memeory operands.  But for vmovd, we failed to handle 64-bit memeory
operand.  This has been gone unnoticed since AT&T syntax always treats
memory operand as 32-bit memory.  This patch properly encodes vmovd
with 64-bit memeory operands.  It also removes AVX512 vmovd with 64-bit
operands since GCC has

    case TYPE_SSEMOV:
      switch (get_attr_mode (insn))
        {
        case MODE_DI:
          /* Handle broken assemblers that require movd instead of movq.  */
          if (!HAVE_AS_IX86_INTERUNIT_MOVQ
              && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
            return "%vmovd\t{%1, %0|%0, %1}";
          return "%vmovq\t{%1, %0|%0, %1}";

and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't
generate AVX512 vmovd with 64-bit operand.

gas/

	PR gas/22681
	* testsuite/gas/i386/i386.exp: Run x86-64-movd and
	x86-64-movd-intel.
	* testsuite/gas/i386/x86-64-movd-intel.d: New file.
	* testsuite/gas/i386/x86-64-movd.d: Likewise.
	* testsuite/gas/i386/x86-64-movd.s: Likewise.

opcodes/

	PR gas/22681
	* i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
	Remove AVX512 vmovd with 64-bit operands.
	* i386-tbl.h: Regenerated.
 2018-01-08 04:37:20 -08:00
Alan Modra
219d1afa89 Update year range in copyright notice of binutils files 2018-01-03 17:49:56 +10:30
Jan Beulich
10c17abdd0 x86: fold certain AVX and AVX2 templates 
Just like for instructions in GPRs, there's no need to have separate
templates for otherwise identical insns acting on XMM or YMM registers
(or memory of the same size).
 2017-12-18 09:37:15 +01:00
Jan Beulich
1b54b8d7e4 x86: fold RegXMM/RegYMM/RegZMM into RegSIMD 
... qualified by their respective sizes, allowing to drop FirstXmm0 at
the same time.
 2017-12-18 09:36:14 +01:00
Jan Beulich
dc821c5f9a x86: replace Reg8, Reg16, Reg32, and Reg64 
Use a combination of a single new Reg bit and Byte, Word, Dword, or
Qword instead.

Besides shrinking the number of operand type bits this has the benefit
of making register handling more similar to accumulator handling (a
generic flag is being accompanied by a "size qualifier"). It requires,
however, to split a few insn templates, as it is no longer correct to
have combinations like Reg32|Reg64|Byte. This slight growth in size will
hopefully be outweighed by this change paving the road for folding a
presumably much larger number of templates later on.
 2017-12-18 09:34:00 +01:00
Jan Beulich
93b71a2666 x86: drop stray CheckRegSize uses 
They are relevant only when multiple operands permit registers:
operand_type_register_match() returns true if either operand is not a
register one. IOW

grep -i CheckRegSize i386-opc.tbl | grep -Ev "(Reg[8136]|Acc).*,.*(Reg|Acc)"

should produce no output.
 2017-12-15 09:13:54 +01:00
Jan Beulich
7ac2002247 x86: derive DispN from BaseIndex 
BaseIndex implies - with the exception of string instructions the
optional presence of a displacement. This is almost completely uniform
for all instructions (the sole exception being MPX ones, which don't
allow 16-bit addressing and hence Disp16), so there's no point in
explicitly stating this in the main opcode table. Drop those explict
specifications in favor of adding logic to i386-gen, shrinking the
table size quite a bit and hence making it more readable.

The opcodes/i386-tbl.h changes are due to a few cases where pointless
Disp* still hadn't been removed from their insns.
 2017-11-30 11:48:13 +01:00
Jan Beulich
b5014f7af2 x86: drop Vec_Disp8 
This is fully redundant with Disp8MemShift being non-zero, and hence can
be folded with normal Disp8 handling.
 2017-11-30 11:47:38 +01:00
Igor Tsimbalist
be7d1531e1 Add Disp8MemShift for AVX512 VAES instructions. 
opcodes/
	* i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
	* i386-tbl.h: Regenerate.

gas/
	* testsuite/gas/i386/avx512f_vaes-intel.d: Regenerate.
	* testsuite/gas/i386/avx512f_vaes.d: Likewise.
	* testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Likewise.
	* testsuite/gas/i386/avx512f_vaes-wig1.d: Likewise.
	* testsuite/gas/i386/avx512vl_vaes-intel.d: Likewise.
	* testsuite/gas/i386/avx512vl_vaes.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_vaes.s: Add instructions with disp8*N.
	* testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Regenerate.
	* testsuite/gas/i386/x86-64-avx512f_vaes.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Add instructions with disp8*N.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Regenerate.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Regenerate.
	* testsuite/gas/i386/x86-64-avx512vl_vaes.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Add instructions with disp8*N.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Regenerate.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Regenerate.
 2017-11-23 18:25:49 +03:00
Jan Beulich
66f1eba0b7 x86: correct UDn 
Make the assembler recognize UD0, supporting only the newer form
expecting a ModR/M byte.

Make assembler and disassembler properly emit / expect a ModR/M byte for
UD1.

For the testsuite, as arch-4 already tests all UDn, avoid producing a
huge delta for other tests using UD2B by making them use UD2 instead.
 2017-11-23 10:59:48 +01:00
Igor Tsimbalist
94b98370de Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor. 
* i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
	* i386-tbl.h: Regenerate.
 2017-11-22 17:41:04 +03:00
Igor Tsimbalist
c7478d028e Remove Vec_Disp8 from vpcompressb and vpexpandb. 
* i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
	* i386-tbl.h: Regenerate.
 2017-11-22 17:13:55 +03:00
Jan Beulich
2645e1d079 x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops 
... matching up with VPCMP*{D,Q}.
 2017-11-14 08:42:26 +01:00
Jan Beulich
df145ef656 x86: string insns don't allow displacements 
Remove the misleading indicators from the table.
 2017-11-14 08:40:48 +01:00
Jan Beulich
897e603cb9 x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should not allow q suffix 
Just like is the case for xsave{s,c}64 and xrstors64 already. I wonder
though why xsave{s,c} and xrstors don't allow for the q suffix, other
than the other insns without the "64" suffix do.
 2017-11-13 12:21:29 +01:00
Igor Tsimbalist
ee6872beb1 Enable Intel AVX512_BITALG instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_bitalg.
	(cpu_noarch): noavx512_bitalg.
	* doc/c-i386.texi: Document .avx512_bitalg, noavx512_bitalg.
	* testsuite/gas/i386/i386.exp: Add AVX512_BITALG tests.
	* testsuite/gas/i386/avx512f_bitalg-intel.d: New test.
	* testsuite/gas/i386/avx512f_bitalg.d: Likewise.
	* testsuite/gas/i386/avx512f_bitalg.s: Likewise.
	* testsuite/gas/i386/avx512vl_bitalg-intel.d: Likewise.
	* testsuite/gas/i386/avx512vl_bitalg.d: Likewise.
	* testsuite/gas/i386/avx512vl_bitalg.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_bitalg-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_bitalg.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_bitalg.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_bitalg-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_bitalg.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_bitalg.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
	(enum): Add EVEX_W_0F3854_P_2.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
	CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_BITALG.
	* i386-opc.h (enum): Add CpuAVX512_BITALG.
	(i386_cpu_flags): Add cpuavx512_bitalg..
	* i386-opc.tbl: Add Intel AVX512_BITALG instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist
8cfcb7659c Enable Intel AVX512_VNNI instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_vnni.
	(cpu_noarch): Add noavx512_vnni.
	* doc/c-i386.texi: Document .avx512_vnni.
	* testsuite/gas/i386/i386.exp: Add AVX512_VNNI tests.
	* testsuite/gas/i386/avx512vnni-intel.d: New test.
	* testsuite/gas/i386/avx512vnni.d: Likewise.
	* testsuite/gas/i386/avx512vnni.s: Likewise.
	* testsuite/gas/i386/avx512vnni_vl-intel.d: Likewise.
	* testsuite/gas/i386/avx512vnni_vl.d: Likewise.
	* testsuite/gas/i386/avx512vnni_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vnni_vl.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
	CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VNNI.
	* i386-opc.h (enum): Add CpuAVX512_VNNI.
	(i386_cpu_flags): Add cpuavx512_vnni.
	* i386-opc.tbl Add Intel AVX512_VNNI instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist
ff1982d53a Enable Intel VPCLMULQDQ instruction. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add VPCLMULQDQ.
	* doc/c-i386.texi: Document VPCLMULQDQ.
	* testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests.
	* testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto.
	* testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
	(enum): Remove VEX_LEN_0F3A44_P_2.
	(vex_len_table): Ditto.
	(enum): Remove VEX_W_0F3A44_P_2.
	(vew_w_table): Ditto.
	(prefix_table): Adjust instructions (see prefixes above).
	* i386-dis-evex.h (evex_table):
	Add new instructions (see prefixes above).
	* i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
	(bitfield_cpu_flags): Ditto.
	* i386-opc.h (enum): Ditto.
	(i386_cpu_flags): Ditto.
	(CpuUnused): Comment out to avoid zero-width field problem.
	* i386-opc.tbl (vpclmulqdq): New instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist
8dcf1fadf2 Enable Intel VAES instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add VAES.
	* doc/c-i386.texi: Document VAES.
	* testsuite/gas/i386/i386.exp: Run VAES tests.
	* testsuite/gas/i386/avx512f_vaes-intel.d: New test.
	* testsuite/gas/i386/avx512f_vaes-wig.s: Ditto.
	* testsuite/gas/i386/avx512f_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512f_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/avx512f_vaes.d: Ditto.
	* testsuite/gas/i386/avx512f_vaes.s: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-wig.s: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes.d: Ditto.
	* testsuite/gas/i386/avx512vl_vaes.s: Ditto.
	* testsuite/gas/i386/vaes-intel.d: Ditto.
	* testsuite/gas/i386/vaes.d: Ditto.
	* testsuite/gas/i386/vaes.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512f_vaes.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes-wig1.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512vl_vaes.s: Ditto.
	* testsuite/gas/i386/x86-64-vaes-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-vaes.d: Ditto.
	* testsuite/gas/i386/x86-64-vaes.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
	PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
	(enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
	VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
	(vex_len_table): Ditto.
	(enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
	VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
	(vew_w_table): Ditto.
	(prefix_table): Adjust instructions (see prefixes above).
	* i386-dis-evex.h (evex_table):
	Add new instructions (see prefixes above).
	* i386-gen.c (cpu_flag_init): Add VAES.
	(bitfield_cpu_flags): Ditto.
	* i386-opc.h (enum): Ditto.
	(i386_cpu_flags): Ditto.
	* i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2017-10-23 15:58:18 +03:00
Igor Tsimbalist
48521003d5 Enable Intel GFNI instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .gfni.
	* doc/c-i386.texi: Document .gfni.
	* testsuite/gas/i386/i386.exp: Add GFNI tests.
	* testsuite/gas/i386/avx.s: New GFNI test.
	* testsuite/gas/i386/x86-64-avx.s: Likewise.
	* testsuite/gas/i386/avx.d: Adjust.
	* testsuite/gas/i386/avx-intel.d: Likewise
	* testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise.
	* testsuite/gas/i386/avx512f_gfni-intel.d: New test.
	* testsuite/gas/i386/avx512f_gfni.d: Likewise.
	* testsuite/gas/i386/avx512f_gfni.s: Likewise.
	* testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise.
	* testsuite/gas/i386/avx512vl_gfni.d: Likewise.
	* testsuite/gas/i386/avx512vl_gfni.s: Likewise.
	* testsuite/gas/i386/gfni-intel.d: Likewise.
	* testsuite/gas/i386/gfni.d: Likewise.
	* testsuite/gas/i386/gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx_gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-avx_gfni.s: Likewise.
	* testsuite/gas/i386/x86-64-gfni-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-gfni.d: Likewise.
	* testsuite/gas/i386/x86-64-gfni.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
	PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
	PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
	(enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
	EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
	(prefix_table): Updated (see prefixes above).
	(three_byte_table): Likewise.
	(vex_w_table): Likewise.
	* i386-dis-evex.h: Likewise.
	* i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
	(cpu_flags): Add CpuGFNI.
	* i386-opc.h (enum): Add CpuGFNI.
	(i386_cpu_flags): Add cpugfni.
	* i386-opc.tbl: Add Intel GFNI instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:13 +03:00
Igor Tsimbalist
53467f5707 Enable Intel AVX512_VBMI2 instructions. 
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_vbmi2.
	(cpu_noarch): noavx512_vbmi2.
	* doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2.
	* testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests.
	* testsuite/gas/i386/avx512vbmi2-intel.d: New test.
	* testsuite/gas/i386/avx512vbmi2.d: Likewise.
	* testsuite/gas/i386/avx512vbmi2.s: Likewise.
	* testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise.
	* testsuite/gas/i386/avx512vbmi2_vl.d: Likewise.
	* testsuite/gas/i386/avx512vbmi2_vl.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise.

opcodes/

	* i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
	Define EXbScalar and EXwScalar for OP_EX.
	(enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
	PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
	PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
	PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
	(enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
	EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
	EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
	EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
	(intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
	(OP_E_memory): Likewise.
	* i386-dis-evex.h: Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
	CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VBMI2.
	* i386-opc.h (enum): Add CpuAVX512_VBMI2.
	(i386_cpu_flags): Add cpuavx512_vbmi2.
	* i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
 2017-10-23 15:58:07 +03:00
H.J. Lu
2234eee61c x86: CET v2.0: Update incssp and setssbsy 
Update x86 assembler and disassembler for CET v2.0:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

1. incsspd and incsspq are changed to take a register opeand with a
different opcode.
2. setssbsy is changed to take no opeand with a different opcode.

gas/

	* testsuite/gas/i386/cet-intel.d: Updated.
	* testsuite/gas/i386/cet.d: Likewise.
	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.d: Likewise.
	* testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests.
	* testsuite/gas/i386/x86-64-cet.s: Likewise.

opcodes/

	* i386-dis.c (RM_0FAE_REG_5): Removed.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_0): New.
	(PREFIX_MOD_3_0FAE_REG_5): Likewise.
	(prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1.  Add
	PREFIX_MOD_3_0F01_REG_5_RM_0.
	(prefix_table): Update PREFIX_MOD_0_0FAE_REG_5.  Add
	PREFIX_MOD_3_0FAE_REG_5.
	(mod_table): Update MOD_0FAE_REG_5.
	(rm_table): Update RM_0F01_REG_5.  Remove RM_0FAE_REG_5.
	* i386-opc.tbl: Update incsspd, incsspq and setssbsy.
	* i386-tbl.h: Regenerated.
 2017-06-21 08:32:51 -07:00
H.J. Lu
c2f7640243 x86: CET v2.0: Rename savessp to saveprevssp 
Replace savessp with saveprevssp for CET v2.0:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

gas/

	* testsuite/gas/i386/cet-intel.d: Updated.
	* testsuite/gas/i386/cet.d: Likewise.
	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.d: Likewise.
	* testsuite/gas/i386/cet.s: Replace savessp with saveprevssp.
	* testsuite/gas/i386/x86-64-cet.s: Likewise.

opcodes/

	* i386-dis.c (prefix_table): Replace savessp with saveprevssp.
	* i386-opc.tbl: Likewise.
	* i386-tbl.h: Regenerated.
 2017-06-21 08:30:52 -07:00
H.J. Lu
04ef582ace x86: Add NOTRACK prefix support 
For register indirect branches, NOTRACK prefix (0x3e), which is also
the DS segment register prefix, can be used to ignore the CET indirect
branch track.

gas/

	* config/tc-i386.c (REX_PREFIX): Changed to 7.
	(NOTRACK_PREFIX): New.
	(MAX_PREFIXES): Changed to 8.
	(_i386_insn): Add notrack_prefix.
	(PREFIX_GROUP): Add PREFIX_DS.
	(add_prefix): Return PREFIX_DS for DS_PREFIX_OPCODE.
	(md_assemble): Check if NOTRACK prefix is supported.
	(parse_insn): Set notrack_prefix and issue an error for
	other prefixes after NOTRACK prefix.
	* testsuite/gas/i386/i386.exp: Run tests for NOTRACK prefix.
	* testsuite/gas/i386/notrack-intel.d: New file.
	* testsuite/gas/i386/notrack.d: Likewise.
	* testsuite/gas/i386/notrack.s: Likewise.
	* testsuite/gas/i386/notrackbad.l: Likewise.
	* testsuite/gas/i386/notrackbad.s: Likewise.
	* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-notrack.d: Likewise.
	* testsuite/gas/i386/x86-64-notrack.s: Likewise.
	* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
	* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.

include/

	* include/opcode/i386.h (NOTRACK_PREFIX_OPCODE): New.

opcodes/

	* i386-dis.c (NOTRACK_Fixup): New.
	(NOTRACK): Likewise.
	(NOTRACK_PREFIX): Likewise.
	(last_active_prefix): Likewise.
	(reg_table): Use NOTRACK on indirect call and jmp.
	(ckprefix): Set last_active_prefix.
	(prefix_name): Return "notrack" for NOTRACK_PREFIX.
	* i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
	* i386-opc.h (NoTrackPrefixOk): New.
	(i386_opcode_modifier): Add notrackprefixok.
	* i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
	Add notrack.
	* i386-tbl.h: Regenerated.
 2017-05-22 11:02:58 -07:00
H.J. Lu
86fa6981e7 X86: Add pseudo prefixes to control encoding 
Many x86 instructions have more than one encodings.  Assembler picks
the default one, usually the shortest one.  Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible.  This patch adds pseudo
prefixes, {xxx}, to control instruction encoding.  The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}.  Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.

gas/

	* config/tc-i386.c (_i386_insn): Add dir_encoding and
	vec_encoding.  Remove swap_operand and need_vrex.
	(extra_symbol_chars): Add '}'.
	(md_begin): Mark '}' with LEX_BEGIN_NAME.  Allow '}' in
	mnemonic.
	(build_vex_prefix): Don't use 2-byte VEX encoding with
	{vex3}.  Check dir_encoding and load.
	(parse_insn): Check pseudo prefixes.  Set dir_encoding.
	(VEX_check_operands): Likewise.
	(match_template): Check dir_encoding and load.
	(parse_real_register): Set vec_encoding instead of need_vrex.
	(parse_register): Likewise.
	* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
	{vex2}, {vex3} and {evex}.  Remove ".s", ".d8" and ".d32"
	* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
	* testsuite/gas/i386/pseudos.d: New file.
	* testsuite/gas/i386/pseudos.s: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
	* testsuite/gas/i386/x86-64-pseudos.s: Likewise.

opcodes/

	* i386-gen.c (opcode_modifiers): Replace S with Load.
	* i386-opc.h (S): Removed.
	(Load): New.
	(i386_opcode_modifier): Replace s with load.
	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	and {evex}.  Replace S with Load.
	* i386-tbl.h: Regenerated.
 2017-03-09 09:59:00 -08:00
H.J. Lu
c1fe188b15 Use CpuCET on rdsspq 
* i386-opc.tbl: Use CpuCET on rdsspq.
	* i386-tbl.h: Regenerated.
 2017-03-09 07:43:48 -08:00
H.J. Lu
603555e563 Add support for Intel CET instructions 
Support Intel Control-flow Enforcement Technology (CET) instructions:

https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

gas/

	* config/tc-i386.c (cpu_arch): Add .cet.
	* doc/c-i386.texi: Document cet.
	* testsuite/gas/i386/cet-intel.d: New file.
	* testsuite/gas/i386/cet.d: Likewise.
	* testsuite/gas/i386/cet.s: Likewise.
	* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.d: Likewise.
	* testsuite/gas/i386/x86-64-cet.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run Intel CET tests.

opcodes/

	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	(MOD_0F1E_PREFIX_1): Likewise.
	(MOD_0F38F5_PREFIX_2): Likewise.
	(MOD_0F38F6_PREFIX_0): Likewise.
	(RM_0F1E_MOD_3_REG_7): Likewise.
	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	(PREFIX_0F1E): Likewise.
	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	(PREFIX_0F38F5): Likewise.
	(dis386_twobyte): Use PREFIX_0F1E.
	(reg_table): Add REG_0F1E_MOD_3.
	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	(three_byte_table): Use PREFIX_0F38F5.
	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	PREFIX_MOD_3_0F01_REG_5_RM_2.
	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	(cpu_flags): Add CpuCET.
	* i386-opc.h (CpuCET): New enum.
	(CpuUnused): Commented out.
	(i386_cpu_flags): Add cpucet.
	* i386-opc.tbl: Add Intel CET instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2017-03-06 15:26:37 -08:00
Jan Beulich
15c7c1d8a5 x86: fix handling of 64-bit operand size VPCMPESTR{I,M} 
Just like REX.W affects operand size of the implicit rAX/rDX inputs to
PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on
the instructions.

Similarly the disassembler needs to be adjusted to no longer require
VEX.W to be zero for the instructions to be valid, and to emit proper
suffixes.

Note, however, that this doesn't address the problem of there being no
way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it
address the problem of the many WIG instructions not getting properly
disassembled when VEX.W=1.
 2017-02-28 10:53:35 +01:00
Igor Tsimbalist
620214f742 Enable Intel AVX512_VPOPCNTDQ instructions 
gas/

2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

	* config/tc-i386.c (cpu_arch): Add .avx512_vpopcntdq.
	(cpu_noarch): Add noavx512_vpopcntdq.
	* doc/c-i386.texi: Document avx512_vpopcntdq, noavx512_vpopcntdq.
	* testsuite/gas/i386/i386.exp: Run AVX512_VPOPCNTDQ tests.
	* testsuite/gas/i386/avx512_vpopcntdqd-intel.d: New file.
	* testsuite/gas/i386/avx512_vpopcntdqd.d: Ditto.
	* testsuite/gas/i386/avx512_vpopcntdqd.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.

opcodes/

2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2017-01-12 08:44:24 -08:00
Alan Modra
2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
H.J. Lu
60227d64dd X86: Remove the .s suffix from EVEX vpextrw 
The .s suffix indicates that the instruction is encoded by swapping
2 register operands.  Since vpextrw takes an XMM register and an
integer register, the .s suffix should be ignored for EVEX vpextrw.

gas/

	PR binutils/20799
	* testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw.
	* testsuite/gas/i386/opcode-intel.d: Updated.
	* testsuite/gas/i386/opcode-suffix.d: Likewise.
	* testsuite/gas/i386/opcode.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw
	tests.
	* testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated.
	* testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise.

opcodes/

	PR binutils/20799
	* i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
	* i386-dis.c (EdqwS): Removed.
	(dqw_swap_mode): Likewise.
	(intel_operand_size): Don't check dqw_swap_mode.
	(OP_E_register): Likewise.
	(OP_E_memory): Likewise.
	(OP_G): Likewise.
	(OP_EX): Likewise.
	* i386-opc.tbl: Remove "S" from EVEX vpextrw.
	* i386-tbl.h: Regerated.
 2016-11-09 14:00:18 -08:00
H.J. Lu
7efeed176a X86: Merge AVX512F vmovq 
AVX512F vmovq doesn't support masking.  We can't swap register operand
in AVX512F vmovq with Reg64 since Reg64 != RegXMM.  This patch merges
AVX512F vmovq.

	* i386-opc.tbl: Merge AVX512F vmovq.
 2016-11-09 10:20:13 -08:00
Igor Tsimbalist
47acf0bd9f Enable Intel AVX512_4VNNIW instructions 
gas/

	* config/tc-i386.c: (cpu_arch) Add .avx512_4vnniw.
	(cpu_noarch): Add noavx512_4vnniw.
	* doc/c-i386.texi: Document avx512_4vnniw, noavx512_4vnniw.
	* testsuite/gas/i386/i386.exp: Run AVX512_4VNNIW tests.
	* testsuite/gas/i386/avx512_4vnniwd_vl-intel.d: New test.
	* testsuite/gas/i386/avx512_4vnniwd_vl.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd_vl.s: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd-intel.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd.d: Ditto.
	* testsuite/gas/i386/avx512_4vnniwd.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd_vl.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4vnniwd.s: Ditto.

opcodes/

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
	CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_4VNNIW.
	* i386-opc.h (enum): (AVX512_4VNNIW): New.
	(i386_cpu_flags): Add cpuavx512_4vnniw.
	* i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2016-11-02 12:31:25 -07:00
Igor Tsimbalist
920d2ddccb Enable Intel AVX512_4FMAPS instructions 
gas/

	* config/tc-i386.c (cpu_arch): Add .avx512_4fmaps.
	(cpu_noarch): Add noavx512_4fmaps.
	(process_operands): Handle implicit quad group.
	* doc/c-i386.texi: Document avx512_4fmaps, noavx512_4fmaps.
	* testsuite/gas/i386/i386.exp: Add AVX512_4FMAPS tests.
	* testsuite/gas/i386/avx512_4fmaps_vl-intel.d: New test.
	* testsuite/gas/i386/avx512_4fmaps_vl.d: Ditto.
	* testsuite/gas/i386/avx512_4fmaps_vl.s: Ditto.
	* testsuite/gas/i386/avx512_4fmaps-intel.d: Ditto.
	* testsuite/gas/i386/avx512_4fmaps.d: Ditto.
	* testsuite/gas/i386/avx512_4fmaps.s: Ditto.
	* testsuite/gas/i386/avx512_4fmaps-warn.l: Ditto.
	* testsuite/gas/i386/avx512_4fmaps-warn.s: Ditto.
	* testsuite/gas/i386/avx512_4fmaps_vl-warn.l: Ditto.
	* testsuite/gas/i386/avx512_4fmaps_vl-warn.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps.d: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.l: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps-warn.s: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.l: Ditto.
	* testsuite/gas/i386/x86-64-avx512_4fmaps_vl-warn.s: Ditto.

opcodes/

	* i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
	PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
	CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_4FMAPS.
	(opcode_modifiers): Add ImplicitQuadGroup modifier.
	* i386-opc.h (AVX512_4FMAP): New.
	(i386_cpu_flags): Add cpuavx512_4fmaps.
	(ImplicitQuadGroup): New.
	(i386_opcode_modifier): Add implicitquadgroup.
	* i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.
 2016-11-02 12:25:34 -07:00
H.J. Lu
b5cefccad8 X86: Remove pcommit instruction 
Remove x86 pcommit instruction support, which has been deprecated:

https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction

gas/

	* config/tc-i386.c (cpu_arch): Remove .pcommit.
	* doc/c-i386.texi: Likewise.
	* testsuite/gas/i386/i386.exp: Remove pcommit tests.
	* testsuite/gas/i386/pcommit-intel.d: Removed.
	* testsuite/gas/i386/pcommit.d: Likewise.
	* testsuite/gas/i386/pcommit.s: Likewise.
	* testsuite/gas/i386/x86-64-pcommit-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-pcommit.d: Likewise.
	* testsuite/gas/i386/x86-64-pcommit.s: Likewise.

opcodes/

	* i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
	(prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
	(rm_table): Update the RM_0FAE_REG_7 entry.
	* i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
	(cpu_flags): Remove CpuPCOMMIT.
	* i386-opc.h (CpuPCOMMIT): Removed.
	(i386_cpu_flags): Remove cpupcommit.
	* i386-opc.tbl: Remove pcommit.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2016-10-21 12:16:32 -07:00
H.J. Lu
6b40c46231 X86: Add ptwrite instruction 
Implement ptwrite instruction defined in Intel64 and IA-32 Architectures
Software Developer’s Manual, June 2016.

gas/

	* config/tc-i386.c (cpu_arch): Add .ptwrite.
	* doc/c-i386.texi: Document ptwrite and .ptwrite.
	* testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel,
	x86-64-ptwrite and x86-64-ptwrite-intel.
	* testsuite/gas/i386/ptwrite-intel.d: New file.
	* testsuite/gas/i386/ptwrite.d: Likewise.
	* testsuite/gas/i386/ptwrite.s: Likewise.
	* testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-ptwrite.d: Likewise.
	* testsuite/gas/i386/x86-64-ptwrite.s: Likewise.

opcodes/

	* i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
	(PREFIX_MOD_3_0FAE_REG_4): Likewise.
	(prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
	PREFIX_MOD_3_0FAE_REG_4.
	(mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
	PREFIX_MOD_3_0FAE_REG_4.
	* i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
	(cpu_flags): Add CpuPTWRITE.
	* i386-opc.h (CpuPTWRITE): New.
	(i386_cpu_flags): Add cpuptwrite.
	* i386-opc.tbl: Add ptwrite instruction.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2016-08-24 15:29:39 -07:00
Jan Beulich
c07315e0c6 x86: allow suffix-less movzw and 64-bit movzb 
... just like is already the case for 16- and 32-bit movzb: I can't see
why omitting suffixes on this (and movs{b,w,l}) is not allowed, when it
is allowed for all other instructions where the suffix is redundant
with (one of) the operands.
 2016-07-01 09:01:41 +02:00
Jan Beulich
9243100aef x86: remove stray instruction attributes 
- with Cpu64 Disp16 makes no sense for memory operands
- with CpuNo64 Disp32S makes no sense
- non-64-bit lgdt doesn't allow 10-byte operands
 2016-07-01 08:57:21 +02:00
Jan Beulich
8325cc6398 x86/Intel: fix operand checking for MOVSD 
The dual purpose mnemonic (string move vs scalar double move) breaks
the assumption that the isstring flag would be set on both the first
and last entry in the current set of templates, which results in bogus
or missing diagnostics for the string move variant of the mnemonic.
Short of mostly rewriting i386_index_check() and its interaction with
the rest of the code, simply shrink the template set to just string
instructions when encountering the second memory operand, and run
i386_index_check() a second time for the first memory operand after
that reduction.
 2016-07-01 08:56:13 +02:00
H.J. Lu
07f5af7d3c Handle indirect branches for AMD64 and Intel64 
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode.
AMD64 supports indirect branches with 16-bit address via the data size
prefix while the data size prefix is ignored by Intel64.

gas/

	PR binutis/18386
	* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
	* testsuite/gas/i386/x86-64-branch.d: Updated.
	* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
	* testsuite/gas/i386/x86-64-branch-4.l: New file.
	* testsuite/gas/i386/x86-64-branch-4.s: Likewise.

opcodes/

	PR binutis/18386
	* i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
	(indir_v_mode): New.
	Add comments for '&'.
	(reg_table): Replace "{T|}" with "{&|}" on call and jmp.
	(putop): Handle '&'.
	(intel_operand_size): Handle indir_v_mode.
	(OP_E_register): Likewise.
	* i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
	64-bit indirect call/jmp for AMD64.
	* i386-tbl.h: Regenerated
 2016-06-03 15:55:29 -07:00
H.J. Lu
e92bae6260 Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 
AMD64 vs CpuIntel64 ISA should be handled similar as AT&T vs Intel
syntax.  Since cpu_flags isn't sorted by position, we need to check
the whole cpu_flags array for the maximum position when verifying
CpuMax.

gas/

	PR gas/20154
	* config/tc-i386.c (cpu_flags_match): Don't set cpuamd64 nor
	cpuintel64.
	(match_template): Check Intel64/AMD64 ISA.

opcodes/

	PR gas/20154
	* i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
	(opcode_modifiers): Add AMD64 and Intel64.
	(main): Properly verify CpuMax.
	* i386-opc.h (CpuAMD64): Removed.
	(CpuIntel64): Likewise.
	(CpuMax): Set to CpuNo64.
	(i386_cpu_flags): Remove cpuamd64 and cpuintel64.
	(AMD64): New.
	(Intel64): Likewise.
	(i386_opcode_modifier): Add amd64 and intel64.
	(i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
	on call and jmp.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2016-05-27 08:03:17 -07:00
Alexander Fomin
8bc526963e Enable Intel RDPID instruction. 
This patch enables Intel RDPID instruction described in Intel64 and
IA-32 Architectures Software Developer's Manual, April 2016.

gas/

	* config/tc-i386.c (cpu_arch): Add RDPID.
	* doc/c-i386.texi: Document RDPID.

gas/testsuite/

	* gas/i386/i386.exp: Run RDPID tests.
	* gas/i386/prefix.d: Adjust.
	* gas/i386/rdpid.s: New test.
	* gas/i386/rdpid.d: Ditto.
	* gas/i386/rdpid-intel.d: Ditto.
	* gas/i386/x86-64-rdpid.s: Ditto.
	* gas/i386/x86-64-rdpid.d: Ditto.
	* gas/i386/x86-64-rdpid-intel.d: Ditto.

opcodes/

	* i386-dis.c (prefix_table): Add RDPID instruction.
	* i386-gen.c (cpu_flag_init): Add RDPID flag.
	(cpu_flags): Add RDPID bitfield.
	* i386-opc.h (enum): Add RDPID element.
	(i386_cpu_flags): Add RDPID field.
	* i386-opc.tbl: Add RDPID instruction.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Regenerate.
 2016-05-10 21:38:39 +03:00
Alan Modra
6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30