Use long NOPs for Intel Core processors since they are faster than
multiple NOPs. Don't use them for 64-bit processors by default since
Intel Atom processors can only decode 4 prefixes in 1 cycle.
* config/tc-i386.c (alt64_9): New.
(alt64_10): Likewise.
(alt64_11): Likewise.
(alt64_12): Likewise.
(alt64_13): Likewise.
(alt64_14): Likewise.
(alt64_15): Likewise.
(alt64_patt): Likewise.
(i386_generate_nops): Use alt64_patt for Intel Core processors
in 64-bit mode.
* testsuite/gas/i386/x86-64-nops-1-core2.d: Expect long NOPs.
* testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Replace
../x86-64-nops-1.d with ../x86-64-nops-1-core2.d.
* testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Replace
../x86-64-nops-4.d with ../x86-64-nops-4-core2.d.
There are two state propagation functions in SCFI machinery - forward
and backward flow. The patch addresses two issues:
- In forward_flow_scfi_state (), the state being compared in forward flow
must be that at the exit of a prev bb and that at the entry of the
next bb. The variable holding the state to be compared was
previously (erroneously) stale.
- In cmp_scfi_state (), the assumption that two different control
flows, leading to the same basic block, cannot have a mismatched
notion of CFA base register, is not true. Remove the assertion and
instead return err if mismatch.
Fixing these issues helps correctly synthesize CFI, when previously
SCFI was erroring out for an otherwise valid input asm.
gas/
* scfi.c (cmp_scfi_state): Remove assertion and return mismatch
in return value as applicable.
(forward_flow_scfi_state): Update state object to be the same as
the exit state of the prev bb before comparing.
gas/testsuite/
* gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
* gas/scfi/x86_64/scfi-cfg-5.d: New test.
* gas/scfi/x86_64/scfi-cfg-5.l: New test.
* gas/scfi/x86_64/scfi-cfg-5.s: New test.
A GCFG (ginsn control flow graph) is created for SCFI purposes in GAS.
The existing GCFG creation process was ignoring some paths.
add_bb_at_ginsn () is a recursive function which should return the root
of the added basic blocks. This property was being violated in some
traversals, e.g., where a taken path involving a sequence of a few basic
blocks eventually culminated in a GINSN_TYPE_RETURN instruction. This
patch fixes the issue by keeping an explicit variable root_bb to
memorize the bb to be returned.
Next, find_or_make_bb () must either create or find the bb with the
first ginsn as the provided ginsn. Add a few assertions to ensure
health of the cfg creation process.
Note that the testcase, in its current shape, is not fit for catching
regressions for the issue at hand. Although the testcase does exercise
the updated code path, the testcase passes even without the current fix,
because the added edge in this specific testcase does not alter the
synthesized CFI. (The missing edge is the fallthrough edge of the
conditional branch "jne .L13" in the testcase.)
Using a manual gcfg_print (), one can see the missing edge without the
fix. Lets keep the testcase for now, until there is a better way to
test the GCFG for this issue (e.g., either by dumping the GCFG in
textual format, or a case when the missing edge does cause wrong
synthesized CFI).
gas/
* ginsn.c (bb_add_edge): Fix a code comment.
(find_bb): Likewise.
(find_or_make_bb): Add new assertions to ensure health of cfg
creation process.
(add_bb_at_ginsn): Keep reference to the root_bb and return it.
gas/testsuite/
* gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
* gas/scfi/x86_64/scfi-cfg-4.d: New test.
* gas/scfi/x86_64/scfi-cfg-4.l: New test.
* gas/scfi/x86_64/scfi-cfg-4.s: New test.
This patch fixes the disassembly of vq[r]shr[u]n insns so that the
shift immediate is properly decoded. See the description of the
previous patch for an example of the incorrect disassembly.
As part of this patch we also fix the mve-vqrshrn.d test which was
testing for the incorrect disassembly of the immediates. The
disassembly now matches the assembled instructions in that test.
Finally we add an mve-vqshrn test which tests the non-rounding variants
of those insns, whose encoding we fixed with the previous patch in this
series.
Support zcmp extension push/pop/popret and popret zero instructions.
The `reg_list' is a list containing 1 to 13 registers, we can use:
"{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}"
to present this feature.
Passed gcc/binutils regressions of riscv-gnu-toolchain.
Most of work was finished by Sinan Lin.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp.
(riscv_supported_std_z_ext): Added zcmp with version 1.0.
(riscv_parse_check_conflicts): Zcmp conflicts with d/zcd.
(riscv_multi_subset_supports): Handle zcmp.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* config/tc-riscv.c (regno_to_reg_list): New function, used to map
register to reg_list number.
(reglist_lookup): Called reglist_lookup_internal. Return false if
reg_list number is zero, which is an invalid value.
(reglist_lookup_internal): Parse register list, and return the last
register by regno_to_reg_list.
(validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/march-help.l: Updated.
* testsuite/gas/riscv/zcmp-push-pop-fail.d: New test.
* testsuite/gas/riscv/zcmp-push-pop-fail.l: New test.
* testsuite/gas/riscv/zcmp-push-pop-fail.s: New test.
* testsuite/gas/riscv/zcmp-push-pop.d: New test.
* testsuite/gas/riscv/zcmp-push-pop.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp.
(MATCH/MASK_CM_POP): Ditto.
(MATCH/MASK_CM_POPRET): Ditto.
(MATCH/MASK_CM_POPRETZ): Ditto.
(DECLARE_INSN): New declarations for zcmp.
* opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm
operand for zcmp.
(OP_MASK_REG_LIST): Handle operand for zcmp register list.
(OP_SH_REG_LIST): Ditto.
(ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base.
(X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers.
(enum riscv_insn_class): Added INSN_CLASS_ZCMP.
(extern riscv_get_sp_base): Added.
opcodes/ChangeLog:
* riscv-dis.c (print_reg_list): New function, used to get zcmp
reg_list field.
(riscv_get_spimm): New function, used to get zcmp sp adjustment
immediate.
(print_insn_args): Handle new operands for zcmp.
* riscv-opc.c (riscv_get_sp_base): New function, used by gas and
objdump. Get sp base adjustment.
(riscv_opcodes): Added zcmp instructions.
This patch is based on APX NF patch and also adds test cases for Checking 64-bit insns not sizeable through
register operands with evex.
gas/ChangeLog:
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Added no-egpr testcases for movbe.
* testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Added tests.
* testsuite/gas/i386/noreg64-evex.d: New test.
* testsuite/gas/i386/noreg64-evex.e: Ditto.
* testsuite/gas/i386/noreg64-evex.s: Ditto.
* testsuite/gas/i386/x86-64-apx_f-evex.d: Ditto.
* testsuite/gas/i386/x86-64-apx_f-evex.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex.h: Added %ME to movbe.
* i386-dis.c : Added %XE to evex_from_vex instructions to output {evex}.
(struct dis386): New %ME.
(putop): Handle %ME and output {evex} for evex_from_legacy instructions.
* Return early when the instruction name is (bad).
For the case when NDD and NF are both 0 in evex-promoted format,
we will fully support and test it in another patch.
gas/ChangeLog:
* NEWS: Support Intel APX NF.
* config/tc-i386.c (enum i386_error): Add unsupported_nf.
(struct _i386_insn): Add has_nf.
(is_apx_evex_encoding): Ditto.
(build_apx_evex_prefix): Encode the NF bit.
(md_assemble): Handle unsupported_nf.
(parse_insn): Handle Prefix_NF and report bad for illegal combination.
(can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf.
(match_template): Support D for APX_F insns and check NF support.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
* testsuite/gas/i386/x86-64-apx-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add apx nf tests.
* testsuite/gas/i386/x86-64-apx-nf-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-nf.d: Ditto.
* testsuite/gas/i386/x86-64-apx-nf.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex.h: Add %NF to the instructions that support APX NF and
add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table.
* i386-dis-evex-reg.h: Ditto.
* i386-dis.c (struct instr_info): Add nf.
(struct dis386): Add "NF" for EVEX.NF.
(get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case.
(print_insn): Handle ins.vex.nf.
(putop): Handle "%NF".
* i386-opc.h (Prefix_NF): New.
* i386-opc.tbl: Added new entries to support full APX NF instructions.
* i386-mnem.h: Regenerated.
* i386-tbl.h: Regenerated.
Ignore .align if it is at the start of a section and the alignment
can be divided by the section alignment, the section alignment
can ensure this .align has a correct alignment.
To represent the first and third expression of .align, R_LARCH_ALIGN need to
associate with a symbol. We define a local symbol for R_LARCH_AGLIN.
But if the section of the local symbol is discarded, it may result in
a undefined symbol error.
Instead, we use the section name symbols, and this does not need to
add extra symbols.
During partial linking (ld -r), if the symbol associated with a relocation is
STT_SECTION type, the addend of relocation needs to add the section output
offset. We prevent it for R_LARCH_ALIGN.
The elf_backend_data.rela_normal only can set all relocations of a target to
rela_normal. Add a new function is_rela_normal to elf_backend_data, it can
set part of relocations to rela_normal.
The ginsn infrastructure in GAS includes the ability to create a GCFG
(ginsn CFG). A GCFG is currently used for SCFI passes.
This patch fixes the following invalid assumptions / code blocks:
- The function ginsn_direct_local_jump_p () was erroneously _not_
checking whether the symbol is locally defined (i.e., within the
scope of the code block for which GCFG is desired). Fix the code
to do so.
- Similarly, the GCFG creation code, in gcfg_build () itself had an
assumption that a GINSN_TYPE_JUMP to a non-local symbol will not be
seen. The latter can indeed be seen, and in fact, needs to be treated
the same way as an exit from the function in terms of control-flow.
gas/
* ginsn.c (ginsn_direct_local_jump_p): Check if the symbol
is local to the code block or function being assembled.
(add_bb_at_ginsn): Remove buggy assumption.
(frch_ginsn_data_append): Direct jmps do not disqualify a stream
of ginsns from GCFG creation.
gas/testsuite/
* gas/scfi/x86_64/scfi-cfg-3.d: New test.
* gas/scfi/x86_64/scfi-cfg-3.l: New test.
* gas/scfi/x86_64/scfi-cfg-3.s: New test.
* gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
1) Without -msse2avx we unconditionally honor REX.W. Hence we ought to
also do so with -msse2avx, converting to VEX.W.
2) {rex} doesn't prevent conversion to VEX encodings. Thus {rex2}
shouldn't either.
I don't view it as sensible to be more lax when it comes to references
to (uses of) such labels compared to their definition: The latter has
been limited to decimal numerics, while the former permitted any radix.
Beyond that leading zeroes on such labels aren't helpful either. Imo
labels and their use sites would better match literally, to avoid
confusion.
As it turns out, one z80 testcase actually had such an odd use of labels
where definition and use don't match in spelling. That testcase is being
adjusted accordingly.
While there also adjust a comment on a local variable in
integer_constant().
For one 0afc614c99 ("x86: Warn .insn instruction with length > 15
bytes") introduced a .insn use involving a slash; such tests need to
have --divide passed to gas.
And then 5bc71c2a6b ("x86-64: Add R_X86_64_CODE_6_GOTTPOFF") broke
BFD_RELOC_X86_64_GOTTPOFF conversion to R_X86_64_CODE_4_GOTTPOFF, by
adding respective code in a section guarded by
generate_relax_relocations (the case of that not being required there
was limited to 32-bit object files). Re-arrange that block of code to
check generate_relax_relocations later.
This relaxation is effective for both macro instructions (call36, tail36)
and explicit relocation instructions (pcaddu18i + jirl).
call36 f -> bl f
R_LARCH_CALL36 -> R_LARCH_B26
tail36 $t0, f -> b f
R_LARCH_CALL36 -> R_LARCH_B26
The following instructions are added in this patch:
- ADDPT (predicated): Add checked pointer vectors (predicated).
- ADDPT (unpredicated): Add checked pointer vectors (unpredicated).
- SUBPT (predicated): Subtract checked pointer vectors (predicated).
- SUBPT (unpredicated): Subtract checked pointer vectors (unpredicated).
- MADPT: Multiply-add checked pointer vectors, writing multiplicand
- MLAPT: Multiply-add checked pointer vectors, writing addend
These instructions are part of Checked Pointer Arithmetic extension
and are enabled when both CPA and SVE are enabled. To achieve this,
both flag "+sve" and "+cpa" should be active.
This patch adds assembler and disassembler support for these instructions
with relevant checks. Tests are included as well.
Regression tested on the aarch64-none-linux-gnu target and no regressions
have been found.
The following instructions are added in this patch:
- ADDPT and SUBPT - Add/Subtract checked pointer
- MADDPT and MSUBPT - Multiply Add/Subtract checked pointer
These instructions are part of Checked Pointer Arithmetic extension.
This patch adds assembler and disassembler support for these instructions
with relevant checks. Tests are included as well.
A new flag "+cpa" added to documentation. This flag enables CPA extension.
Regression tested on the aarch64-none-linux-gnu target and no regressions
have been found.
Except for bfml{a,s} their 1st and 3rd operands need to match - pass
the TIED macro argument accordingly. While doing that also slightly
re-arrange table entries, such that all predicated insns are close
together.
At the same time change the existing test source to actually use non-
matching operands for the respective bfml{a,s} forms.
Their index is in bits 19, 20, and 22. Bit 11 in particular is already
set in the base opcode. Note also how disassembler output didn't match
assembler input in the respective testcase.
Irrespective of the encoding being EVEX, the usable SIMD register range
continues to be limited to %xmm0-%xmm15. Enforce this in gas (but
continue to generate code, as in principle we know how to encode
things) and recognize/flag the case in the disassembler.
Oddly enough wrong forms were actually used in the testsuite (register-
only forms are then really meaningless to test here, and are hence
dropped instead of adjusted).
Convert the POP2 test that needs touching anyway (due to a bad ModR/M
byte having been chosen) to .insn.
Use -march=help for gas to print all supported extensions and versions.
Here is part of the output of `as -march=help`:
All available -march extensions for RISC-V:
e 1.9
i 2.1, 2.0
m 2.0
a 2.1, 2.0
f 2.2, 2.0
d 2.2, 2.0
q 2.2, 2.0
c 2.0
v 1.0
h 1.0
zicbom 1.0
zicbop 1.0
...
This patch assumes that the supported extensions with the same versions
are listed together. For example:
static struct riscv_supported_ext riscv_supported_std_ext[] =
{
...
{"i", ISA_SPEC_CLASS_20191213, 2, 1, 0 },
{"i", ISA_SPEC_CLASS_20190608, 2, 1, 0 },
{"i", ISA_SPEC_CLASS_2P2, 2, 0, 0 },
...
};
For the "i" extension, 2.1.0 with different spec class are listed together.
This patch records the previous printed extension and version. If the
current extension and version are the same as the previous one, skip
printing.
bfd/
* elfxx-riscv.c (riscv_print_extensions): New function. Print
available extensions and versions.
* elfxx-riscv.h (riscv_print_extensions): New declaration.
gas/
* gas/config/tc-riscv.c (md_parse_option): Parse 'help' keyword in
-march option to print available extensions and versions.
* testsuite/gas/riscv/march-help.l: New testcase for -march=help.
* testsuite/gas/riscv/riscv.exp: Updated.
Currently, gas will exit immediately and report an error when
it sees illegal operands, and will not process the remaining
instructions. Replace as_fatal with as_bad to check for all
illegal operands.
Add test cases for illegal operands of some instructions.
* After adding the old LE relax, all old LE relocations will have
an R_LARCH_RELAX relocation. Fix the gas test case failure caused
by the implementation of the old LE relax.
* loongarch64-elf does not support pie and -z norelro options,
removed in test files.
Some of these have no explicit %xmm operand(s), yet they still act SSE-
like (in leaveing bits 128 and up untouched). Hence they want similarly
diagnosing, if that was asked for.
Provide expected operand type in s390-specific assembler operand parsing
error message:
"error: operand <operand-number>: missing <operand-type> operand"
With <operand-type> being one of:
- base register
- displacement
- [vector] index register
- length
- access register
- control register
- floating-point register
- general-purpose register
- vector register
- [un]signed number
gas/
* config/tc-s390.c: Provide missing operand type in error
message.
* testsuite/gas/s390/zarch-base-index-0-err.l: Update test case
result validation patterns to operand number in operand syntax
error messages.
* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Prepend the operand number "operand %d:" to the s390-specific assembler
operand parsing warning and error messages.
While at it reword the custom operand out of range error message text to
be closer to the one used by as_bad_value_out_of_range(). Additionally
reword the invalid FPR pair warning message to make it nicer.
gas/
* config/tc-s390.c: Print operand number in error messages.
* testsuite/gas/s390/zarch-base-index-0-err.l: Update test case
verification patterns to accept syntax error messages now
containing the operand number.
* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.
* testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise.
* testsuite/gas/s390/zarch-z9-109-err.l: Likewise.
* testsuite/gas/s390/zarch-z900-err.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
The base register operand B may be omitted in D(B) by coding D and in
D(L,B) by coding D(L). The index register operand X may be omitted in
D(X,B) by coding D(B) or explicitly omitted by coding D(,B). In both
cases the omitted base register operand value defaults to zero.
Allow to explicitly omit the base register operand B in D(X,B) and
D(L,B) by coding D(X,) and D(L,). Default the omitted base register
operand value to zero.
gas/
* config/tc-s390.c: Allow to explicitly omit the base register
operand in assembly.
* NEWS: Mention that the base register now may be omitted on
s390.
* gas/testsuite/gas/s390/zarch-base-index-0.s: Update test cases
for change to allow to explicitly omit the base register
operand in assembly.
* gas/testsuite/gas/s390/zarch-base-index-0.d: Likewise.
* gas/testsuite/gas/s390/zarch-base-index-0-err.s: Likewise.
* gas/testsuite/gas/s390/zarch-base-index-0-err.l: Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index.s: Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index-err.s:
Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index-err.l:
Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Base and index register 0 have no effect in address computation:
"A value of zero in the B [base] or X [index] field specifies that no
base or index is to be applied, and, thus, general register 0 cannot be
designated as containing a base address or index."
IBM z/Architecture Principles of Operation [1], chapter "Organization",
section "General Registers".
Index register 0 is omitted in the s390 disassembly. Base register 0 is
omitted in D(B), D(L,B) and D(X,B) - the latter only if the index
register is zero.
To make it more apparent print base register 0 as "0" instead of "%r0",
whenever it would still be printed in the disassembly.
[1]: IBM z/Architecture Principles of Operation, SA22-7832-13,
https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
opcodes/
* s390-dis.c: Print base register 0 as "0" in disassembly.
binutils/
* NEWS: Mention base register 0 now being printed as "0" in s390
disassembly.
gas/
* testsuite/gas/s390/zarch-base-index-0.d: Update test case
output verification patterns to accept "0" as base base
register due to disassembler output format change.
* gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Print a warning message when the register type of a specified register
name does not match with the operand's register type:
operand {#}: expected {access|control|floating-point|general|vector}
register name [as {base|index} register]
Introduce a s390-specific assembler option "warn-regtype-mismatch"
with the values "strict", "relaxed", and "no" as well as an option
"no-warn-regtype-mismatch" which control whether the assembler
performs register name type checks and generates above warning messages.
warn-regtype-mismatch=strict:
Perform strict register name type checks.
warn-regtype-mismatch=relaxed:
Perform relaxed register name type checks, which allow floating-point
register (FPR) names %f0 to %f15 to be specified as argument to vector
register (VR) operands and vector register (VR) names %v0 to %v15 to
be specified as argument to floating-point register (FPR) operands.
This is acceptable as the FPRs are embedded into the lower halves of
the VRs. Make "relaxed" the default, as GCC generates assembler code
using FPR and VR interchangeably, which would cause assembler warnings
to be generated with "strict".
warn-regtype-mismatch=no:
no-warn-regtype-mismatch:
Disable any register name type checks.
Tag .insn pseudo mnemonics as such, to skip register name type checks
on those. They need to be skipped, as there do not exist .insn pseudo
mnemonics for every possible operand register type combination. Keep
track of the currently parsed operand number to provide it as reference
in warning messages.
To verify that the introduction of this change does not unnecessarily
affect the compilation of existing code the GNU Binutils, GNU C Library,
and Linux Kernel have been build with the new assembler, verifying that
the assembler did not generate any of the new warning messages.
gas/
* config/tc-s390.c: Handle new assembler options
"[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate
parsed register expressions with register type. Keep track of
operand number being parsed. Print warning message in case of
register type mismatch between instruction operand and parsed
register expression.
* doc/as.texi: Document new s390-specific assembler options
"[no-]warn-regtype-mismatch[=strict|relaxed|no]".
* NEWS: Mention new s390-specific register name type checks and
related assembler option "warn-regtype-mismatch=strict|
relaxed|no".
* testsuite/gas/s390/s390.exp: Add test cases for new assembler
option "warn-regtype-mismatch={strict|relaxed}".
* testsuite/gas/s390/esa-g5.s: Fix register types in tests for
didbr, diebr, tbdr, and tbedr.
* testsuite/gas/s390/zarch-z13.s: Fix register types in tests
for vgef, vgeg, vscef, and vsceg.
* testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s:
Tests for assembler option "warn-regtype-mismatch=strict".
* testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l:
Likewise.
* gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s:
Tests for assembler option "warn-regtype-mismatch=relaxed".
* gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l:
Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update
test cases for assembler option "warn-regtype-mismatch"
defaulting to "relaxed".
* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.
include/
* opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add
instruction flag to tag .insn pseudo-mnemonics.
opcodes/
* s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as
such.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
While at it add comments to logic to omit base and/or index register 0
in s390 disassembly.
opcodes/
* s390-dis.c: Add comments related to omitting base and/or index
register 0 in disassembly.
gas/
* testsuite/gas/s390/s390.exp: Add test cases for base and/or
index register 0.
* testsuite/gas/s390/zarch-base-index-0.s: Add test cases for
base and/or index register 0.
* testsuite/gas/s390/zarch-base-index-0.d: Likewise.
* testsuite/gas/s390/zarch-base-index-0-err.s: Add error test
cases for base and/or index register 0.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Assemble the esa-g5 test case with -march=g5.
Assemble the zarch-z900 test case with -march=z900.
gas/
* testsuite/gas/s390/s390.exp: Assemble processor specific test
cases for their respective processor (-march=<processor>).
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
The combination of an architecture size of 32 bits and z/Architecture
mode requires the highgprs flag to be set in the ELF output. It causes
the high-halves of the general purpose registers (GPRs) to be preserved
at run-time, so that the code can use 64-bit GPRs.
The architecture size of 32 bits can either be the default in case of
a default architecture name of "s390" or due to specification of the
option -m31 (to generate the 31-bit file format).
The z/Architecture mode can either be the default or due to
specification of the option -mzarch (to assemble for z/Architecture
mode). It can also be selected using the pseudo commands
".machinemode zarch" and ".machinemode zarch_nohighgprs". The latter
not causing the highgprs flag to be set.
The highgprs flag was only set when the following s390-specific
assembler options were given in the following specific order:
"-m31 -mzarch".
The highgprs flag was erroneously not set when:
- the order of above options was inverse (i.e. "-mzarch -m31"),
- the architecture mode defaulted to z/Architecture mode and
option "-m31" was specified,
- the architecture size defaulted to 32 bits due to a default
architecture name of "s390" and option -mzarch was specified,
- the architecture size defaulted to 32 bits and the architecture
mode defaulted to z/Architecture due to the specified processor
(e.g. "-march=z900" or follow-on processor).
Determine whether to set the highgprs flag in init_default_arch() after
having processed all assembler options in md_parse_option(). This
ensures the flag is set in all of the above cases it was erroneously not
set. Add test cases for highgprs flag, including ones that use
.machinemode to switch the architecture mode.
gas/
* config/tc-s390.c: Correct setting of highgprs flag in ELF
output.
* testsuite/gas/s390/s390.exp: Add test cases for highgprs
flag.
* testsuite/gas/s390/blank.s: Empty assembler source used in
test cases for "highgprs" flag.
* testsuite/gas/s390/esa-highgprs-0.d: Add test case for
highgprs flag.
* testsuite/gas/s390/zarch-highgprs-0.d: Likewise.
* testsuite/gas/s390/zarch-highgprs-1.d: Likewise.
* testsuite/gas/s390/esa-highgprs-machinemode-0.s: Add test case
for highgprs flag when using .machinemode to switch
architecture mode.
* testsuite/gas/s390/esa-highgprs-machinemode-0.d: Likewise.
* testsuite/gas/s390/esa-highgprs-machinemode-1.s: Likewise.
* testsuite/gas/s390/esa-highgprs-machinemode-1.d: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
The base register operand B may optionally be omitted in D(B) by coding
D and in D(L,B) by coding D(L). The index register operand X may
optionally be omitted in D(X,B) by coding D(,B) or D(B). Both base and
index register operands may optionally be omitted in D(X,B) by coding D.
In any case the omitted base and/or index register operand value
defaults to zero.
When parsing an erroneously omitted length L operand in D(L,B) by coding
D(,B) the base register operand B was erroneously consumed as length
operand. When using a register name for the base register operand this
was detected and reported as error. But when not using a register name
the base register operand value was erroneously used as length operand
value.
Correct the parsing of an omitted optional base or index register to not
erroneously use the base register operand value as length, when
erroneously omitting the length operand.
While at it rename the variable used to remember whether the base or
index register operand was omitted to enhance code readability.
Additionally add test cases for the optional omission of base and/or
index register operands.
Example assembler source:
mvc 16(1,%r1),32(%r2)
mvc 16(1),32(%r2)
mvc 16(,1),32(%r2) # undetected syntax error
Disassembly of bad assembly without commit shows the base register
operand value was erroneously used as length operand value:
0: d2 00 10 10 20 20 mvc 16(1,%r1),32(%r2)
6: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2)
c: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2)
Assembler messages with commit:
3: Error: operand 1: missing operand
gas/
* config/tc-s390.c: Correct parsing of omitted base register.
* testsuite/gas/s390/s390.exp: Add test cases for omitted base
and/or index register.
* testsuite/gas/s390/zarch-omitted-base-index.s: Test cases for
omitted optional base or index register.
* testsuite/gas/s390/zarch-omitted-base-index.d: Likewise.
* testsuite/gas/s390/zarch-omitted-base-index-err.s: Test cases
for omitted base and/or index register.
* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Report s390 assembler syntax errors as error instead of fatal error.
This allows the assembler to continue and potentially report further
syntax errors in the source. This should not cause syntax errors to
be erroneously accepted, as both error and fatal error cause the
assembler to return with a non-zero return code.
The following syntax errors are changed from fatal to error:
- invalid length field specified
- odd numbered general purpose register specified as register pair
- invalid floating point register pair. Valid fp register pair operands
are 0, 1, 4, 5, 8, 9, 12 or 13.
gas/
* config/tc-s390.c: Lower severity of assembler syntax errors
from fatal to error.
* testsuite/gas/s390/zarch-z9-109-err.l: Likewise.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
