Along with the relevant unit-tests, this adds the following rcpc3
instructions:
STL1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAP1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAPUR <Bt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Ht>, [<Xn|SP>{, #<simm>}]
LDAPUR <St>, [<Xn|SP>{, #<simm>}]
LDAPUR <Dt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Qt>, [<Xn|SP>{, #<simm>}]
STLUR <Bt>, [<Xn|SP>{, #<simm>}]
STLUR <Ht>, [<Xn|SP>{, #<simm>}]
STLUR <St>, [<Xn|SP>{, #<simm>}]
STLUR <Dt>, [<Xn|SP>{, #<simm>}]
STLUR <Qt>, [<Xn|SP>{, #<simm>}]
with `#<simm>' taking on a signed 8-bit integer value in the range
[-256,255] and `index' the values 0 or 1.
Co-authored-by: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Given the introduction of the new address operand types for rcpc3
instructions, this patch adds the necessary logic to teach
`general_constraint_met_p` how to proper handle these.
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
- AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
- AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
Beyond the need to encode any registers involved in data transfer and
the address base register for load/stores, it is necessary to specify
the data register addressing mode and whether the address register is
to be pre/post-indexed, whereby loads may be post-indexed and stores
pre-indexed with write-back.
The use of a single bit to specify both the indexing mode and indexing
value requires a novel function be written to accommodate this for
address operand insertion in assembly and another for extraction in
disassembly, along with the definition of two insn fields for use with
these instructions.
This therefore defines the following functions:
- aarch64_ins_rcpc3_addr_opt_offset
- aarch64_ins_rcpc3_addr_offset
- aarch64_ext_rcpc3_addr_opt_offset
- aarch64_ext_rcpc3_addr_offset
It extends the `do_special_{encoding|decoding}' functions and defines
two rcpc3 instruction fields:
- FLD_opc2
- FLD_rcpc3_size
The allowed immediate offsets in integer rcpc3 load store instructions
are not encoded explicitly in the instruction itself, being rather
implicitly equivalent to the amount of data loaded/stored by the
instruction.
This leads to the requirement that this quantity be calculated based on
the number of registers involved in the transfer, either as data
source or destination registers and their respective qualifiers.
This is done via `calc_ldst_datasize (const aarch64_opnd_info *opnds)'
implemented here, using a cumulative sum of qualifier sizes preceding
the address operand in the OPNDS operand list argument.
Indicating the presence of the Armv8.2-a feature adding further
support for the Release Consistency Model, the `+rcpc3' architectural
extension flag is added to the list of possible `-march' options in
Binutils, together with the necessary macro for encoding rcpc3
instructions.
This fixes the ld "Handle no DWARF information" testcase. Which
currently fails on riscv because a local label name is assumed
to be the current function name.
bfd/ChangeLog:
* elfnn-riscv.c (riscv_maybe_function_sym): Also check
_bfd_elf_is_local_label_name.
There are some tlbi operations that don't have a corresponding tlbip operation,
but we were incorrectly using the same list for both. Add the missing tlbi
*nxs operations, and use the F_REG_128 flag to filter tlbi operations that
don't have a tlbip analogue. For increased clarity, I have also used a macro
to reduce duplication between the 'nxs' and non-'nxs' variants, and added a
test to verify that no invalid combinations are accepted.
Additionally, fix two missing checks for AARCH64_OPND_SYSREG_TLBIP that were
preventing disassembly of tlbip instructions.
Hi,
This patch add support for SVE2.1 instructions ld1q,
ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 instruction faddqv,
fmaxnmqv, fmaxqv, fminnmqv and fminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 instruction dupq, eorqv and extq.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature
along with +sve2p1 optional flag to enabe this feature.
Also support for following SVE2p1 instructions is added
addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for FEAT_SME2p1 and "movaz" instructions
along with the optional flag +sme2p1.
Following "movaz" instructions are add:
Move and zero two ZA tile slices to vector registers.
Move and zero four ZA tile slices to vector registers.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 and SME2.1 non-widening BFloat16
(FEAT_B16B16) instructions.
Following instructions predicated, unpredicated and indexed
variants are added in this patch.
bfadd, bfclamp, bfmax bfmaxnm, bfmin,bfminnm,
bfmla,bfmls,bfmul and bfsub.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
The testsuite for SCFI contains target-specific tests.
When a test is executed with --scfi=experimental command line option,
the CFI annotations in the test .s files are skipped altogether by the
GAS for processing. The CFI directives in the input assembly files are,
however, validated by running the assembler one more time without
--scfi=experimental.
Some testcases are used to highlight those asm constructs that the SCFI
machinery in GAS currently does not support:
- Only System V AMD64 ABI is supported for now. Using either --32 or
--x32 with SCFI results in hard error.
See scfi-unsupported-1.s.
- Untraceable stack-pointer manipulation in function epilougue and prologue.
See scfi-unsupported-2.s.
- Using Dynamically Realigned Arguement Pointer (DRAP) register to
realign the stack. For SCFI, the CFA must be only REG_SP or REG_FP
based. See scfi-unsupported-drap-1.s
Some testcases are used to highlight some diagnostics that the SCFI
machinery in GAS currently issues, with an intent to help user correct
inadvertent errors in their hand-written asm. An error is issued when
GAS finds that input asm is not amenable to correct CFI synthesis.
- (#1) "Warning: SCFI: Asymetrical register restore"
- (#2) "Error: SCFI: usage of REG_FP as scratch not supported"
- (#3) "Error: SCFI: unsupported stack manipulation pattern"
In case of (#2) and (#3), SCFI generation is skipped for the respective
function. Above is a subset of the warnings/errors implemented in the
code.
gas/testsuite/:
* gas/scfi/README: New test.
* gas/scfi/x86_64/ginsn-add-1.l: New test.
* gas/scfi/x86_64/ginsn-add-1.s: New test.
* gas/scfi/x86_64/ginsn-dw2-regnum-1.l: New test.
* gas/scfi/x86_64/ginsn-dw2-regnum-1.s: New test.
* gas/scfi/x86_64/ginsn-pop-1.l: New test.
* gas/scfi/x86_64/ginsn-pop-1.s: New test.
* gas/scfi/x86_64/ginsn-push-1.l: New test.
* gas/scfi/x86_64/ginsn-push-1.s: New test.
* gas/scfi/x86_64/scfi-add-1.d: New test.
* gas/scfi/x86_64/scfi-add-1.l: New test.
* gas/scfi/x86_64/scfi-add-1.s: New test.
* gas/scfi/x86_64/scfi-add-2.d: New test.
* gas/scfi/x86_64/scfi-add-2.l: New test.
* gas/scfi/x86_64/scfi-add-2.s: New test.
* gas/scfi/x86_64/scfi-asm-marker-1.d: New test.
* gas/scfi/x86_64/scfi-asm-marker-1.l: New test.
* gas/scfi/x86_64/scfi-asm-marker-1.s: New test.
* gas/scfi/x86_64/scfi-asm-marker-2.d: New test.
* gas/scfi/x86_64/scfi-asm-marker-2.l: New test.
* gas/scfi/x86_64/scfi-asm-marker-2.s: New test.
* gas/scfi/x86_64/scfi-asm-marker-3.d: New test.
* gas/scfi/x86_64/scfi-asm-marker-3.l: New test.
* gas/scfi/x86_64/scfi-asm-marker-3.s: New test.
* gas/scfi/x86_64/scfi-bp-sp-1.d: New test.
* gas/scfi/x86_64/scfi-bp-sp-1.l: New test.
* gas/scfi/x86_64/scfi-bp-sp-1.s: New test.
* gas/scfi/x86_64/scfi-bp-sp-2.d: New test.
* gas/scfi/x86_64/scfi-bp-sp-2.l: New test.
* gas/scfi/x86_64/scfi-bp-sp-2.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-1.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-1.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-1.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-2.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-2.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-2.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-3.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-3.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-3.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-4.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-4.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-4.s: New test.
* gas/scfi/x86_64/scfi-cfg-1.d: New test.
* gas/scfi/x86_64/scfi-cfg-1.l: New test.
* gas/scfi/x86_64/scfi-cfg-1.s: New test.
* gas/scfi/x86_64/scfi-cfg-2.d: New test.
* gas/scfi/x86_64/scfi-cfg-2.l: New test.
* gas/scfi/x86_64/scfi-cfg-2.s: New test.
* gas/scfi/x86_64/scfi-cfi-label-1.d: New test.
* gas/scfi/x86_64/scfi-cfi-label-1.l: New test.
* gas/scfi/x86_64/scfi-cfi-label-1.s: New test.
* gas/scfi/x86_64/scfi-cfi-sections-1.d: New test.
* gas/scfi/x86_64/scfi-cfi-sections-1.l: New test.
* gas/scfi/x86_64/scfi-cfi-sections-1.s: New test.
* gas/scfi/x86_64/scfi-cofi-1.d: New test.
* gas/scfi/x86_64/scfi-cofi-1.l: New test.
* gas/scfi/x86_64/scfi-cofi-1.s: New test.
* gas/scfi/x86_64/scfi-diag-1.l: New test.
* gas/scfi/x86_64/scfi-diag-1.s: New test.
* gas/scfi/x86_64/scfi-diag-2.l: New test.
* gas/scfi/x86_64/scfi-diag-2.s: New test.
* gas/scfi/x86_64/scfi-dyn-stack-1.d: New test.
* gas/scfi/x86_64/scfi-dyn-stack-1.l: New test.
* gas/scfi/x86_64/scfi-dyn-stack-1.s: New test.
* gas/scfi/x86_64/scfi-enter-1.d: New test.
* gas/scfi/x86_64/scfi-enter-1.l: New test.
* gas/scfi/x86_64/scfi-enter-1.s: New test.
* gas/scfi/x86_64/scfi-fp-diag-2.l: New test.
* gas/scfi/x86_64/scfi-fp-diag-2.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-1.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-1.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-1.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-2.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-2.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-2.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-3.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-3.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-3.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-4.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-4.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-4.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-5.s: New test.
* gas/scfi/x86_64/scfi-lea-1.d: New test.
* gas/scfi/x86_64/scfi-lea-1.l: New test.
* gas/scfi/x86_64/scfi-lea-1.s: New test.
* gas/scfi/x86_64/scfi-leave-1.d: New test.
* gas/scfi/x86_64/scfi-leave-1.l: New test.
* gas/scfi/x86_64/scfi-leave-1.s: New test.
* gas/scfi/x86_64/scfi-pushq-1.d: New test.
* gas/scfi/x86_64/scfi-pushq-1.l: New test.
* gas/scfi/x86_64/scfi-pushq-1.s: New test.
* gas/scfi/x86_64/scfi-pushsection-1.d: New test.
* gas/scfi/x86_64/scfi-pushsection-1.l: New test.
* gas/scfi/x86_64/scfi-pushsection-1.s: New test.
* gas/scfi/x86_64/scfi-pushsection-2.d: New test.
* gas/scfi/x86_64/scfi-pushsection-2.l: New test.
* gas/scfi/x86_64/scfi-pushsection-2.s: New test.
* gas/scfi/x86_64/scfi-selfalign-func-1.d: New test.
* gas/scfi/x86_64/scfi-selfalign-func-1.l: New test.
* gas/scfi/x86_64/scfi-selfalign-func-1.s: New test.
* gas/scfi/x86_64/scfi-simple-1.d: New test.
* gas/scfi/x86_64/scfi-simple-1.l: New test.
* gas/scfi/x86_64/scfi-simple-1.s: New test.
* gas/scfi/x86_64/scfi-simple-2.d: New test.
* gas/scfi/x86_64/scfi-simple-2.l: New test.
* gas/scfi/x86_64/scfi-simple-2.s: New test.
* gas/scfi/x86_64/scfi-sub-1.d: New test.
* gas/scfi/x86_64/scfi-sub-1.l: New test.
* gas/scfi/x86_64/scfi-sub-1.s: New test.
* gas/scfi/x86_64/scfi-sub-2.d: New test.
* gas/scfi/x86_64/scfi-sub-2.l: New test.
* gas/scfi/x86_64/scfi-sub-2.s: New test.
* gas/scfi/x86_64/scfi-unsupported-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-1.s: New test.
* gas/scfi/x86_64/scfi-unsupported-2.l: New test.
* gas/scfi/x86_64/scfi-unsupported-2.s: New test.
* gas/scfi/x86_64/scfi-unsupported-3.l: New test.
* gas/scfi/x86_64/scfi-unsupported-3.s: New test.
* gas/scfi/x86_64/scfi-unsupported-4.l: New test.
* gas/scfi/x86_64/scfi-unsupported-4.s: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-1.s: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-2.l: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-2.s: New test.
* gas/scfi/x86_64/scfi-unsupported-drap-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-drap-1.s: New test.
* gas/scfi/x86_64/scfi-unsupported-insn-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-insn-1.s: New test.
* gas/scfi/x86_64/scfi-x86-64.exp: New file.
The ginsn representation keeps the DWARF register number of the
operands. The API ginsn_dw2_regnum relies on the the relative ordering
of these register entries in the table. Add a comment to make it clear.
opcodes/
* i386-reg.tbl: Add a comment.
Add a new listing option, -i, to emit ginsn in the listing output. We
may also emit other SCFI information if necessary in the future.
ginsn are most useful when seen alongside the assembly instructions.
Hence, they are emitted when the user includes the assembly instructions
in the listing output, i.e., "-ali=FILE".
gas/doc/:
* as.texi: Add documentation for the new listing option, -i.
This patch adds support in GAS to create generic GAS instructions
(a.k.a., the ginsn) for the x86 backend (AMD64 ABI only at this time).
Using this ginsn infrastructure, GAS can then synthesize CFI for
hand-written asm for x86_64.
A ginsn is a target-independent representation of the machine
instructions. One machine instruction may need one or more ginsn.
This patch also adds skeleton support for printing ginsn in the listing
output for debugging purposes.
Since the current use-case of ginsn is to synthesize CFI, the x86 target
needs to generate ginsns necessary for the following machine
instructions only:
- All change of flow instructions, including all conditional and
unconditional branches, call and return from functions.
- All register saves and unsaves to the stack.
- All instructions affecting the two registers that could potentially
be used as the base register for CFA tracking. For SCFI, the base
register for CFA tracking is limited to REG_SP and REG_FP only for
now.
The representation of ginsn is kept simple:
- GAS instruction has GINSN_NUM_SRC_OPNDS (defined to be 2 at this time)
number of source operands and one destination operand at this time.
- GAS instruction uses DWARF register numbers in its representation and
does not track register size.
- GAS instructions carry location information (file name and line
number).
- GAS instructions are ID's with a natural number in order of their
addtion to the list. This can be used as a proxy for the static
program order of the corresponding machine instructions.
Note that, GAS instruction (ginsn) format does not support
GINSN_TYPE_PUSH and GINSN_TYPE_POP. Some architectures, like aarch64,
do not have push and pop instructions, but rather STP/LDP/STR/LDR etc.
instructions. Further these instructions have a variety of addressing
modes, like offset, pre-indexing and post-indexing etc. Among other
things, one of differences in these addressing modes is _when_ the addr
register is updated with the result of the address calculation: before
or after the memory operation. To best support such needs, the generic
instructions like GINSN_TYPE_LOAD, GINSN_TYPE_STORE together with
GINSN_TYPE_ADD, and GINSN_TYPE_SUB may be used.
The functionality provided in ginsn.c and scfi.c is compiled in when a
target defines TARGET_USE_SCFI and TARGET_USE_GINSN. This can be
revisited later when there are other use-cases of creating ginsn's in
GAS, apart from the current use-case of synthesizing CFI for
hand-written asm.
Support is added only for System V AMD64 ABI for ELF at this time. If
the user enables SCFI with --32, GAS issues an error:
"Fatal error: SCFI is not supported for this ABI"
For synthesizing (DWARF) CFI, the SCFI machinery requires the programmer
to adhere to some pre-requisites for their asm:
- Hand-written asm block must begin with a .type foo, @function
It is highly recommended to, additionally, also ensure that:
- Hand-written asm block ends with a .size foo, .-foo
The SCFI machinery encodes some rules which align with the standard
calling convention specified by the ABI. Apart from the rules, the SCFI
machinery employs some heuristics. For example:
- The base register for CFA tracking may be either REG_SP or REG_FP.
- If the base register for CFA tracking is REG_SP, the precise amount of
stack usage (and hence, the value of REG_SP) must be known at all times.
- If using dynamic stack allocation, the function must switch to
FP-based CFA. This means using instructions like the following (in
AMD64) in prologue:
pushq %rbp
movq %rsp, %rbp
and analogous instructions in epilogue.
- Save and Restore of callee-saved registers must be symmetrical.
However, the SCFI machinery at this time only warns if any such
asymmetry is seen.
These heuristics/rules are architecture-independent and are meant to
employed for all architectures/ABIs using SCFI in the future.
gas/
* Makefile.am: Add new files.
* Makefile.in: Regenerated.
* as.c (defined): Handle documentation and listing option for
ginsns and SCFI.
* config/obj-elf.c (obj_elf_size): Invoke ginsn_data_end.
(obj_elf_type): Invoke ginsn_data_begin.
* config/tc-i386.c (x86_scfi_callee_saved_p): New function.
(ginsn_prefix_66H_p): Likewise.
(ginsn_dw2_regnum): Likewise.
(x86_ginsn_addsub_reg_mem): Likewise.
(x86_ginsn_addsub_mem_reg): Likewise.
(x86_ginsn_alu_imm): Likewise.
(x86_ginsn_move): Likewise.
(x86_ginsn_lea): Likewise.
(x86_ginsn_jump): Likewise.
(x86_ginsn_jump_cond): Likewise.
(x86_ginsn_enter): Likewise.
(x86_ginsn_safe_to_skip): Likewise.
(x86_ginsn_unhandled): Likewise.
(x86_ginsn_new): New functionality to generate ginsns.
(md_assemble): Invoke x86_ginsn_new.
(s_insn): Likewise.
(i386_target_format): Add hard error for usage of SCFI with non AMD64 ABIs.
* config/tc-i386.h (TARGET_USE_GINSN): New definition.
(TARGET_USE_SCFI): Likewise.
(SCFI_MAX_REG_ID): Likewise.
(REG_FP): Likewise.
(REG_SP): Likewise.
(SCFI_INIT_CFA_OFFSET): Likewise.
(SCFI_CALLEE_SAVED_REG_P): Likewise.
(x86_scfi_callee_saved_p): Likewise.
* gas/listing.h (LISTING_GINSN_SCFI): New define for ginsn and
SCFI.
* gas/read.c (read_a_source_file): Close SCFI processing at end
of file read.
* gas/scfidw2gen.c (scfi_process_cfi_label): Add implementation.
(scfi_process_cfi_signal_frame): Likewise.
* subsegs.h (struct frch_ginsn_data): New forward declaration.
(struct frchain): New member for ginsn data.
* gas/subsegs.c (subseg_set_rest): Initialize the new member.
* symbols.c (colon): Invoke ginsn_frob_label to convey
user-defined labels to ginsn infrastructure.
* ginsn.c: New file.
* ginsn.h: New file.
* scfi.c: New file.
* scfi.h: New file.
Some x86 instructions affect the stack pointer implicitly. Add a new
operand constraint to reflect this. This will be useful for SCFI
implmentation to ensure its correctness.
Mark all push, pop, call, ret, enter, leave, INT, iret instructions.
opcodes/
* i386-gen.c: Update opcode_modifiers.
* i386-opc.h: Add a new constraint.
* i386-opc.tbl: Update the affected instructions.
* i386-tbl.h: Regenerated.
Rex2 is currently an operand constraint. For the upcoming SCFI
implementation in GAS, we need to identify operations which implicitly
update the stack pointer. An operand constraint enumerator for implicit
stack op seems more appropriate than an attribute. However, two opcodes
currently necessitate both Rex2 and an implicit stack op marker; this
prompts revisiting the current representations a bit.
Make Rex2 a standalone attribute, so that later a new operand constraint
may be added for IMPLICIT_STACK_OP.
ChangeLog:
* gas/config/tc-i386.c (is_apx_rex2_encoding): Update the check.
* opcodes/i386-gen.c: Add a new BITFIELD for Rex2.
* opcodes/i386-opc.h (REX2_REQUIRED): Remove.
* opcodes/i386-opc.tbl: Remove Rex2 operand constraint.
* opcodes/i386-tbl.h: Regenerated.
Define a new set of handlers for CFI directives for the purpose of SCFI.
The SCFI machinery ignores many of the user-specified CFI direcives when
SCFI is in effect. A warning ("Warning: SCFI ignores most
user-specified CFI directives") is issued once per file. The following
CFI directives, however, are not ignored:
- .cfi_sections
- .cfi_label
- .cfi_signal_frame
gas/
* Makefile.am: Add new files to GAS_CFILES and HFILES.
* Makefile.in: Likewise.
* gas/read.c (scfi_pop_insert): New define.
(pobegin): Use the SCFI handlers.
* scfidw2gen.c: New file.
* scfidw2gen.h: New file.
When the command line option --scfi=experimenta is passed to the GNU
assembler, it will synthesize DWARF call frame information (CFI) for the
input assembly.
The option --scfi=experimental will also ignore most of the existing
.cfi_* directives, if already contained in the provided input file.
Only the following CFI directives will not be ignored:
- .cfi_sections,
- .cfi_label,
- .cfi_signal_frame
To use SCFI, a target will need to:
- define TARGET_USE_SCFI and TARGET_USE_GINSN, and other necessary
definitions,
- provide means to help GAS understand the target specific instruction
semantics by creating ginsns.
The upcoming support for SCFI is inteded to be experimental, hence the
option --scfi=experimental. The --scfi= may see more options like
--scfi=[all,none] added in future, once the SCFI support in GAS is
mature and robust. The offering may also see for example, an
--scfi=inline option for dealing with inline asm may be added in the
future. In --scfi=inline option, the GNU assembler may consume (and not
ignore) the compiler generated CFI for the code surrounding the inline
asm.
Also document the option.
gas/
* as.c (show_usage): Add support for --scfi=experimental.
(parse_args): Likewise.
* as.h (enum synth_cfi_type): Define new type.
* doc/as.texi: Document the new option.
scfidw2gen will use this for processing the .cfi_sections directive.
gas/
* dw2gencfi.c (dot_cfi_sections): Not static anymore.
* dw2gencfi.h (dot_cfi_sections): Mark as extern.
Move the following three defines to the header file, so the SCFI
machinery can use them:
- tc_cfi_frame_initial_instructions
- tc_cfi_startproc
- tc_cfi_endproc
gas/
* dw2gencfi.c: Move from ...
* dw2gencfi.h: ... to here.
The code in dw2gencfi.c was checking variable cfi_sections and
all_cfi_sections seemingly randomly. Accessing all_cfi_sections seems
to the correct variable to access.
The data in cfi_sections has already been propagated to all_cfi_sections
once cfi_dot_startproc () has been called.
gas/
* dw2gencfi.c (dot_cfi_startproc): Use all_cfi_sections
instead.
(dot_cfi_endproc): Likewise.
(dot_cfi_fde_data): Likewise.
cfi_sections_set is best set to true in cfi_dot_startproc (). Setting
it to true again in other APIs (dot_cfi_endproc, dot_cfi_fde_data, and
cfi_finish) is unnecessary. Also, move setting the global var
all_cfi_sections into cfi_set_sections ().
gas/
* dw2gencfi.c (cfi_set_sections): Set cfi_sections_set and
cfi_sections here.
(dot_cfi_startproc): Remove unnecessarily setting
cfi_set_sections to true.
(dot_cfi_endproc): Likewise.
(dot_cfi_fde_data): Likewise.
(cfi_finish): Likewise.
When running test-case gdb.mi/mi-dprintf.exp with check-read1, I run into:
...
(gdb) ^M
PASS: gdb.mi/mi-dprintf.exp: gdb: mi 2nd dprintf stop
-data-evaluate-expression stderr^M
^done,value="0x7ffff7e4a420 <_IO_2_1_stderr_>"^M
(gdb) FAIL: gdb.mi/mi-dprintf.exp: stderr symbol check
...
The problem is in proc mi_gdb_is_stderr_available:
...
proc mi_gdb_is_stderr_available {} {
set has_stderr_symbol false
gdb_test_multiple "-data-evaluate-expression stderr" "stderr symbol check" {
-re "\\^error,msg=\"'stderr' has unknown type; cast it to its declared type\"\r\n$::mi_gdb_prompt$" {
}
-re "$::mi_gdb_prompt$" {
set has_stderr_symbol true
}
}
...
which uses a gdb_test_multiple that is supposed to use the mi prompt, but
doesn't use -prompt to indicate this. Consequently, the default patterns use
the regular gdb prompt, which trigger earlier than the two custom patterns
which use "$::mi_gdb_prompt$".
Fix this by adding the missing -prompt "$::mi_gdb_prompt$" arguments.
While we're at it, make the gdb_test_multiple call a bit more readable by
using variables, and by using -wrap.
Tested on x86_64-linux, with:
- gcc and clang (to trigger both the has_stderr_symbol true and false cases)
- make check and make check-read1.
With check-read1 we run into:
...
(gdb) break DNE>::DNE^M
Function "DNE>::DNE" not defined.^M
Make breakpoint pending on future shared library load? (y or [n]) y^M
Breakpoint 9 (DNE>::DNE) pending.^M
n^M
(gdb) FAIL: gdb.cp/namespace.exp: br malformed '>' (got interactive prompt)
n^M
...
The question is supposed to be handled by the question and response arguments
to this gdb_test call:
...
gdb_test "break DNE>::DNE" "" "br malformed \'>\'" \
"Make breakpoint pending on future shared library load?.*" "y"
...
but both this and the builtin handling in gdb_test_multiple triggers.
The cause of this is that the question argument regexp is incomplete.
Fix this by making sure that the entire question is matched in the regexp:
...
set yn_re [string_to_regexp {(y or [n])}]
...
"Make breakpoint pending on future shared library load\\? $yn_re " "Y"
...
Tested on x86_64-linux.
Per RISC-V spec, the lr/sc sequence can consist of up to 16 instructions, and we
cannot insert breakpoints in the middle of this sequence. Before this, we only
detected a specific pattern (the most common one). This patch improves this part
and now supports more complex pattern detection.
Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn>
Approved-By: Andrew Burgess <aburgess@redhat.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Fix two cases where gp-display-html terminates prematurely because the
input format is not recognized. This problem occurs in the function
overview and caller-callee parts of the code.
The fix consists of new regular expressions and a different approach
in handling the input from gp-display-text.
Also fix a performance problem in the caller-callee part that has a
noticeable impact on the performance for large applications.
gprofng/ChangeLog
2024-01-10 Ruud van der Pas <ruud.vanderpas@oracle.com>
PR gprofng/30438
PR gprofng/30439
PR gprofng/30942
* gp-display-html/gp-display-html.in: fixes the issues.
The following change broke simulator testsuite with host GCC 13:
commit 435ad222b3
sim: warnings: compile build tools with -Werror too
Host GCC13 complains about missing function prototypes:
binutils/sim/testsuite/common/bits-gen.c:26:1: error: no previous prototype for ‘gen_struct’ [-Werror=missing-prototypes]
26 | gen_struct (void)
| ^~~~~~~~~~
Fix by making the functions static, which instructs the compiler that
there is no need for a prototype.
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
Relocations installed by the BPF ELF backend were sometimes incorrectly
adding the symbol value to the relocation entry addend, when the correct
relocation value was already stored in the addend. This could lead to a
relocation effectively adding the symbol value twice.
Fix that by making bpf_elf_generic_reloc () more similar to the flow of
bfd_install_relocation in the case where howto->install_addend is set,
which is how it ought to behave.
bfd/
* bpf-reloc.def (R_BPF_64_ABS32, R_BPF_64_ABS64)
(R_BPF_64_NODYLD32): Set partial_inplace to true.
* elf64-bpf.c (bpf_elf_generic_reloc): Do not include the value
of the symbol when installing relocation. Copy some additional
logic from bfd_elf_generic_reloc.
gas/
* testsuite/gas/bpf/bpf.exp: Run new test.
* testsuite/gas/bpf/elf-relo-1.d: New.
* testsuite/gas/bpf/elf-relo-1.s: New.
After this commit:
commit 1925bba80e
Date: Thu Jan 4 10:01:24 2024 +0000
gdb/python: add gdb.InferiorThread.__repr__() method
failures were reported for gdb.python/py-inferior.exp.
The test grabs a gdb.InferiorThread object representing an inferior
thread, and then, later in the test, expects this Python object to
become invalid when the inferior thread has exited.
The gdb.InferiorThread object was obtained from the list returned by
calling gdb.Inferior.threads().
The mistake I made in the original commit was to assume that the order
of the threads returned from gdb.Inferior.threads() somehow reflected
the thread creation order. Specifically, I was expecting the main
thread to be first in the list, and "other" threads to appear ... not
first.
However, the gdb.Inferior.threads() function creates a list and
populates it from a map. The order of the threads in the returned
list has no obvious relationship to the thread creation order, and can
vary from host to host.
On my machine the ordering was as I expected, so the test passed for
me. For others the ordering was not as expected, and it just happened
that we ended up recording the gdb.InferiorThread for the main thread.
As the main thread doesn't exit (until the test is over), the
gdb.InferiorThread object never became invalid, and the test failed.
Fixed in this commit by taking more care to correctly find a non-main
thread. I do this by recording the main thread early on (when there
is only one inferior thread), and then finding any thread that is not
this main thread.
Then, once all of the secondary threads have exited, I know that the
second InferiorThread object I found should now be invalid.
The test still passes for me, and I believe this should fix the issue
for everyone else too.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31238
