Remove the patterns to match Maverick co-processor instructions from
the disassembly tables.
This required fixing a couple of tests in the assembler testsuite
where we, probably incorrectly, disassembled generic co-processor
instructions as a Maverick instruction (it particularly made no sense
to do this for Armv6t2 in Thumb state).
Delete all the Maverick instructions and register handling from the
assembler. We continue to recognize -mcpu=ep9312, but treat it as an
alias for arm920t. We no-longer recognize -mfpu=maverick.
* https://github.com/riscv/riscv-b/tags
Added standard B extension back, which implies Zba, Zbb and Zbs extensions.
* https://github.com/riscv/riscv-zaamo-zalrsc/tags
Splited standard A extension into two new extensions, Zaamo and Zalrsc.
The A extension implies Zaamo and Zalrsc extensions.
Not sure if we need to do the similar check as i and zicsr/zifencei.
Passed riscv[32|64]-[elf/linux] binutils testcases.
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules
for A and B extensions. The A implies Zaamo and Zalrsc, the
B implies Zba, Zbb and Zbs.
(riscv_supported_std_ext): Supported B extension with v1.0.
(riscv_supported_std_z_ext): Supported Zaamo and Zalrsc with v1.0.
(riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Updated.
include/
* opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_A, Added
INSN_CLASS_ZAAMO and INSN_CLASS_ZALRSC.
opcodes/
* riscv-opc.c (riscv_opcodes): Splited standard A extension into two
new extensions, Zaamo and Zalrsc.
gas/
* testsuite/gas/riscv/march-imply-a.d: New testcase.
* testsuite/gas/riscv/march-imply-b.d: New testcase.
* testsuite/gas/riscv/attribute-01.d: Updated.
* testsuite/gas/riscv/attribute-02.d: Updated.
* testsuite/gas/riscv/attribute-03.d: Updated.
* testsuite/gas/riscv/attribute-04.d: Updated.
* testsuite/gas/riscv/attribute-05.d: Updated.
* testsuite/gas/riscv/attribute-10.d: Updated.
* testsuite/gas/riscv/mapping-symbols.d: Updated.
* testsuite/gas/riscv/march-imply-g.d: Updated.
* testsuite/gas/riscv/march-imply-unsupported.d: Updated.
* testsuite/gas/riscv/march-ok-reorder.d: Updated.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Updated.
gas/ChangeLog:
* config/tc-i386.c (build_modrm_byte): Dropped the use of
extension_opcode to encode the vvvv register.
* testsuite/gas/i386/x86-64-sse2avx.d: Added new testcases.
* testsuite/gas/i386/x86-64-sse2avx.s: Diito.
opcodes/ChangeLog:
* i386-opc.tbl: Added DstVVVV to some extension_opcode instructions.
* i386-tbl.h: Regenerated.
gas/ChangeLog:
* config/tc-i386.c (build_modrm_byte): Dropped the use of
SWAP_SOURCES to encode the vvvv register.
opcodes/ChangeLog:
* i386-opc.h (SWAP_SOURCES): Dropped.
(NO_DEFAULT_MASK): Adjusted the value.
(ADDR_PREFIX_OP_REG): Ditto.
(DISTINCT_DEST): Ditto.
(IMPLICIT_STACK_OP): Ditto.
(VexVVVV_SRC2): New.
* i386-opc.tbl: Dropped SwapSources and replaced its VexVVVV
with Src1VVVV.
* i386-tbl.h: Regenerated.
Use vexvvvv as the switch state, and replace VexVVVV with Src1VVVV.
Src1VVVV means using VEX.vvvv encodes the first source register
operand. The old logic did not check vexvvvv first, which made the
logic here very complicated.
gas/ChangeLog:
* config/tc-i386.c (optimize_encoding): Replaced 1 with Src1VVVV.
(build_modrm_byte): Used vexvvvv to encode the vvvv register.
(s_insn): Replaced 1 with Src1VVVV.
opcodes/ChangeLog:
* i386-opc.h (VexVVVV_DST): Adjusted the value.
(Src1VVVV): New.
* i386-opc.tbl: Replaced part VexVVVV with Src1VVVV.
* i386-tbl.h: Regenerated.
Since {vex}/{vex3} are respected on legacy mnemonics when -msse2avx is
in use, {evex} should be respected, too. So far this is the case only
for insns where eGPR-s can come into play. Extend coverage to insns with
only %xmm register and possibly immediate operands.
Legacy encoded SIMD insns are converted to AVX ones in that mode. When
eGPR-s are in use, i.e. with APX, convert to AVX10 insns (where
available; there are quite a few which can't be converted).
Note that LDDQU is represented as VMOVDQU32 (and the prior use of the
sse3 template there needs dropping, to get the order right).
Note further that in a few cases, due to the use of templates, AVX512VL
is used when AVX512F would suffice. Since AVX10 is the main reference,
this shouldn't be too much of a problem.
In certain cases we were calculating the jump displacement incorrectly
when deciding whether to relax a branch. This meant for some branches,
such as a very long backwards conditional branch, relaxation was not
done when it should have been. The result was to error later, because
the actual jump displacement was too large to fit in the original
instruction.
This patch fixes up the displacement calculation so that those branches
are correctly relaxed and no longer result in an error. In addition, it
changes md_convert_frag to install fixups for the JAL instructions in
the resulting relaxations rather than encoding the displacement value
directly.
gas/
* config/tc-bpf.c (relaxed_branch_length): Correct displacement
calculation when relaxing.
(md_convert_frag): Likewise. Install fixups for JAL
instructions resulting from relaxation.
* testsuite/gas/bpf/jump-relax-ja-be.d: Correct and expand test.
* testsuite/gas/bpf/jump-relax-ja.d: Likewise.
* testsuite/gas/bpf/jump-relax-ja.s: Likewise.
* testsuite/gas/bpf/jump-relax-jump-be.d: Likewise.
* testsuite/gas/bpf/jump-relax-jump.d: Likewise.
* testsuite/gas/bpf/jump-relax-jump.s: Likewise.
Gas should not emit ADD/SUB relocation pairs for label differences
if they are in the same section without code flag even relax enabled.
Because the real value is not be affected by relaxation and it can be
compute out in assembly stage. Thus, correct the `TC_FORCE_RELOCATION
_SUB_SAME` and the label differences in same section without code
flag can be resolved in fixup_segment().
Ignore .align at the start of a section may result in misalignment when
partial linking. Manually add -mignore-start-align option without partial
linking.
Gcc -falign-functions add .align 5 to the start of a section, it causes some
error message mismatch. Set these testcases to xfail on LoongArch target.
Fix a memory leak in md_assemble where copy may be cleared and may be
the same as copy:
if (copy && !mnem_suffix)
{
line = copy;
copy = NULL;
no_match:
* config/tc-i386.c (md_assemble): Properly free the xstrdup
memory.
CFI label name can be freed only after use.
* scfi.c (handle_scfi_dot_cfi): Free CFI label name after use.
* scfidw2gen.c (scfi_process_cfi_label): Add a comment. Remove
TODO on freeing CFI label name.
Use long NOPs for Intel Core processors since they are faster than
multiple NOPs. Don't use them for 64-bit processors by default since
Intel Atom processors can only decode 4 prefixes in 1 cycle.
* config/tc-i386.c (alt64_9): New.
(alt64_10): Likewise.
(alt64_11): Likewise.
(alt64_12): Likewise.
(alt64_13): Likewise.
(alt64_14): Likewise.
(alt64_15): Likewise.
(alt64_patt): Likewise.
(i386_generate_nops): Use alt64_patt for Intel Core processors
in 64-bit mode.
* testsuite/gas/i386/x86-64-nops-1-core2.d: Expect long NOPs.
* testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Replace
../x86-64-nops-1.d with ../x86-64-nops-1-core2.d.
* testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Replace
../x86-64-nops-4.d with ../x86-64-nops-4-core2.d.
There are two state propagation functions in SCFI machinery - forward
and backward flow. The patch addresses two issues:
- In forward_flow_scfi_state (), the state being compared in forward flow
must be that at the exit of a prev bb and that at the entry of the
next bb. The variable holding the state to be compared was
previously (erroneously) stale.
- In cmp_scfi_state (), the assumption that two different control
flows, leading to the same basic block, cannot have a mismatched
notion of CFA base register, is not true. Remove the assertion and
instead return err if mismatch.
Fixing these issues helps correctly synthesize CFI, when previously
SCFI was erroring out for an otherwise valid input asm.
gas/
* scfi.c (cmp_scfi_state): Remove assertion and return mismatch
in return value as applicable.
(forward_flow_scfi_state): Update state object to be the same as
the exit state of the prev bb before comparing.
gas/testsuite/
* gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
* gas/scfi/x86_64/scfi-cfg-5.d: New test.
* gas/scfi/x86_64/scfi-cfg-5.l: New test.
* gas/scfi/x86_64/scfi-cfg-5.s: New test.
A GCFG (ginsn control flow graph) is created for SCFI purposes in GAS.
The existing GCFG creation process was ignoring some paths.
add_bb_at_ginsn () is a recursive function which should return the root
of the added basic blocks. This property was being violated in some
traversals, e.g., where a taken path involving a sequence of a few basic
blocks eventually culminated in a GINSN_TYPE_RETURN instruction. This
patch fixes the issue by keeping an explicit variable root_bb to
memorize the bb to be returned.
Next, find_or_make_bb () must either create or find the bb with the
first ginsn as the provided ginsn. Add a few assertions to ensure
health of the cfg creation process.
Note that the testcase, in its current shape, is not fit for catching
regressions for the issue at hand. Although the testcase does exercise
the updated code path, the testcase passes even without the current fix,
because the added edge in this specific testcase does not alter the
synthesized CFI. (The missing edge is the fallthrough edge of the
conditional branch "jne .L13" in the testcase.)
Using a manual gcfg_print (), one can see the missing edge without the
fix. Lets keep the testcase for now, until there is a better way to
test the GCFG for this issue (e.g., either by dumping the GCFG in
textual format, or a case when the missing edge does cause wrong
synthesized CFI).
gas/
* ginsn.c (bb_add_edge): Fix a code comment.
(find_bb): Likewise.
(find_or_make_bb): Add new assertions to ensure health of cfg
creation process.
(add_bb_at_ginsn): Keep reference to the root_bb and return it.
gas/testsuite/
* gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
* gas/scfi/x86_64/scfi-cfg-4.d: New test.
* gas/scfi/x86_64/scfi-cfg-4.l: New test.
* gas/scfi/x86_64/scfi-cfg-4.s: New test.
This patch fixes the disassembly of vq[r]shr[u]n insns so that the
shift immediate is properly decoded. See the description of the
previous patch for an example of the incorrect disassembly.
As part of this patch we also fix the mve-vqrshrn.d test which was
testing for the incorrect disassembly of the immediates. The
disassembly now matches the assembled instructions in that test.
Finally we add an mve-vqshrn test which tests the non-rounding variants
of those insns, whose encoding we fixed with the previous patch in this
series.
As it stands, these insns are incorrectly encoded as vqrshr[u]n.
Concretely, the problem can be seen as follows:
$ cat t.s
vqrshrnb.s16 q0,q0,#8
vqshrnb.s16 q0,q0,#8
$ gas/as-new t.s -march=armv8.1-m.main+mve -o t.o
$ binutils/objdump -d t.o -m armv8.1-m.main
t.o: file format elf32-littlearm
Disassembly of section .text:
00000000 <.text>:
0: ee88 0f41 vqrshrnb.s16 q0, q0, #0
4: ee88 0f41 vqrshrnb.s16 q0, q0, #0
Here we assemble these two instructions to the same opcode. The
encoding of the first is the correct, while the encoding of the second
is incorrect, and the bottom bit should be clear, see the Armv8-M ARM:
https://developer.arm.com/documentation/ddi0553/latest/
There is an additional problem here in that the disassembly of the
immediate is incorrect. llvm-objdump shows the correct disassembly
here:
t.o: file format elf32-littlearm
Disassembly of section .text:
00000000 <$t>:
0: ee88 0f41 vqrshrnb.s16 q0, q0, #8
4: ee88 0f41 vqrshrnb.s16 q0, q0, #8
Note that we defer adding a test for the correct encoding of these insns
until the next patch which fixes the disassembly issue.
Support zcmp extension push/pop/popret and popret zero instructions.
The `reg_list' is a list containing 1 to 13 registers, we can use:
"{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2} ... {ra, s0-sN}"
to present this feature.
Passed gcc/binutils regressions of riscv-gnu-toolchain.
Most of work was finished by Sinan Lin.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subset): Imply zca for zcmp.
(riscv_supported_std_z_ext): Added zcmp with version 1.0.
(riscv_parse_check_conflicts): Zcmp conflicts with d/zcd.
(riscv_multi_subset_supports): Handle zcmp.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* config/tc-riscv.c (regno_to_reg_list): New function, used to map
register to reg_list number.
(reglist_lookup): Called reglist_lookup_internal. Return false if
reg_list number is zero, which is an invalid value.
(reglist_lookup_internal): Parse register list, and return the last
register by regno_to_reg_list.
(validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/march-help.l: Updated.
* testsuite/gas/riscv/zcmp-push-pop-fail.d: New test.
* testsuite/gas/riscv/zcmp-push-pop-fail.l: New test.
* testsuite/gas/riscv/zcmp-push-pop-fail.s: New test.
* testsuite/gas/riscv/zcmp-push-pop.d: New test.
* testsuite/gas/riscv/zcmp-push-pop.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH/MASK_CM_PUSH): New macros for zcmp.
(MATCH/MASK_CM_POP): Ditto.
(MATCH/MASK_CM_POPRET): Ditto.
(MATCH/MASK_CM_POPRETZ): Ditto.
(DECLARE_INSN): New declarations for zcmp.
* opcode/riscv.h (EXTRACT/ENCODE/VALID_ZCMP_SPIMM): Handle spimm
operand for zcmp.
(OP_MASK_REG_LIST): Handle operand for zcmp register list.
(OP_SH_REG_LIST): Ditto.
(ZCMP_SP_ALIGNMENT): New argument, used in riscv_get_sp_base.
(X_S0, X_S1, X_S2, X_S10, X_S11): New register numbers.
(enum riscv_insn_class): Added INSN_CLASS_ZCMP.
(extern riscv_get_sp_base): Added.
opcodes/ChangeLog:
* riscv-dis.c (print_reg_list): New function, used to get zcmp
reg_list field.
(riscv_get_spimm): New function, used to get zcmp sp adjustment
immediate.
(print_insn_args): Handle new operands for zcmp.
* riscv-opc.c (riscv_get_sp_base): New function, used by gas and
objdump. Get sp base adjustment.
(riscv_opcodes): Added zcmp instructions.
This patch is based on APX NF patch and also adds test cases for Checking 64-bit insns not sizeable through
register operands with evex.
gas/ChangeLog:
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Added no-egpr testcases for movbe.
* testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Added tests.
* testsuite/gas/i386/noreg64-evex.d: New test.
* testsuite/gas/i386/noreg64-evex.e: Ditto.
* testsuite/gas/i386/noreg64-evex.s: Ditto.
* testsuite/gas/i386/x86-64-apx_f-evex.d: Ditto.
* testsuite/gas/i386/x86-64-apx_f-evex.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex.h: Added %ME to movbe.
* i386-dis.c : Added %XE to evex_from_vex instructions to output {evex}.
(struct dis386): New %ME.
(putop): Handle %ME and output {evex} for evex_from_legacy instructions.
* Return early when the instruction name is (bad).
For the case when NDD and NF are both 0 in evex-promoted format,
we will fully support and test it in another patch.
gas/ChangeLog:
* NEWS: Support Intel APX NF.
* config/tc-i386.c (enum i386_error): Add unsupported_nf.
(struct _i386_insn): Add has_nf.
(is_apx_evex_encoding): Ditto.
(build_apx_evex_prefix): Encode the NF bit.
(md_assemble): Handle unsupported_nf.
(parse_insn): Handle Prefix_NF and report bad for illegal combination.
(can_convert_NDD_to_legacy): Replace i.tm.opcode_modifier.nf with i.has_nf.
(match_template): Support D for APX_F insns and check NF support.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Add bad test for NF bit.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.
* testsuite/gas/i386/x86-64-apx-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add apx nf tests.
* testsuite/gas/i386/x86-64-apx-nf-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-nf.d: Ditto.
* testsuite/gas/i386/x86-64-apx-nf.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex.h: Add %NF to the instructions that support APX NF and
add new instruction imul, popcnt, tzcnt and lzcnt to EVEX table.
* i386-dis-evex-reg.h: Ditto.
* i386-dis.c (struct instr_info): Add nf.
(struct dis386): Add "NF" for EVEX.NF.
(get_valid_dis386): Set ins->vex.nf and report bad-nf for illegal case.
(print_insn): Handle ins.vex.nf.
(putop): Handle "%NF".
* i386-opc.h (Prefix_NF): New.
* i386-opc.tbl: Added new entries to support full APX NF instructions.
* i386-mnem.h: Regenerated.
* i386-tbl.h: Regenerated.
For some reason, these targets are missing although others from the
same family are present. This looks like an oversight.
This enables calling 'make install-dvi' from the top-level build
directory.
Ignore .align if it is at the start of a section and the alignment
can be divided by the section alignment, the section alignment
can ensure this .align has a correct alignment.
To represent the first and third expression of .align, R_LARCH_ALIGN need to
associate with a symbol. We define a local symbol for R_LARCH_AGLIN.
But if the section of the local symbol is discarded, it may result in
a undefined symbol error.
Instead, we use the section name symbols, and this does not need to
add extra symbols.
During partial linking (ld -r), if the symbol associated with a relocation is
STT_SECTION type, the addend of relocation needs to add the section output
offset. We prevent it for R_LARCH_ALIGN.
The elf_backend_data.rela_normal only can set all relocations of a target to
rela_normal. Add a new function is_rela_normal to elf_backend_data, it can
set part of relocations to rela_normal.
The ginsn infrastructure in GAS includes the ability to create a GCFG
(ginsn CFG). A GCFG is currently used for SCFI passes.
This patch fixes the following invalid assumptions / code blocks:
- The function ginsn_direct_local_jump_p () was erroneously _not_
checking whether the symbol is locally defined (i.e., within the
scope of the code block for which GCFG is desired). Fix the code
to do so.
- Similarly, the GCFG creation code, in gcfg_build () itself had an
assumption that a GINSN_TYPE_JUMP to a non-local symbol will not be
seen. The latter can indeed be seen, and in fact, needs to be treated
the same way as an exit from the function in terms of control-flow.
gas/
* ginsn.c (ginsn_direct_local_jump_p): Check if the symbol
is local to the code block or function being assembled.
(add_bb_at_ginsn): Remove buggy assumption.
(frch_ginsn_data_append): Direct jmps do not disqualify a stream
of ginsns from GCFG creation.
gas/testsuite/
* gas/scfi/x86_64/scfi-cfg-3.d: New test.
* gas/scfi/x86_64/scfi-cfg-3.l: New test.
* gas/scfi/x86_64/scfi-cfg-3.s: New test.
* gas/scfi/x86_64/scfi-x86-64.exp: Add new test.
It has always been looking a little odd to me that this was done deep
in cpu_flags_match(). Move it to match_template() itself - there's no
need to do anything complex when encountering such a template while it
cannot possibly be used.
1) Without -msse2avx we unconditionally honor REX.W. Hence we ought to
also do so with -msse2avx, converting to VEX.W.
2) {rex} doesn't prevent conversion to VEX encodings. Thus {rex2}
shouldn't either.
Once properly set, it's only ever holding the same value as "radix".
Even if there was some plan with it, that plan hasn't made it anywhere
in over 20 years.
I don't view it as sensible to be more lax when it comes to references
to (uses of) such labels compared to their definition: The latter has
been limited to decimal numerics, while the former permitted any radix.
Beyond that leading zeroes on such labels aren't helpful either. Imo
labels and their use sites would better match literally, to avoid
confusion.
As it turns out, one z80 testcase actually had such an odd use of labels
where definition and use don't match in spelling. That testcase is being
adjusted accordingly.
While there also adjust a comment on a local variable in
integer_constant().
For one 0afc614c99 ("x86: Warn .insn instruction with length > 15
bytes") introduced a .insn use involving a slash; such tests need to
have --divide passed to gas.
And then 5bc71c2a6b ("x86-64: Add R_X86_64_CODE_6_GOTTPOFF") broke
BFD_RELOC_X86_64_GOTTPOFF conversion to R_X86_64_CODE_4_GOTTPOFF, by
adding respective code in a section guarded by
generate_relax_relocations (the case of that not being required there
was limited to 32-bit object files). Re-arrange that block of code to
check generate_relax_relocations later.
This relaxation is effective for both macro instructions (call36, tail36)
and explicit relocation instructions (pcaddu18i + jirl).
call36 f -> bl f
R_LARCH_CALL36 -> R_LARCH_B26
tail36 $t0, f -> b f
R_LARCH_CALL36 -> R_LARCH_B26
The following instructions are added in this patch:
- ADDPT (predicated): Add checked pointer vectors (predicated).
- ADDPT (unpredicated): Add checked pointer vectors (unpredicated).
- SUBPT (predicated): Subtract checked pointer vectors (predicated).
- SUBPT (unpredicated): Subtract checked pointer vectors (unpredicated).
- MADPT: Multiply-add checked pointer vectors, writing multiplicand
- MLAPT: Multiply-add checked pointer vectors, writing addend
These instructions are part of Checked Pointer Arithmetic extension
and are enabled when both CPA and SVE are enabled. To achieve this,
both flag "+sve" and "+cpa" should be active.
This patch adds assembler and disassembler support for these instructions
with relevant checks. Tests are included as well.
Regression tested on the aarch64-none-linux-gnu target and no regressions
have been found.
