gas/
* config/tc-mips.c (mips_set_options): Rename gp32 to gp throughout.
(HAVE_32BIT_GPRS, HAVE_64BIT_GPRS): Remove. Re-implement via GPR_SIZE.
(HAVE_32BIT_FPRS, HAVE_64BIT_FPRS): Remove. Re-implement via FPR_SIZE.
(GPR_SIZE, FPR_SIZE): New macros. Use throughout.
In mi_interpreter_init, multiple MI consoles/channels are created and a quoting
character is given. In mi_console_raw_packet, we check if the value is not 0
to decide if we should quote the string, but we don't use the value. It is
hardcoded to ". We might never use another quoting character than an actual
quote, but I suggest we change it, for correctness. There is not visible
behavior change.
I changed the latest fputs_unfiltered changed to fputc_unfiltered just to stay
consistent.
gdb/ChangeLog:
2014-05-12 Simon Marchi <simon.marchi@ericsson.com>
* mi/mi-console.c (mi_console_raw_packet): Use the value from
mi_console->quote as the quoting character.
ld:
* ldlang.c (lang_finish): Don't call bfd_link_hash_table_free here.
(output_bfd_hash_table_free_fn): New variable.
(open_output): Save the _bfd_link_hash_table_free function for the
output_bfd into output_bfd_hash_table_free_fn.
* ldmain.c (ld_cleanup): If set, call output_bfd_hash_table_free_fn
on link_info.hash.
* ldlang.h (output_bfd_hash_table_free_fn): Declare.
ld/testsuite:
* ld-mmix/wrap1.d, ld-mmix/wrap1a.s, ld-mmix/wrap1b.s,
ld-mmix/wrap1c.s, ld-mmix/wrap2.d, ld-mmix/wrap3.d,
ld-mmix/wrap3a.s, ld-mmix/wrap3b.s, ld-mmix/wrap4.d: New
tests.
gas/
* config/tc-mips.c (mips_set_options): Rename fp32 field to fp.
Update fp32 == 0 to fp == 64 and fp32 == 1 to fp != 64 throughout.
(file_mips_gp32, file_mips_fp32, file_mips_soft_float,
file_mips_single_float, file_mips_isa, file_mips_arch): Merge into
one struct...
(file_mips_opts): Here. New static global. Update throughout.
(mips_opts): Update defaults for gp32 and fp.
* cp-demangle.c (struct d_component_stack): New structure.
(struct d_print_info): New field component_stack.
(d_print_init): Initialize the above.
(d_print_comp_inner): Renamed from d_print_comp.
Do not restore template stack if it would cause a loop.
(d_print_comp): New function.
* testsuite/demangle-expected: New test cases.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210205 138bc75d-0d04-0410-961f-82ee72b054a4
libiberty/
* cp-demangle.c (d_demangle_callback): Put an abort call in place,
to help the compiler.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@207200 138bc75d-0d04-0410-961f-82ee72b054a4
I think "set debugvarobj" has the wrong name.
It ought to be "set debug varobj", like gdb's other debug settings.
This patch makes the change.
I chose not to install deprecated aliases, since this is only a debug
setting; but if someone feels strongly about it I will add them.
Built and regtested on x86-64 Fedora 20.
2014-04-29 Tom Tromey <tromey@redhat.com>
* varobj.c (_initialize_varobj): Rename to "set debug varobj" and
"show debug varobj".
2014-04-29 Tom Tromey <tromey@redhat.com>
* gdb.texinfo (Debugging Output): Rename to "set debug varobj" and
"show debug varobj".
* msp430-sim.c (sim_open): Do not allocate memory over the
hardware multiply registers.
(get_op): Add support for reads from the hardware multiply
registers.
(put_op): Add support for writes to the hardware multiply
registers.
(msp430_step_once): Add support for the RETI instruction used by
the CPUX architecture.
This adds support for the load-link/store-conditional
l.lwa/l.swa atomic instructions.
The support is added in such way, that the cpu description not
only describes the mnemonics, but also the functionality.
A couple of fixes to typos in nearby/related code are also snuck
into this.
cpu/
* or1korbis.cpu (h-atomic-reserve): New hardware.
(h-atomic-address): Likewise.
(insn-opcode): Add opcodes for LWA and SWA.
(atomic-reserve): New operand.
(atomic-address): Likewise.
(l-lwa, l-swa): New instructions.
(l-lbs): Fix typo in comment.
(store-insn): Clear atomic reserve on store to atomic-address.
Fix register names in fmt field.
opcodes/
* or1k-desc.c: Regenerated.
* or1k-desc.h: Likewise.
* or1k-opc.c: Likewise.
* or1k-opc.h: Likewise.
* or1k-opinst.c: Likewise.
R_XTENSA_DIFF relocation offsets are in fact signed. Treat them as such.
Add testcase that examines ld behaviour on R_XTENSA_DIFF relocation
changing sign during relaxation.
2014-05-02 Volodymyr Arbatov <arbatov@cadence.com>
David Weatherford <weath@cadence.com>
Max Filippov <jcmvbkbc@gmail.com>
bfd/
* elf32-xtensa.c (relax_section): treat R_XTENSA_DIFF* relocations as
signed.
gas/
* config/tc-xtensa.c (md_apply_fix): mark BFD_RELOC_XTENSA_DIFF*
fixups as signed.
ld/testsuite/
* ld-xtensa/diff_overflow.exp, * ld-xtensa/diff_overflow1.s,
* ld-xtensa/diff_overflow2.s: Add test for DIFF* relocation
signedness and overflow checking.
gdb/Changelog:
* aarch64-tdep.c (aarch64_software_single_step): New function.
(aarch64_gdbarch_init): Handle single stepping of atomic sequences
with aarch64_software_single_step.
gdb/testsuite/ChangeLog:
* gdb.arch/aarch64-atomic-inst.c: New file.
* gdb.arch/aarch64-atomic-inst.exp: New file.
This patch firstly adds support for mips32r3 mips32r5, mips64r3
and mips64r5. Secondly it adds support for the eretnc instruction.
ChangeLog:
bfd/
* aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3,
mips32r5 and mips64r5.
* archures.c (bfd_architecture): Likewise.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (arch_info_struct): Likewise.
* elfxx-mips.c (mips_set_isa_flags): Likewise.
gas/
* tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3
and mips64r5.
(ISA_HAS_64BIT_FPRS): Likewise.
(ISA_HAS_ROR): Likewise.
(ISA_HAS_ODD_SINGLE_FPR): Likewise.
(ISA_HAS_MXHC1): Likewise.
(hilo_interlocks): Likewise.
(md_longopts): Likewise.
(ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5.
(ISA_HAS_DROR): Likewise.
(options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and
OPTION_MIPS64R5.
(mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
(md_parse_option): Likewise.
(s_mipsset): Likewise.
(mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3
and mips64r5. Also change p5600 entry to be mips32r5.
* configure.in: Add support for mips32r3, mips32r5, mips64r3 and
mips64r5.
* configure: Regenerate.
* doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and
-mips64r5 command line options.
* doc/as.texinfo: Likewise.
gas/testsuite/
* gas/mips/mips.exp: Add MIPS32r5 tests. Also add the mips32r3,
mips32r5, mips64r3 and mips64r5 isas to the testsuite.
* gas/mips/r5.s: New test.
* gas/mips/r5.d: Likewise.
include/opcode/
* mips.h (INSN_ISA_MASK): Updated.
(INSN_ISA32R3): New define.
(INSN_ISA32R5): New define.
(INSN_ISA64R3): New define.
(INSN_ISA64R5): New define.
(INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
(mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
mips64r5.
(INSN_UPTO32R3): New define.
(INSN_UPTO32R5): New define.
(INSN_UPTO64R3): New define.
(INSN_UPTO64R5): New define.
(ISA_MIPS32R3): New define.
(ISA_MIPS32R5): New define.
(ISA_MIPS64R3): New define.
(ISA_MIPS64R5): New define.
(CPU_MIPS32R3): New define.
(CPU_MIPS32R5): New define.
(CPU_MIPS64R3): New define.
(CPU_MIPS64R5): New define.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
(I34): New define.
(I36): New define.
(I66): New define.
(I68): New define.
* mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
mips64r5.
(parse_mips_dis_option): Update MSA and virtualization support to
allow mips64r3 and mips64r5.
This fixes an issue with Mark Shinwell's "Rearrange MIPS INSN* masks" patch
(https://sourceware.org/ml/binutils/2007-11/msg00231.html). In the patch
the pref instruction had its membership flags changed from I4|I32|G3 to
I4_32|G3. Unfortunately G3 was defined as being I4, which made the actual
expanded flags as: I4|I32|I4 and therefore the membership flags should have
been I4_32. Since the patch was committed G3 was redefined to be I4|EE. This
fix just removes I4 from G3 making the expanded membership flags for pref as
I4_32|EE.
ChangeLog:
opcodes/
* mips-opc.c (G3): Remove I4.
Hi,
I recently see the fail in dwzbuildid.exp below on some targets,
(gdb) print the_int
No symbol "the_int" in current context.
(gdb) FAIL: gdb.dwarf2/dwzbuildid.exp: mismatch: print the_int
Looks the pattern expects to see "No symbol table is loaded", which
is emitted in c-exp.y,
variable: name_not_typename
....
if (msymbol.minsym != NULL)
write_exp_msymbol (pstate, msymbol);
else if (!have_full_symbols () && !have_partial_symbols ())
error (_("No symbol table is loaded. Use the \"file\" command."));
else
error (_("No symbol \"%s\" in current context."),
copy_name ($1.stoken));
it is expected to have no full symbols nor partial symbols, but something
brings full symbols or partial symbols in. I added "maint info symtabs"
and "maint info psymtabs" in dwzbuildid.exp, and it shows symbols are from
ld.so, which has debug information. Then, I reproduce the fail like this,
$ make check RUNTESTFLAGS="CFLAGS_FOR_TARGET='-Wl,-rpath=${glibc_build}:${glibc_build}/math -Wl,--dynamic-linker=${glibc_build}/elf/ld.so' dwzbuildid.exp"
${glibc_build} is the glibc build tree. Debug information is not striped,
so the test fail. However, if I strip debug information from libc.so, libm.so
and ld.so. The test passes.
This patch is to relax the pattern to match the both cases that glibc build
has and has not debug information.
gdb/testsuite:
2014-05-07 Yao Qi <yao@codesourcery.com>
* gdb.dwarf2/dwzbuildid.exp: Match output "No symbol "the_int" in
current context" too.
is no PLT.
gold/
PR gold/16900
* i386.cc (Output_data_got_plt_i386): New class.
(Output_data_plt_i386::Output_data_plt_i386): Change type of got_plt
parameter. Change all callers.
(Output_data_plt_i386::layout_): Remove.
(Output_data_plt_i386::got_plt_): Change type.
(Target_i386::got_plt_): Change type. Change all references.
(Target_i386::got_section): Create instance of new class.
(Output_data_got_plt_i386::do_write): New function.
* x86_64.cc (Output_data_got_plt_x86_64): New class.
(Output_data_plt_x86_64::Output_data_plt_x86_64): Change type of got_plt
parameter. Change all callers.
(Output_data_plt_x86_64::layout_): Remove.
(Output_data_plt_x86_64::got_plt_): Change type.
(Target_x86_64::got_plt_): Change type. Change all references.
(Target_x86_64::got_section): Create instance of new class.
(Output_data_got_plt_x86_64::do_write): New function.
(Output_data_plt_x86_64::do_write): Don't write reserved words in GOT.
(Target_x86_64<size>::init_got_plt_for_update): Create instance of new
class.
* elfxx-mips.h (elfxx-mips.h): Declare.
* elfxx-mips.c (mips_elf_merge_obj_attributes): Use it to report
Tag_GNU_MIPS_ABI_FP mismatches.
(_bfd_mips_fp_abi_string): New function.
