mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-24 12:35:55 +08:00
232bfb8644
3492 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Andreas Krebbel
|
f47998d69f |
S/390: Support vector alignment hints
This patch adds the vector alignment hints to the vector load and store instructions as documented in the IBM z14 Principles of Operations manual: http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr011.pdf opcodes/ChangeLog: 2018-10-23 Andreas Krebbel <krebbel@linux.ibm.com> * s390-opc.txt: Add vector load/store instructions with additional alignment parameter. gas/ChangeLog: 2018-10-23 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (md_gather_operands): Fix for optional operands following memory addresses. * testsuite/gas/s390/zarch-arch12.d: Add regexp checks for new instruction variants. * testsuite/gas/s390/zarch-arch12.s: Emit new instruction variants. |
||
Alan Modra
|
1f38083f42 |
gas simple-forward test
Tests that target md_apply_fix can handle fixups that have resolved down to a constant and thus do not need relocations. Also a fix for eqv-dot xfails. * testsuite/gas/all/simple-forward.d, * testsuite/gas/all/simple-forward.s: New test. * testsuite/gas/all/gas.exp: Run it. * testsuite/gas/all/eqv-dot.d: xfail tic30 and tic54x. |
||
|
Alan Modra
|
e1748c54a2 |
Apply alpha BFD_RELOC_8 fixups
* config/tc-alpha.c (md_apply_fix): Handle BFD_RELOC_8 for fixups without a symbol. * testsuite/gas/all/gas.exp: Don't xfail forward test here.. * testsuite/gas/all/forward.d: ..do so here, removing alpha. |
||
|
Alan Modra
|
e4c2619ad1 |
PR23800, .eqv doesn't always defer expression evaluation
.eqv (and ==) ought not simplify expressions involving dot or other symbols set by .eqv. If such simplification occurs, the value of dot will be that at the assignment rather than at the place where the symbol is used. PR 23800 * expr.c (expr): Don't simplify expressions involving forward_ref symbols when mode is expr_defer. * config/tc-spu.c (spu_cons): Parse expression using normal expression evaluation if @ppu is not detected. * testsuite/gas/all/eqv-dot.d, * testsuite/gas/all/eqv-dot.s: New test. * testsuite/gas/all/gas.exp: Run it. |
||
Tamar Christina
|
bacb77d018 |
Arm: Skip new binary decode tests on pe targets
The two new test I added require the use of the ".inst" directive which the PE targets don't support. Because of that I excluded *-unknown-pe but the mask needs to be wider. I am now excluding *-*-pe. gas/ChangeLog: * testsuite/gas/arm/undefined-insn-arm.d: Widen pe skip. * testsuite/gas/arm/undefined-insn-thumb.d: Likewise. |
||
|
Tamar Christina
|
0b347048e7 |
Arm: Fix disassembler crashing on -b binary when thumb file and thumb not forced.
The disassembler for Arm has some aborts in it in places it assumes can never be reached. Under normal circumstances they indeed cannot be reached because the right options are selected from the ARM attributes in the ELF file. However when disassembling with -b binary then if you do not get the options right the disassembler just aborts. This changes it so it just prints how it was trying to interpret the instruction and prints UNKNOWN instructions next to it. This way the user has an idea of what's going. gas/ChangeLog: * testsuite/gas/arm/undefined-insn-arm.d: New test. * testsuite/gas/arm/undefined-insn-thumb.d: New test. * testsuite/gas/arm/undefined-insn.s: New test. opcodes/ChangeLog: * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode. (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode. (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them. |
||
Fredrik Noring
|
33d64ca5db |
This set of changes clarifies the conditions for the R5900 short loop fix and extends its test with the border cases of six and seven instructions.
* testsuite/gas/mips/r5900.s: Extend the R5900 short loop fix test with border cases. * testsuite/gas/mips/r5900.d: Add extra expected disassembly. * config/tc-mips.c (can_swap_branch_p): Clarify the R5900 short loop hardware bug conditions. Correct note on the R5900 instruction count short loop fix. |
||
Matthew Malcomson
|
66e6f0b760 |
AArch64: Fix error checking for SIMD udot (by element)
Committed on behalf of Matthew Malcomson:
The SIMD UDOT instruction assembly has an unusual operand that selects a single
32 bit element with the mnemonic 4B.
This unusual mnemonic is handled by a special operand qualifier and associated
qualifier data in `aarch64_opnd_qualifiers`.
The current qualifier data describes 4 1-byte elements with the structure
{1, 4, 0x0, "4b", OQK_OPD_VARIANT}
This makes sense, as the instruction does work on 4 1-byte elements, however
some logic in the `operand_general_constraint_met_p` makes assumptions about
the range of index allowed when selecting a SIMD_ELEMENT depending on element
size.
That function reasons that e.g. in order to select a byte-sized element in a 16
byte V register an index must allow selection of one of the 16 elements and
hence its range will be in [0,15].
This reasoning breaks with the above description of a 4 part selection of 1
byte elements and allows an index outside the valid [0,3] range, triggering an
assert later on in the program in `aarch64_ins_reglane`.
vshcmd: > echo 'udot v0.2s, v1.8b, v2.4b[4]' | ../src/binutils-build/gas/as-new -march=armv8.4-a
as-new: ../../binutils-gdb/opcodes/aarch64-asm.c:134: aarch64_ins_reglane: Assertion `reglane_index < 4' failed.
{standard input}: Assembler messages:
{standard input}:1: Internal error (Aborted).
Please report this bug.
This patch changes the operand qualifier data so that it describes a single
32 bit element.
{4, 1, 0x0, "4b", OQK_OPD_VARIANT}
Hence the calculation in `operand_general_constraint_met_p` provides the
correct answer and the usual error checking machinery is used.
vshcmd: > echo 'udot v0.2s, v1.8b, v2.4b[4]' | ../src/binutils-build/gas/as-new -march=armv8.4-a
{standard input}: Assembler messages:
{standard input}:1: Error: register element index out of range 0 to 3 at operand 3 -- `udot v0.2s,v1.8b,v2.4b[4]'
|
||
Jan Beulich
|
a9597defaf |
x86: add {,V}MOVQ cases to xmmword test
I had overlooked these when putting together the original test. |
||
Sudakshina Das
|
104fefeebb |
[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRS
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds support for the mitigation for Spectre Variant 4 by adding the PSTATE bit SSBS which are accessible using MSR and MRS instructions. Although this is a mandatory addition to the ARMv8.5-A, it is permitted to be added to any version of the ARMv8 architecture. This is enabled using the command line option of +ssbs for older versions. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SSBS): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (operand_general_constraint_met_p): Add SSBS in the check for one-bit immediate. (aarch64_sys_regs): New entry for SSBS. (aarch64_sys_reg_supported_p): New check for above. (aarch64_pstatefields): New entry for SSBS. (aarch64_pstatefield_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add new "ssbs". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/ssbs-illegal1.d: New test. * testsuite/gas/aarch64/ssbs-illegal1.l: New test. * testsuite/gas/aarch64/ssbs-illegal2.d: New test. * testsuite/gas/aarch64/ssbs-illegal2.l: New test. * testsuite/gas/aarch64/ssbs.s: New test. * testsuite/gas/aarch64/ssbs1.d: Test with +ssbs * testsuite/gas/aarch64/ssbs2.d: Test with armv8.5-a. |
||
|
Sudakshina Das
|
a97330e723 |
[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New. (AARCH64_FEATURE_ID_PFR2): New. (AARCH64_ARCH_V8_5): Add both by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs): New entries for scxtnum_el[0,1,2,3,12] and id_pfr2_el1. (aarch64_sys_reg_supported_p): New checks for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test registers scxtnum_el[0,1,2,3,12] and id_pfr2_el1. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. |
||
|
Sudakshina Das
|
ff6054520c |
[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification) The Branch Target Identification instructions (BTI) are allocated to existing HINT space, using HINT numbers 32, 34, 36, 38, such that bits[7:6] of the instruction identify the compatibility of the BTI instruction to different branches. BTI {<targets>} where <targets> one of the following, specifying which type of indirection is allowed: j : Can be a target of any BR Xn isntruction. c : Can be a target of any BLR Xn and BR {X16|X17}. jc: Can be a target of any free branch. A BTI instruction without any <targets> is the strictest of all and can not be a target of nay free branch. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_BTI): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default. (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET. (HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to define HINT #imm values. (HINT_OPD_JC, HINT_OPD_NULL): Likewise. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New. (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag with the hint immediate. * aarch64-opc.c (aarch64_hint_options): New entries for c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI. (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET while checking for HINT_OPD_F_NOPRINT flag. * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to extract value. * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New. (aarch64_opcode_table): Add entry for BTI. (AARCH64_OPERANDS): Add new description for BTI targets. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_bti_operand): New. (process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET. (parse_operands): Likewise. * testsuite/gas/aarch64/system.d: Update for BTI. * testsuite/gas/aarch64/bti.s: New. * testsuite/gas/aarch64/bti.d: New. * testsuite/gas/aarch64/illegal-bti.d: New. * testsuite/gas/aarch64/illegal-bti.l: New. |
||
|
Sudakshina Das
|
af4bcb4ce6 |
[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructions
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) The encodings can be found in the System Register XML. This patch adds the following: MSR Xn, RNDR MSR Xn, RNDRRS These are optional instructions in ARMv8.5-A and hence the new +rng is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_RNG): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs): New entries for rndr and rndrrs. (aarch64_sys_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): New "rng" option. * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/sysreg-4.s: Test both instructions. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. |
||
|
Sudakshina Das
|
3fd229a447 |
[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys) This patch adds the DC CVADP instruction. Since this has a separate identification mechanism a new feature bit is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp. (aarch64_sys_ins_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test instruction. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. |
||
|
Sudakshina Das
|
2ac435d466 |
[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order) This patch adds the prediction restriction instructions (that is, cfp, dvp, cpp). These instructions are retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a new +predres which can be used by the older architectures. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default. (aarch64_opnd): Add AARCH64_OPND_SYSREG_SR. (aarch64_sys_regs_sr): Declare new table. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-dis.c (aarch64_ext_sysins_op): Add case for AARCH64_OPND_SYSREG_SR. * aarch64-opc.c (aarch64_print_operand): Likewise. (aarch64_sys_regs_sr): Define table. (aarch64_sys_ins_reg_supported_p): Check for RCTX with AARCH64_FEATURE_PREDRES. * aarch64-tbl.h (aarch64_feature_predres): New. (PREDRES, PREDRES_INSN): New. (aarch64_opcode_table): Add entries for cfp, dvp and cpp. (AARCH64_OPERANDS): Add new description for SYSREG_SR. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New. (parse_operands): Add entry for AARCH64_OPND_SYSREG_SR. (md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh with aarch64_sys_regs_sr. (aarch64_features): Add new "predres" option for older architectures. * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/sysreg-4.s: New. * testsuite/gas/aarch64/sysreg-4.d: New. * testsuite/gas/aarch64/illegal-sysreg-4.d: New. * testsuite/gas/aarch64/illegal-sysreg-4.l: New. * testsuite/gas/aarch64/predres.s: New. * testsuite/gas/aarch64/predres.d: New. |
||
|
Sudakshina Das
|
68dfbb92ef |
[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-A
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order) This instruction is retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence a new command line option of "+sb" is added for older architectures. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SB): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_sb): New. (SB, SB_INSN): New. (aarch64_opcode_table): Add entry for sb. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (aarch64_features): Add new "sb" option for older architectures. * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/sb.s: New. * testsuite/gas/aarch64/sb.d: New. |
||
|
Sudakshina Das
|
13c60ad7e1 |
[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order) This patch adds the data processing instructions that are new to ARMv8.5-A. 1) There are 2 instructions: xaflag, axflag, that are added to manipulate the states of the flag and are used to convert between the Arm representation and the fcmp representation. 2) The other instructions are rounding instructions which have 8 versions based on whether the floating-point number is a Single-Precision or Double-Precision number, whether the target integer is a 32-bit or 64-bit integer and whether the rounding mode is the ambient rounding mode or to zero. Each of these instruction is available in both Scalar and Vector forms. Since both 1) and 2) have separate identification mechanism and it is permissible that a ARMv8.4 compliant implementation may include any arbitrary subset of the ARMv8.5 features unless otherwise specified, new feature bits are added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New. (AARCH64_FEATURE_FRINTTS): New. (AARCH64_ARCH_V8_5): Add both by default. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-tbl.h (aarch64_feature_flagmanip): New. (aarch64_feature_frintts): New. (FLAGMANIP, FRINTTS): New. (aarch64_opcode_table): Add entries for xaflag, axflag and frint[32,64][x,z] instructions. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/armv8_5-a-dp.s: New. * testsuite/gas/aarch64/armv8_5-a-dp.d: New. |
||
H.J. Lu
|
a4e78aa5fe |
x86: Add Intel ENCLV to assembler and disassembler
gas/ * testsuite/gas/i386/se1.s: Add enclv. * testsuite/gas/i386/x86-64-se1.s: Likewise. * testsuite/gas/i386/se1.d: Updated. * testsuite/gas/i386/x86-64-se1.d: Likewise. opcodes/ * i386-dis.c (rm_table): Add enclv. * i386-opc.tbl: Add enclv. * i386-tbl.h: Regenerated. |
||
|
Sudakshina Das
|
dad0c3bfb5 |
[Arm, 3/3] Add Execution and Data Prediction instructions for AArch32
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) This patch adds the Execution and Data Prediction Restriction instructions (that is, cfprctx, dvprxtc, cpprctx). These are all aliases to MCR and are disassembled as such. This instruction is retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a new +predres for older versions of the architecture. *** include/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * opcode/arm.h (ARM_EXT2_PREDRES): New. (ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default. *** gas/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (arm_ext_predres): New. (insns): Add new cfprctx, dvprctx and cpprctx instructions. (arm_extensions): Add "predres". * doc/c-arm.texi: Document the above. * testsuite/gas/arm/predres-bad.d: New test. * testsuite/gas/arm/predres-bad.l: New test. * testsuite/gas/arm/predres.s: New test. * testsuite/gas/arm/predres1.d: New test. * testsuite/gas/arm/predres2.d: New test. |
||
|
Sudakshina Das
|
7fadb25d6f |
[Arm, 2/3] Add instruction SB for AArch32
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) This patch adds the instruction SB. This instruction is retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a new "+sb" for older archtectures. *** include/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * opcode/arm.h (ARM_EXT2_SB): New. (ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default. *** opcodes/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (arm_opcodes): Add sb. (thumb32_opcodes): Likewise. *** gas/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (arm_ext_sb): New. (insns): Add new sb instruction. (arm_extensions): Add "sb". * doc/c-arm.texi: Document the above. * testsuite/gas/arm/sb-bad.d: New test. * testsuite/gas/arm/sb-bad.l: New test. * testsuite/gas/arm/sb-thumb1.d: New test. * testsuite/gas/arm/sb-thumb2.d: New test. * testsuite/gas/arm/sb.s: New test. * testsuite/gas/arm/sb1.d: New test. * testsuite/gas/arm/sb2.d: New test. |
||
|
Sudakshina Das
|
23f233a595 |
[Arm, 1/3] Add -march=armv8.5-a and related internal feature macros to AArch32
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) This is the first of the patch series and adds -march=armv8.5-a and other internal feature marcos needed for it. *** gas/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (arm_archs): New entry for armv8.5-a. (cpu_arch_ver): Likewise. * doc/c-arm.texi: Add documentation for the same. * testsuite/gas/arm/attr-march-armv8_5-a.d: New. *** include/ChnageLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * opcode/arm.h (ARM_EXT2_V8_5A): New. (ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New. |
||
Richard Henderson
|
07f5f4c683 |
or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and overflow float. Changes to the instructions are made in the .cpu file, then we regenerate the binutils and sim files. The changes also required a few fixups for tests and additional sim helpers. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> Stafford Horne <shorne@gmail.com> * or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU. (insn-opcode-alu-regreg): Add opcodes for MULD and MULDU. (l-mul): Fix overflow support and indentation. (l-mulu): Fix overflow support and indentation. (l-muld, l-muldu, l-msbu, l-macu): New instructions. (l-div); Remove incorrect carry behavior. (l-divu): Fix carry and overflow behavior. (l-mac): Add overflow support. (l-msb, l-msbu): Add carry and overflow support. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> Stafford Horne <shorne@gmail.com> * or1k-desc.c: Regenerate. * or1k-desc.h: Regenerate. * or1k-opc.c: Regenerate. * or1k-opc.h: Regenerate. * or1k-opinst.c: Regenerate. sim/common/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * cgen-ops.h (ADDCFDI): New function, add carry flag DI variant. (ADDOFDI): New function, add overflow flag DI variant. (SUBCFDI): New function, subtract carry flag DI variant. (SUBOFDI): New function, subtract overflow flag DI variant. sim/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * or1k/cpu.h: Regenerate. * or1k/decode.c: Regenerate. * or1k/decode.h: Regenerate. * or1k/model.c: Regenerate. * or1k/sem-switch.c: Regenerate. * or1k/sem.c: Regenerate: sim/testsuite/sim/or1k/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * div.S: Fix tests to match correct overflow/carry semantics. * mul.S: Likewise. gas/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * testsuite/gas/or1k/allinsn.s: Add instruction tests for l.muld, l.muldu, l.macu, l.msb, l.msbu. * testsuite/gas/or1k/allinsn.d: Add test results for new instructions. |
||
Stafford Horne
|
c8e98e3692 |
or1k: Add the l.adrp insn and supporting relocations
This patch adds the new instruction and relocation as per proposal: https://openrisc.io/proposals/ladrp This is to be added to the spec in an upcoming revision. The new instruction l.adrp loads the page offset of the current instruction offset by a 21-bit immediate shifted left 13-bits. This is meant to be used with a 13-bit lower bit page offset. This allows us to free up the got register r16. l.adrp r3, foo l.ori r4, r3, po(foo) l.lbz r5, po(foo)(r3) l.sb po(foo)(r3), r6 The relocations we add are: - BFD_RELOC_OR1K_PLTA26 For PLT jump relocation with PLT entry asm: plta() implemented using l.ardp, meaning no need for r16 (the GOT reg) - BFD_RELOC_OR1K_GOT_PG21 Upper 21-bit Page offset got address asm: got() - BFD_RELOC_OR1K_TLS_GD_PG21 Upper 21-bit Page offset with TLS General asm: tlsgd() Dynamic calculation - BFD_RELOC_OR1K_TLS_LDM_PG21 Upper 21-bit Page offset with TLS local asm: tlsldm() dynamic calculation - BFD_RELOC_OR1K_TLS_IE_PG21 Upper 21-bit Page offset with TLS Initial asm: gottp() Executable calculation - BFD_RELOC_OR1K_PCREL_PG21 Default relocation for disp21 (l.adrp instructions) - BFD_RELOC_OR1K_LO13 low 13-bit page offset relocation asm: po() i.e. mem loads, addi etc - BFD_RELOC_OR1K_SLO13 low 13-bit page offset relocation asm: po() i.e. mem stores, with split immediate - BFD_RELOC_OR1K_GOT_LO13, low 13-bit page offset with GOT calcs asm: gotpo() - BFD_RELOC_OR1K_TLS_GD_LO13 Lower 13-bit offset with TLS GD calcs asm: tlsgdpo() - BFD_RELOC_OR1K_TLS_LDM_LO13 Lower 13-bit offset with TLS LD calcs asm: tlsldmpo() - BFD_RELOC_OR1K_TLS_IE_LO13 Lower 13-bit offset with TLS IE calcs asm: gottppo() bfd/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * bfd-in2.h: Regenerated. * elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26. (or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13, BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26. (elf_or1k_link_hash_table): Add field saw_plta. (or1k_final_link_relocate): Add value calculations for new relocations. (or1k_elf_relocate_section): Add section relocations for new relocations. (or1k_write_plt_entry): New function. (or1k_elf_finish_dynamic_sections): Add support for PLTA relocations using new l.adrp instruction. Cleanup PLT relocation code generation. * libbfd.h: Regenerated. * reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13, BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_TLS_IE_LO13. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k.opc (parse_disp26): Add support for plta() relocations. (parse_disp21): New function. (or1k_rclass): New enum. (or1k_rtype): New enum. (or1k_imm16_relocs): Define new PO and SPO relocation mappings. (parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations. (parse_imm16): Add support for the new 21bit and 13bit relocations. * or1korbis.cpu (f-disp26): Don't assume SI. (f-disp21): New pc-relative 21-bit 13 shifted to right. (insn-opcode): Add ADRP. (l-adrp): New instruction. gas/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21, BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21, BFD_RELOC_OR1K_TLS_IE_LO13. * testsuite/gas/or1k/allinsn.s: Add test for l.adrp. * testsuite/gas/or1k/allinsn.d: Add test results for new instructions. * testsuite/gas/or1k/reloc-1.s: Add tests to generate R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13 relocations. * testsuite/gas/or1k/reloc-1.d: Add relocation results for tests. * testsuite/gas/or1k/reloc-2.s: Add negative tests for store to gotpo(). * testsuite/gas/or1k/reloc-2.l: Add expected error test results. ld/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/ld-or1k/or1k.exp: Add test cases for plt generation. * testsuite/ld-or1k/plt1.dd: New file. * testsuite/ld-or1k/plt1.s: New file. * testsuite/ld-or1k/plt1.x.dd: New file. * testsuite/ld-or1k/plta1.dd: New file. * testsuite/ld-or1k/plta1.s: New file. * testsuite/ld-or1k/pltlib.s: New file. include/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k-asm.c: Regenerated. * or1k-desc.c: Regenerated. * or1k-desc.h: Regenerated. * or1k-dis.c: Regenerated. * or1k-ibld.c: Regenerated. * or1k-opc.c: Regenerated. * or1k-opc.h: Regenerated. * or1k-opinst.c: Regenerated. |
||
|
Richard Henderson
|
1c4f3780f7 |
or1k: Add relocations for high-signed and low-stores
This patch adds the following target relocations: - BFD_RELOC_HI16_S High 16-bit relocation, for used with signed asm: ha() lower. - BFD_RELOC_HI16_S_GOTOFF High 16-bit GOT offset relocation for local asm: gotoffha() symbols, for use with signed lower. - BFD_RELOC_OR1K_TLS_IE_AHI16 High 16-bit TLS relocation with initial asm: gottpoffha() executable calculation, for use with signed lower. - BFD_RELOC_OR1K_TLS_LE_AHI16 High 16-bit TLS relocation for local executable asm: tpoffha() variables, for use with signed lower. - BFD_RELOC_OR1K_SLO16 Split lower 16-bit relocation, used with asm: lo() OpenRISC store instructions. - BFD_RELOC_OR1K_GOTOFF_SLO16 Split lower 16-bit GOT offset relocation for asm: gotofflo() local symbols, used with OpenRISC store instructions. - BFD_RELOC_OR1K_TLS_LE_SLO16 Split lower 16-bit relocation for TLS local asm: tpofflo() executable variables, used with OpenRISC store instructions. bfd/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> Stafford Horne <shorne@gmail.com> * bfd-in2.h: Regenerated. * elf32-or1k.c (N_ONES): New macro. (or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow. Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF, R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16. (or1k_reloc_map): Add entries for BFD_RELOC_HI16_S, BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF, BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16, BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_LE_SLO16. (or1k_reloc_type_lookup): Change search loop to start ad index 0 and also check results before returning. (or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index limit. (or1k_final_link_relocate): New function. (or1k_elf_relocate_section): Add support for new AHI and SLO relocations. Use or1k_final_link_relocate instead of generic _bfd_final_link_relocate. (or1k_elf_check_relocs): Add support for new AHI and SLO relocations. * reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16, BFD_RELOC_OR1K_TLS_LE_SLO16. Remove unused BFD_RELOC_OR1K_GOTOFF_HI16 and BFD_RELOC_OR1K_GOTOFF_LO16. * libbfd.h: Regenerated. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k.opc: Add RTYPE_ enum. (INVALID_STORE_RELOC): New string. (or1k_imm16_relocs): New array array. (parse_reloc): New static function that just does the parsing. (parse_imm16): New static function for generic parsing. (parse_simm16): Change to just call parse_imm16. (parse_simm16_split): New function. (parse_uimm16): Change to call parse_imm16. (parse_uimm16_split): New function. * or1korbis.cpu (simm16-split): Change to use new simm16_split. (uimm16-split): Change to use new uimm16_split. gas/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation. * testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations. * testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp. * testsuite/gas/or1k/or1k.exp: Add reloc-2 list test. * testsuite/gas/or1k/reloc-1.d: New file. * testsuite/gas/or1k/reloc-1.s: New file. * testsuite/gas/or1k/reloc-2.l: New file. * testsuite/gas/or1k/reloc-2.s: New file. include/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16. ld/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * testsuite/ld-or1k/offsets1.d: New file. * testsuite/ld-or1k/offsets1.s: New file. * testsuite/ld-or1k/or1k.exp: New file. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> * or1k-asm.c: Regenerate. |
||
|
Tamar Christina
|
e66cfcef72 |
AArch64: Add MOVPRFX tests and update testsuite
This patch adds the tests and expected output for each of the conditions where
the MOVPRFX constraint should apply.
The specific test cases are all documented to indicate what the expected
behavior should be.
gas/
* testsuite/gas/aarch64/sve-movprfx_1.d: New test.
* testsuite/gas/aarch64/sve-movprfx_1.s: New test.
* testsuite/gas/aarch64/sve-movprfx_10.d: New test.
* testsuite/gas/aarch64/sve-movprfx_10.l: New test.
* testsuite/gas/aarch64/sve-movprfx_10.s: New test.
* testsuite/gas/aarch64/sve-movprfx_11.d: New test.
* testsuite/gas/aarch64/sve-movprfx_11.s: New test.
* testsuite/gas/aarch64/sve-movprfx_12.d: New test.
* testsuite/gas/aarch64/sve-movprfx_12.s: New test.
* testsuite/gas/aarch64/sve-movprfx_13.d: New test.
* testsuite/gas/aarch64/sve-movprfx_13.l: New test.
* testsuite/gas/aarch64/sve-movprfx_13.s: New test.
* testsuite/gas/aarch64/sve-movprfx_14.d: New test.
* testsuite/gas/aarch64/sve-movprfx_14.l: New test.
* testsuite/gas/aarch64/sve-movprfx_14.s: New test.
* testsuite/gas/aarch64/sve-movprfx_15.d: New test.
* testsuite/gas/aarch64/sve-movprfx_15.l: New test.
* testsuite/gas/aarch64/sve-movprfx_15.s: New test.
* testsuite/gas/aarch64/sve-movprfx_16.d: New test.
* testsuite/gas/aarch64/sve-movprfx_16.s: New test.
* testsuite/gas/aarch64/sve-movprfx_17.d: New test.
* testsuite/gas/aarch64/sve-movprfx_17.l: New test.
* testsuite/gas/aarch64/sve-movprfx_17.s: New test.
* testsuite/gas/aarch64/sve-movprfx_18.d: New test.
* testsuite/gas/aarch64/sve-movprfx_18.l: New test.
* testsuite/gas/aarch64/sve-movprfx_18.s: New test.
* testsuite/gas/aarch64/sve-movprfx_19.d: New test.
* testsuite/gas/aarch64/sve-movprfx_19.s: New test.
* testsuite/gas/aarch64/sve-movprfx_2.d: New test.
* testsuite/gas/aarch64/sve-movprfx_2.l: New test.
* testsuite/gas/aarch64/sve-movprfx_2.s: New test.
* testsuite/gas/aarch64/sve-movprfx_20.d: New test.
* testsuite/gas/aarch64/sve-movprfx_20.l: New test.
* testsuite/gas/aarch64/sve-movprfx_20.s: New test.
* testsuite/gas/aarch64/sve-movprfx_21.d: New test.
* testsuite/gas/aarch64/sve-movprfx_21.s: New test.
* testsuite/gas/aarch64/sve-movprfx_22.d: New test.
* testsuite/gas/aarch64/sve-movprfx_22.l: New test.
* testsuite/gas/aarch64/sve-movprfx_22.s: New test.
* testsuite/gas/aarch64/sve-movprfx_23.d: New test.
* testsuite/gas/aarch64/sve-movprfx_23.l: New test.
* testsuite/gas/aarch64/sve-movprfx_23.s: New test.
* testsuite/gas/aarch64/sve-movprfx_24.d: New test.
* testsuite/gas/aarch64/sve-movprfx_24.l: New test.
* testsuite/gas/aarch64/sve-movprfx_24.s: New test.
* testsuite/gas/aarch64/sve-movprfx_25.d: New test.
* testsuite/gas/aarch64/sve-movprfx_25.l: New test.
* testsuite/gas/aarch64/sve-movprfx_25.s: New test.
* testsuite/gas/aarch64/sve-movprfx_26.d: New test.
* testsuite/gas/aarch64/sve-movprfx_26.l: New test.
* testsuite/gas/aarch64/sve-movprfx_26.s: New test.
* testsuite/gas/aarch64/sve-movprfx_3.d: New test.
* testsuite/gas/aarch64/sve-movprfx_3.l: New test.
* testsuite/gas/aarch64/sve-movprfx_3.s: New test.
* testsuite/gas/aarch64/sve-movprfx_4.d: New test.
* testsuite/gas/aarch64/sve-movprfx_4.l: New test.
* testsuite/gas/aarch64/sve-movprfx_4.s: New test.
* testsuite/gas/aarch64/sve-movprfx_5.d: New test.
* testsuite/gas/aarch64/sve-movprfx_5.s: New test.
* testsuite/gas/aarch64/sve-movprfx_6.d: New test.
* testsuite/gas/aarch64/sve-movprfx_6.l: New test.
* testsuite/gas/aarch64/sve-movprfx_6.s: New test.
* testsuite/gas/aarch64/sve-movprfx_7.d: New test.
* testsuite/gas/aarch64/sve-movprfx_7.l: New test.
* testsuite/gas/aarch64/sve-movprfx_7.s: New test.
* testsuite/gas/aarch64/sve-movprfx_8.d: New test.
* testsuite/gas/aarch64/sve-movprfx_8.l: New test.
* testsuite/gas/aarch64/sve-movprfx_8.s: New test.
* testsuite/gas/aarch64/sve-movprfx_9.d: New test.
* testsuite/gas/aarch64/sve-movprfx_9.l: New test.
* testsuite/gas/aarch64/sve-movprfx_9.s: New test.
|
||
|
Tamar Christina
|
bde90be2cd |
AArch64: Constraint disassembler and assembler changes.
This patch wires in the new constraint verifiers into the assembler and
disassembler. Because of this the MOVPRFX tests have to be split out from the
generic SVE tests into their own tests so warnings can be ignored.
These tests are only intended to test the encoding correctness and not the
constraints.
gas/
* testsuite/gas/aarch64/sve-movprfx.d: New test.
* testsuite/gas/aarch64/sve-movprfx.s: New test.
* testsuite/gas/aarch64/sve.d: Refactor.
* testsuite/gas/aarch64/sve.s: Refactor.
* testsuite/gas/aarch64/sysreg-diagnostic.d: Update.
opcodes/
* aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
* aarch64-dis.c (print_operands): Refactor to take notes.
(print_verifier_notes): New.
(print_aarch64_insn): Apply constraint verifier.
(print_insn_aarch64_word): Update call to print_aarch64_insn.
* aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
|
||
Palmer Dabbelt
|
64a336ac13
|
RISC-V: Add fence.tso instruction
The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso". This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.
I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets. I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.
gas/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* testsuite/gas/riscv/fence-tso.d: New file.
* testsuite/gas/riscv/fence-tso.s: Likewise.
include/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
(MASK_FENCE_TSO): Likewise.
opcodes/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
|
||
Sandra Loosemore
|
ca60b3af44 |
Skip broken assembler test on Windows host.
2018-09-26 Sandra Loosemore <sandra@codesourcery.com> gas/ * testsuite/gas/all/gas.exp: Skip "Output file must be distinct from input" test on Windows host. |
||
|
Andreas Krebbel
|
3d6e0c015a |
S/390: Fix symbolic displacement in lay
Increase the fixup length to 4 for the 20 bit displacement. gas/ChangeLog: 2018-09-25 Andreas Krebbel <krebbel@linux.ibm.com> * config/tc-s390.c (md_apply_fix): Set fx_size to 4 for 20 bit displacements. * testsuite/gas/s390/s390.exp: Run new test. * testsuite/gas/s390/zarch-z990-symbol-lay.s: New test. |
||
|
Alan Modra
|
be9a9af906 |
Fix more fallout from 17f6ade235
gas/ * testsuite/gas/avr/large-debug-line-table.d: Update. ld/ * testsuite/ld-avr/gc-section-debugline.d: Update. |
||
|
H.J. Lu
|
ddb77fcccb |
gas: Update expected outputs of "readelf -wL"
Update expected outputs of "readelf -wL" for
commit
|
||
Nick Clifton
|
fbaf61ad52 |
Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream!
We have not only removed all unsupported and obsolete code, but also supported lost of new features, including better link-time relaxations and TLS implementations. Besides, the files generated by the newly assembler and linker usually get higher performance and more optimized code size. ld * emultempl/nds32elf.em (hyper_relax): New variable. (nds32_elf_create_output_section_statements): the parameters of bfd_elf32_nds32_set_target_option (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Add new option --mhyper-relax. * emultempl/nds32elf.em (nds32_elf_after_open): Updated. * emultempl/nds32elf.em (tls_desc_trampoline): New variable. * (nds32_elf_create_output_section_statements): Updated. * (nds32_elf_after_parse): Disable relaxations when PIC is enable. * (PARSE_AND_LIST_PROLOGUE, PARSE_AND_LIST_OPTIONS, PARSE_AND_LIST_ARGS_CASES): Add new option --m[no-]tlsdesc-trampoline. include * elf/nds32.h: Remove the unused target features. * dis-asm.h (disassemble_init_nds32): Declared. * elf/nds32.h (E_NDS32_NULL): Removed. (E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New. * opcode/nds32.h: Ident. (N32_SUB6, INSN_LW): New macros. (enum n32_opcodes): Updated. * elf/nds32.h: Doc fixes. * elf/nds32.h: Add R_NDS32_LSI. * elf/nds32.h: Add new relocations for TLS. gas * config/tc-nds32.c: Remove the unused target features. (nds32_relax_relocs, md_pseudo_table, nds32_elf_record_fixup_exp, nds32_set_elf_flags_by_insn, nds32_insert_relax_entry, nds32_apply_fix): Likewise. (nds32_no_ex9_begin): Removed. * config/tc-nds32.c (add_mapping_symbol_for_align, make_mapping_symbol, add_mapping_symbol): New functions. * config/tc-nds32.h (enum mstate): New. (nds32_segment_info_type): Likewise. * configure.ac (--enable-dsp-ext, --enable-zol-ext): New options. * config.in: Regenerated. * configure: Regenerated. * config/tc-nds32.c (nds32_dx_regs): Set the value according to the configuration. (nds32_perf_ext, nds32_perf_ext2, nds32_string_ext, nds32_audio_ext): Likewise. (nds32_dsp_ext): New variable. Set the value according to the configuration. (nds32_zol_ext): Likewise. (asm_desc, nds32_pseudo_opcode_table): Make them static. (nds32_set_elf_flags_by_insn): Updated. (nds32_check_insn_available): Updated. (nds32_str_tolower): New function. * config/tc-nds32.c (relax_table): Updated. (md_begin): Updated. (md_assemble): Use XNEW macro to allocate space for `insn.info', and then remember to free it. (md_section_align): Cast (-1) to ValueT. (nds32_get_align): Cast (~0U) to addressT. (nds32_relax_branch_instructions): Updated. (md_convert_frag): Add new local variable `final_r_type'. (invalid_prev_frag): Add new bfd_boolean parameter `relax'. All callers changed. * config/tc-nds32.c (struct nds32_relocs_pattern): Add `insn' field. (struct nds32_hint_map): Add `option_list' field. (struct suffix_name, suffix_table): Remove the unused `pic' field. (do_pseudo_b, do_pseudo_bal): Remove the suffix checking. (do_pseudo_la_internal, do_pseudo_pushpopm): Indent. (relax_hint_bias, relax_hint_id_current): New static variables. (reset_bias, relax_hint_begin): New variables. (nds_itoa): New function. (CLEAN_REG, GET_OPCODE): New macros. (struct relax_hint_id): New. (nds32_relax_hint): For .relax_hint directive, we can use `begin' and `end' to mark the relax pattern without giving exactly id number. (nds32_elf_append_relax_relocs): Handle the case that the .relax_hint directives are attached to pseudo instruction. (nds32_elf_save_pseudo_pattern): Change the second parameter from instruction's opcode to byte code. (nds32_elf_build_relax_relation): Add new bfd_boolean parameter `pseudo_hint'. (nds32_lookup_pseudo_opcode): Fix the overflow issue. (enum nds32_insn_type): Add N32_RELAX_ALU1 and N32_RELAX_16BIT. (nds32_elf_record_fixup_exp, relax_ls_table, hint_map, nds32_find_reloc_table, nds32_match_hint_insn, nds32_parse_name): Updated. * config/tc-nds32.h (MAX_RELAX_NUM): Extend it to 6. (enum nds32_relax_hint_type): Merge NDS32_RELAX_HINT_LA and NDS32_RELAX_HINT_LS into NDS32_RELAX_HINT_LALS. Add NDS32_RELAX_HINT_LA_PLT, NDS32_RELAX_HINT_LA_GOT and NDS32_RELAX_HINT_LA_GOTOFF. * config/tc-nds32.h (relax_ls_table): Add floating load/store to gp relax pattern. (hint_map, nds32_find_reloc_table): Likewise. * configure.ac: Define NDS32_LINUX_TOOLCHAIN. * configure: Regenerated. * config.in: Regenerated. * config/tc-nds32.h (enum nds32_ramp): Updated. (enum nds32_relax_hint_type): Likewise. * config/tc-nds32.c: Include "errno.h" and "limits.h". (relax_ls_table): Add TLS relax patterns. (nds32_elf_append_relax_relocs): Attach BFD_RELOC_NDS32_GROUP on each instructions of TLS patterns. (nds32_elf_record_fixup_exp): Updated. (nds32_apply_fix): Likewise. (suffix_table): Add TLSDESC suffix. binutils* testsuite/binutils-all/objcopy.exp: Set the unsupported reloc number from 215 to 255 for NDS32. bfd * elf32-nds32.c (nds32_elf_relax_loadstore): Remove the unused target features. (bfd_elf32_nds32_set_target_option): Remove the unused parameters. (nds32_elf_relax_piclo12, nds32_elf_relax_letlslo12, nds32_elf_relax_letlsadd, nds32_elf_relax_letlsls, nds32_elf_relax_pltgot_suff, nds32_elf_relax_got_suff nds32_elf_relax_gotoff_suff, calculate_plt_memory_address, calculate_plt_offset, calculate_got_memory_address, nds32_elf_check_dup_relocs): Removed. All callers changed. * elf32-nds32.h: Remove the unused macros and defines. (elf_nds32_link_hash_table): Remove the unused variable. (bfd_elf32_nds32_set_target_option): Update prototype. (nds32_elf_ex9_init): Removed. * elf32-nds32.c (nds32_convert_32_to_16): Updated. * elf32-nds32.c (HOWTO2, HOWTO3): Define new HOWTO macros to initialize array nds32_elf_howto_table in any order without lots of EMPTY_HOWTO. (nds32_reloc_map): Updated. * reloc.c: Add BFD_RELOC_NDS32_LSI. * bfd-in2.h: Regenerated. * bfd/libbfd.h: Regenerated. * elf32-nds32.c (nds32_elf_relax_howto_table): Add R_NDS32_LSI. (nds32_reloc_map): Likewise. (nds32_elf_relax_flsi): New function. (nds32_elf_relax_section): Support floating load/store relaxation. * elf32-nds32.c (NDS32_GUARD_SEC_P, elf32_nds32_local_gp_offset): New macro. (struct elf_nds32_link_hash_entry): New `offset_to_gp' field. (struct elf_nds32_obj_tdata): New `offset_to_gp' and `hdr_size' fields. (elf32_nds32_allocate_local_sym_info, nds32_elf_relax_guard, nds32_elf_is_target_special_symbol, nds32_elf_maybe_function_sym): New functions. (nds32_info_to_howto_rel): Add BFD_ASSERT. (bfd_elf32_bfd_reloc_type_table_lookup, nds32_elf_link_hash_newfunc, nds32_elf_link_hash_table_create, nds32_elf_relocate_section, nds32_elf_relax_loadstore, nds32_elf_relax_lo12, nds32_relax_adjust_label, bfd_elf32_nds32_set_target_option, nds32_fag_mark_relax): Updated. (nds32_elf_final_sda_base): Improve it to find the better gp value. (insert_nds32_elf_blank): Must consider `len' when inserting blanks. * elf32-nds32.h (bfd_elf32_nds32_set_target_option): Update prototype. (struct elf_nds32_link_hash_table): Add new variable `hyper_relax'. * elf32-nds32.c (elf32_nds32_allocate_dynrelocs): New function. (create_got_section): Likewise. (allocate_dynrelocs, nds32_elf_size_dynamic_sections, nds32_elf_relocate_section, nds32_elf_finish_dynamic_symbol): Updated. (nds32_elf_check_relocs): Fix the issue that the shared library may has TEXTREL entry in the dynamic section. (nds32_elf_create_dynamic_sections): Enable to call readonly_dynrelocs since the TEXTREL issue is fixed in the nds32_elf_check_relocs. (nds32_elf_finish_dynamic_sections): Update and add DT_RELASZ dynamic entry. (calculate_offset): Remove the unused parameter `pic_ext_target' and related codes. All callers changed. (elf_backend_dtrel_excludes_plt): Disable it temporarily since it will cause some errors for our test cases. * elf32-nds32.c (nds32_elf_merge_private_bfd_data): Allow to link the generic object. * reloc.c: Add TLS relocations. * libbfd.h: Regenerated. * bfd-in2.h: Regenerated. * elf32-nds32.h (struct section_id_list_t): New. (elf32_nds32_lookup_section_id, elf32_nds32_check_relax_group, elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New prototypes. (elf32_nds32_compute_jump_table_size, elf32_nds32_local_tlsdesc_gotent): New macro. (nds32_insertion_sort, bfd_elf32_nds32_set_target_option, elf_nds32_link_hash_table): Updated. * elf32-nds32.c (enum elf_nds32_tls_type): New. (struct elf32_nds32_relax_group_t, struct relax_group_list_t): New. (elf32_nds32_add_dynreloc, patch_tls_desc_to_ie, get_tls_type, fls, ones32, list_insert, list_insert_sibling, dump_chain, elf32_nds32_check_relax_group, elf32_nds32_lookup_section_id, elf32_nds32_unify_relax_group, nds32_elf_unify_tls_model): New functions. (elf_nds32_obj_tdata): Add new fields. (elf32_nds32_relax_group_ptr, nds32_elf_local_tlsdesc_gotent): New macros. (nds32_elf_howto_table): Add TLS relocations. (nds32_reloc_map): Likewise. (nds32_elf_copy_indirect_symbol, nds32_elf_size_dynamic_sections, nds32_elf_finish_dynamic_symbol, elf32_nds32_allocate_local_sym_info, nds32_elf_relocate_section, bfd_elf32_nds32_set_target_option, nds32_elf_check_relocs, allocate_dynrelocs): Updated. (nds32_elf_relax_section): Call nds32_elf_unify_tls_model. (dtpoff_base): Rename it to `gottpof' and then update it. opcodes * nds32-asm.c (operand_fields): Remove the unused fields. (nds32_opcodes): Remove the unused instructions. * nds32-dis.c (nds32_ex9_info): Removed. (nds32_parse_opcode): Updated. (print_insn_nds32): Likewise. * nds32-asm.c (config.h, stdlib.h, string.h): New includes. (LEX_SET_FIELD, LEX_GET_FIELD): Update defines. (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table, build_opcode_hash_table): New functions. (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table, nds32_opcode_table): New. (hw_ktabs): Declare it to a pointer rather than an array. (build_hash_table): Removed. * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT, SYN_ROPT and upadte HW_GPR and HW_INT. * nds32-dis.c (keywords): Remove const. (match_field): New function. (nds32_parse_opcode): Updated. * disassemble.c (disassemble_init_for_target): Add disassemble_init_nds32. * nds32-dis.c (eum map_type): New. (nds32_private_data): Likewise. (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid, nds32_add_opcode_hash_table, disassemble_init_nds32): New functions. (print_insn_nds32): Updated. * nds32-asm.c (parse_aext_reg): Add new parameter. (parse_re, parse_re2, parse_aext_reg): Only reduced registers are allowed to use. All callers changed. * nds32-asm.c (keyword_usr, keyword_sr): Updated. (operand_fields): Add new fields. (nds32_opcodes): Add new instructions. (keyword_aridxi_mx): New keyword. * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX and NASM_ATTR_ZOL. (ALU2_1, ALU2_2, ALU2_3): New macros. * nds32-dis.c (nds32_filter_unknown_insn): Updated. |
||
Jim Wilson
|
4e2b18982a |
RISC-V: bge[u] should get higher priority than ble[u].
2018-09-17 Kito Cheng <kito@andestech.com> gas/ * testsuite/gas/riscv/bge.d: New. * testsuite/gas/riscv/bge.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu. |
||
|
H.J. Lu
|
04e2a1829e |
x86: Set EVex=2 on EVEX.128 only vmovd and vmovq
EVEX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64", "VMOVD r64/m64, xmm2", "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with EVEX.128. Set EVex=2 on EVEX.128 only vmovd and vmovq. gas/ PR gas/23670 * testsuite/gas/i386/evex-lig-2.d: New file. * testsuite/gas/i386/evex-lig-2.s: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.d: Likewise. * testsuite/gas/i386/x86-64-evex-lig-2.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex-lig-2 and x86-64-evex-lig-2. opcodes/ PR gas/23670 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2, EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2. (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. * i386-dis.c (USE_EVEX_LEN_TABLE): New. (EVEX_LEN_TABLE): Likewise. (EVEX_LEN_0F6E_P_2): New enum. (EVEX_LEN_0F7E_P_1): Likewise. (EVEX_LEN_0F7E_P_2): Likewise. (EVEX_LEN_0FD6_P_2): Likewise. (evex_len_table): New. (get_valid_dis386): Handle USE_EVEX_LEN_TABLE. * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated. |
||
|
H.J. Lu
|
d5f787c2bc |
x86: Set Vex=1 on VEX.128 only vmovd and vmovq
AVX "VMOVD xmm1, r32/m32", "VMOVD r32/m32, xmm2", "VMOVQ xmm1, r64/m64" and "VMOVD r64/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovd and vmovq. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar.s: Remove vmovq and vmovd tests. * testsuite/gas/i386/x86-64-avx-scalar.s: Likewise. * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. * testsuite/gas/i386/i386.exp: Run avx-scalar2 and x86-64-avx-scalar2. * testsuite/gas/i386/avx-scalar-2.d: New file. * testsuite/gas/i386/avx-scalar-2.s: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-2.s: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and VEX_LEN_0F7E_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq. * i386-tbl.h: Regenerated. |
||
|
H.J. Lu
|
0375113302 |
x86: Add -mvexwig=[0|1] option to assembler
Add -mvexwig=[0|1] option to x86 assembler to control how the assembler should encode the VEX.W bit in WIG VEX instructions. * gas/NEWS: Mention -mvexwig=[0|1] option. * config/tc-i386.c (vexwig): New. (build_vex_prefix): Set the VEX.W bit for -mvexwig=1 for WIG VEX instructions. (OPTION_MVEXWIG): New. (md_longopts): Add -mvexwig=. (md_parse_option): Handle OPTION_MVEXWIG. (md_show_usage): Show -mvexwig=[0|1]. * doc/c-i386.texi: Document -mvexwig=[0|1]. * testsuite/gas/i386/avx-wig.d: New file. * testsuite/gas/i386/avx-wig.s: Likewise. * testsuite/gas/i386/avx2-wig.d: Likewise. * testsuite/gas/i386/avx2-wig.s: Likewise. * testsuite/gas/i386/x86-64-avx-wig.d: Likewise. * testsuite/gas/i386/x86-64-avx-wig.s: Likewise. * testsuite/gas/i386/x86-64-avx2-wig.d: Likewise. * testsuite/gas/i386/x86-64-avx2-wig.s: Likewise. * testsuite/gas/i386/i386.exp: Run avx-wig, avx2-wig, x86-64-avx-wig and x86-64-avx2-wig. |
||
|
Alan Modra
|
a4b9568c7e |
Remove bogus notarget in gas teststuite
* testsuite/gas/arm/arch7.d: Delete notarget. * testsuite/gas/arm/arch7a-mp.d: Likewise. * testsuite/gas/arm/arch7em.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-5.d: Likewise. * testsuite/gas/arm/barrier.d: Likewise. * testsuite/gas/arm/bignum1.d: Likewise. * testsuite/gas/arm/thumb32.d: Likewise. * testsuite/gas/elf/dwarf2-1.d: Likewise. * testsuite/gas/elf/dwarf2-2.d: Likewise. * testsuite/gas/elf/dwarf2-4.d: Likewise. * testsuite/gas/elf/group2.d: Likewise. * testsuite/gas/arm/mapshort-elf.d: Only notarget pe and wince. * testsuite/gas/elf/dwarf2-3.d: Delete notarget, xfail ft32 and h8300. * testsuite/gas/elf/dwarf2-6.d: Delete notarget, xfail a few. |
||
|
Alan Modra
|
0b1352e04c |
A few hppa testcase tidies
binutils/ * testsuite/lib/binutils-common.exp (is_som_format): New proc. (run_dump_test): Correct target test for alternate .comm syntax. (get_standard_section_names): Handle som format. * testsuite/lib/utils-lib.exp (default_binutils_assemble_flags): Correct target test for alternate .comm syntax. gas/ * testsuite/gas/all/gas.exp (redef3): Don't xfail for hppa. (octa): Run for hppa. * testsuite/gas/elf/elf.exp (common1, common2): Likewise. * testsuite/gas/elf/symver.d: Delete notarget. ld/ * testsuite/ld-elf/comm-data5.d: Remove notarget for hppa. * testsuite/ld-scripts/defined6.d: Likewise. |
||
|
Nick Clifton
|
a0a8a9340d |
Ensure that binutils test names are unique.
binutils* testsuite/binutils-all/compress.exp: Rename second "objcopy zlib-gnu compress debug sections 3" test to "objcopy zlib-gabi compress debug sections 3" and use gabi object files instead of gnu object files. * testsuite/binutils-all/objcopy.exp: Add suffix to the names of the "ELF group" tests. * testsuite/binutils-all/readelf.exp (proc readelf_find_size): Add an iteration parameter and include it in the name of the test. Update callers to include an iteration count. gas * testuite/gas/elf/group0a.d: Add extra details to the test name. * testuite/gas/elf/group0b.d: Likewise. * testuite/gas/elf/group1a.d: Likewise. * testuite/gas/elf/group1b.d: Likewise. * testuite/gas/elf/group0b.d: Likewise. * testuite/gas/elf/section9.d: Likewise. * testuite/gas/i386/ilp32/lns/lns-common-1.d: Likewise. * testuite/gas/i386/ilp32/lns/lns-duplicate-1.d: Likewise. ld * testuite/ld/ld-elf/audit.exp: Differentiate the names of the two "Run with shared with --audit" tests. * testuite/ld/ld-elf/compress.exp: Differentiate the zlib compressed debug output test names. * testuite/ld/ld-i386/tlspie1.d: Add extra details to the test name. * testuite/ld/ld-i386/tlspie2.d: Likewise. * testuite/ld/ld-size/size.exp: Add missing escapes to the end of lines in the size-3e test. * testuite/ld/ld-unique/unique.exp: Differentiate the names of the two "Checking unique PIC object" tests. * testuite/ld/ld-x86-64/tlspie1.d: Add extra details to the test name. |
||
|
H.J. Lu
|
3c3741435f |
x86: Set Vex=1 on VEX.128 only vmovq
AVX "VMOVQ xmm1, xmm2/m64" and "VMOVQ xmm1/m64, xmm2" can only be encoded with VEX.128. Set Vex=1 on VEX.128 only vmovq and update assembler tests. gas/ PR gas/23665 * testsuite/gas/i386/avx-scalar-intel.d: Updated. * testsuite/gas/i386/avx-scalar.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar-intel.d: Likewise. * testsuite/gas/i386/x86-64-avx-scalar.d: Likewise. opcodes/ PR gas/23665 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and VEX_LEN_0FD6_P_2 entries. * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq. * i386-tbl.h: Regenerated. |
||
|
Alan Modra
|
8ffb70eb57 |
Consolidate run_dump_test
This merges the three versions of run_dump_test. Improved warning handling versus the old gas version shows up a number of tests that need their disassembly updating: arm-linuxeabi +FAIL: ARM v1 instructions arm-linuxeabi +FAIL: Accepted v8-a with ARMv8.1 AdvSIMD. arm-linuxeabi +FAIL: bl local instructions for v4t. arm-linuxeabi +FAIL: UDF and some that now fail due to detecting assembly warnings: h8300-elf +FAIL: binutils-all/strip-13 h8300-elf +FAIL: binutils-all/strip-14 h8300-elf +FAIL: binutils-all/strip-15 I've generally kept the union of all run_dump_test features, except that the ld target aliases "cfi" and "shared" have disappeared, as has the binutils substitution of $srcdir as $scrdir/$subdir. binutils/ * testsuite/binutils-all/add-symbol.d: Add "section_subst: no". * testsuite/binutils-all/elfedit.exp: Don't set tempfile or copyfile. * testsuite/binutils-all/symbols-1.d, * testsuite/binutils-all/symbols-2.d, * testsuite/binutils-all/symbols-3.d, * testsuite/binutils-all/symbols-4.d: Quote '*' and '!'. * testsuite/binutils-all/add-empty-section.d, * testsuite/binutils-all/add-section.d, * testsuite/binutils-all/elfedit.exp, * testsuite/binutils-all/note-1.d, * testsuite/binutils-all/pr23633.d: Add $subdir after $srcdir. * testsuite/config/default.exp (AS, ASFLAGS): Define. * testsuite/config/hppa.sed: Handle all common symbols. * testsuite/lib/binutils-common.exp (run_dump_test): New proc, merged from three other versions. (slurp_options, file_contents, set_file_contents): Likewise. (big_or_little_endian, get_standard_section_names): Likewise. * testsuite/lib/utils-lib.exp (run_dump_test): Delete. (slurp_options, proc file_contents): Delete. (get_standard_section_names): Delete. gas/ * testsuite/config/default.exp: Make tmpdir. * testsuite/lib/gas-defs.exp (run_dump_test): Delete. (get_standard_section_names, slurp_options): Delete. ld/ * testsuite/ld-d10v/reloc-007.d, * testsuite/ld-d10v/reloc-008.d, * testsuite/ld-d10v/reloc-015.d, * testsuite/ld-d10v/reloc-016.d: Remove "error:". * testsuite/ld-elf/eh-frame-hdr.d, * testsuite/ld-elf/eh5.d, * testsuite/ld-gc/personality.d: Replace "cfi" and "shared" in target list with appropriate proc. * testsuite/ld-elf/frame.exp: Use check_shared_lib_support rather than "istarget shared". * testsuite/lib/ld-lib.exp (proc big_or_little_endian): Delete. (run_dump_test, slurp_options, file_contents): Delete. (set_file_contents, istarget): Delete. |
||
|
Alan Modra
|
99bcaeaf0f |
run_dump_test replace PROG with DUMPPROG in gas and ld
To be compatible with the binutils version, that uses PROG for the tool under test and DUMPPROG for the dump tool. gas/ * testsuite/gas/mips/aent-2.d, * testsuite/gas/mips/aent-mdebug-2.d, * testsuite/gas/mips/attr-gnu-4-0.d, * testsuite/gas/mips/attr-gnu-4-1.d, * testsuite/gas/mips/attr-gnu-4-2.d, * testsuite/gas/mips/attr-gnu-4-3.d, * testsuite/gas/mips/attr-gnu-4-5.d, * testsuite/gas/mips/attr-gnu-4-6.d, * testsuite/gas/mips/attr-gnu-4-7.d, * testsuite/gas/mips/attr-none-double.d, * testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d, * testsuite/gas/mips/attr-none-o32-fp64.d, * testsuite/gas/mips/attr-none-o32-fpxx.d, * testsuite/gas/mips/attr-none-single-float.d, * testsuite/gas/mips/attr-none-soft-float.d, * testsuite/gas/mips/elf-rel27.d, * testsuite/gas/mips/loc-swap-2.d, * testsuite/gas/mips/loc-swap-3.d, * testsuite/gas/mips/loc-swap.d, * testsuite/gas/mips/micromips@loc-swap-2.d, * testsuite/gas/mips/micromips@loc-swap.d, * testsuite/gas/mips/micromips@stabs-symbol-type.d, * testsuite/gas/mips/mips16-intermix.d, * testsuite/gas/mips/mips16@loc-swap-2.d, * testsuite/gas/mips/mips16@loc-swap.d, * testsuite/gas/mips/mips16@stabs-symbol-type.d, * testsuite/gas/mips/mips16e@loc-swap.d, * testsuite/gas/mips/no-odd-spreg.d, * testsuite/gas/mips/odd-spreg.d, * testsuite/gas/mips/r6-attr-none-double.d, * testsuite/gas/mips/stabs-symbol-type.d, * testsuite/lib/gas-defs.exp (run_dump_test): Replace PROG with DUMPPROG. ld/ * testsuite/lib/ld-lib.exp (run_dump_test): Replace PROG with DUMPPROG. |
||
|
Alan Modra
|
4abd8e8de7 |
gas testuite fixes: don't match dump.o
The consolidated run_dump_test will use object file names based on the source file name, like the current ld version. * testsuite/gas/elf/symver.d, * testsuite/gas/ft32/insn.d, * testsuite/gas/ft32/insnsc.d, * testsuite/gas/i386/ilp32/elf/symver.d, * testsuite/gas/lm32/csr.d, * testsuite/gas/lm32/insn.d, * testsuite/gas/m68hc11/9s12x-exg-sex-tfr.d, * testsuite/gas/m68hc11/9s12x-mov.d, * testsuite/gas/m68hc11/hexprefix.d, * testsuite/gas/m68hc11/insns9s12x.d, * testsuite/gas/m68hc11/insns9s12xg.d, * testsuite/gas/mep/dj1.be.d, * testsuite/gas/mep/dj1.le.d, * testsuite/gas/mips/set-arch.d, * testsuite/gas/mips/tls-o32.d, * testsuite/gas/nios2/branch-r2.d, * testsuite/gas/nios2/branch.d, * testsuite/gas/pdp11/absreloc.d, * testsuite/gas/pdp11/opcode.d, * testsuite/gas/pdp11/pr14480.d, * testsuite/gas/pdp11/pr23481.d, * testsuite/gas/ppc/xcoff-dwsect-1-32.d, * testsuite/gas/ppc/xcoff-dwsect-1-64.d, * testsuite/gas/rx/abs.d, * testsuite/gas/rx/adc.d, * testsuite/gas/rx/add.d, * testsuite/gas/rx/and.d, * testsuite/gas/rx/bclr.d, * testsuite/gas/rx/bcnd.d, * testsuite/gas/rx/bmcnd.d, * testsuite/gas/rx/bnot.d, * testsuite/gas/rx/bra.d, * testsuite/gas/rx/brk.d, * testsuite/gas/rx/bset.d, * testsuite/gas/rx/bsr.d, * testsuite/gas/rx/btst.d, * testsuite/gas/rx/clrpsw.d, * testsuite/gas/rx/cmp.d, * testsuite/gas/rx/dbt.d, * testsuite/gas/rx/div.d, * testsuite/gas/rx/divu.d, * testsuite/gas/rx/emaca.d, * testsuite/gas/rx/emsba.d, * testsuite/gas/rx/emul.d, * testsuite/gas/rx/emula.d, * testsuite/gas/rx/emulu.d, * testsuite/gas/rx/fadd.d, * testsuite/gas/rx/fcmp.d, * testsuite/gas/rx/fdiv.d, * testsuite/gas/rx/fmul.d, * testsuite/gas/rx/fsqrt.d, * testsuite/gas/rx/fsub.d, * testsuite/gas/rx/ftoi.d, * testsuite/gas/rx/ftou.d, * testsuite/gas/rx/gprel.d, * testsuite/gas/rx/int.d, * testsuite/gas/rx/itof.d, * testsuite/gas/rx/jmp.d, * testsuite/gas/rx/jsr.d, * testsuite/gas/rx/machi.d, * testsuite/gas/rx/maclh.d, * testsuite/gas/rx/maclo.d, * testsuite/gas/rx/max.d, * testsuite/gas/rx/min.d, * testsuite/gas/rx/mov.d, * testsuite/gas/rx/movco.d, * testsuite/gas/rx/movli.d, * testsuite/gas/rx/movu.d, * testsuite/gas/rx/msbhi.d, * testsuite/gas/rx/msblh.d, * testsuite/gas/rx/msblo.d, * testsuite/gas/rx/mul.d, * testsuite/gas/rx/mulhi.d, * testsuite/gas/rx/mullh.d, * testsuite/gas/rx/mullo.d, * testsuite/gas/rx/mvfacgu.d, * testsuite/gas/rx/mvfachi.d, * testsuite/gas/rx/mvfaclo.d, * testsuite/gas/rx/mvfacmi.d, * testsuite/gas/rx/mvfc.d, * testsuite/gas/rx/mvfcp.d, * testsuite/gas/rx/mvtacgu.d, * testsuite/gas/rx/mvtachi.d, * testsuite/gas/rx/mvtaclo.d, * testsuite/gas/rx/mvtc.d, * testsuite/gas/rx/mvtcp.d, * testsuite/gas/rx/neg.d, * testsuite/gas/rx/nop.d, * testsuite/gas/rx/not.d, * testsuite/gas/rx/opecp.d, * testsuite/gas/rx/or.d, * testsuite/gas/rx/pop.d, * testsuite/gas/rx/popc.d, * testsuite/gas/rx/popm.d, * testsuite/gas/rx/pr19665.d, * testsuite/gas/rx/pr22737.d, * testsuite/gas/rx/push.d, * testsuite/gas/rx/pushc.d, * testsuite/gas/rx/pushm.d, * testsuite/gas/rx/r-bcc.d, * testsuite/gas/rx/r-bra.d, * testsuite/gas/rx/racl.d, * testsuite/gas/rx/racw.d, * testsuite/gas/rx/rdacl.d, * testsuite/gas/rx/rdacw.d, * testsuite/gas/rx/revl.d, * testsuite/gas/rx/revw.d, * testsuite/gas/rx/rmpa.d, * testsuite/gas/rx/rolc.d, * testsuite/gas/rx/rorc.d, * testsuite/gas/rx/rotl.d, * testsuite/gas/rx/rotr.d, * testsuite/gas/rx/round.d, * testsuite/gas/rx/rte.d, * testsuite/gas/rx/rtfi.d, * testsuite/gas/rx/rts.d, * testsuite/gas/rx/rtsd.d, * testsuite/gas/rx/sat.d, * testsuite/gas/rx/satr.d, * testsuite/gas/rx/sbb.d, * testsuite/gas/rx/sccnd.d, * testsuite/gas/rx/scmpu.d, * testsuite/gas/rx/setpsw.d, * testsuite/gas/rx/shar.d, * testsuite/gas/rx/shll.d, * testsuite/gas/rx/shlr.d, * testsuite/gas/rx/smovb.d, * testsuite/gas/rx/smovf.d, * testsuite/gas/rx/smovu.d, * testsuite/gas/rx/sstr.d, * testsuite/gas/rx/stnz.d, * testsuite/gas/rx/stz.d, * testsuite/gas/rx/sub.d, * testsuite/gas/rx/suntil.d, * testsuite/gas/rx/swhile.d, * testsuite/gas/rx/tst.d, * testsuite/gas/rx/utof.d, * testsuite/gas/rx/wait.d, * testsuite/gas/rx/xchg.d, * testsuite/gas/rx/xor.d, * testsuite/gas/s12z/abs.d, * testsuite/gas/s12z/adc-imm.d, * testsuite/gas/s12z/adc-opr.d, * testsuite/gas/s12z/add-imm.d, * testsuite/gas/s12z/add-opr.d, * testsuite/gas/s12z/and-imm.d, * testsuite/gas/s12z/and-opr.d, * testsuite/gas/s12z/and-or-cc.d, * testsuite/gas/s12z/bfext-special.d, * testsuite/gas/s12z/bfext.d, * testsuite/gas/s12z/bit-manip.d, * testsuite/gas/s12z/bit.d, * testsuite/gas/s12z/bra-expression-defined.d, * testsuite/gas/s12z/bra-expression-undef.d, * testsuite/gas/s12z/bra.d, * testsuite/gas/s12z/brclr-symbols.d, * testsuite/gas/s12z/brset-clr-opr-imm-rel.d, * testsuite/gas/s12z/brset-clr-opr-reg-rel.d, * testsuite/gas/s12z/brset-clr-reg-imm-rel.d, * testsuite/gas/s12z/brset-clr-reg-reg-rel.d, * testsuite/gas/s12z/clb.d, * testsuite/gas/s12z/clr-opr.d, * testsuite/gas/s12z/clr.d, * testsuite/gas/s12z/cmp-imm.d, * testsuite/gas/s12z/cmp-opr-inc.d, * testsuite/gas/s12z/cmp-opr-rdirect.d, * testsuite/gas/s12z/cmp-opr-reg.d, * testsuite/gas/s12z/cmp-opr-rindirect.d, * testsuite/gas/s12z/cmp-opr-sxe4.d, * testsuite/gas/s12z/cmp-opr-xys.d, * testsuite/gas/s12z/cmp-s-imm.d, * testsuite/gas/s12z/cmp-s-opr.d, * testsuite/gas/s12z/cmp-xy.d, * testsuite/gas/s12z/com-opr.d, * testsuite/gas/s12z/complex-shifts.d, * testsuite/gas/s12z/db-tb-cc-opr.d, * testsuite/gas/s12z/db-tb-cc-reg.d, * testsuite/gas/s12z/dbCC.d, * testsuite/gas/s12z/dec-opr.d, * testsuite/gas/s12z/dec.d, * testsuite/gas/s12z/div.d, * testsuite/gas/s12z/eor.d, * testsuite/gas/s12z/exg.d, * testsuite/gas/s12z/ext24-ld-xy.d, * testsuite/gas/s12z/inc-opr.d, * testsuite/gas/s12z/inc.d, * testsuite/gas/s12z/inh.d, * testsuite/gas/s12z/jmp.d, * testsuite/gas/s12z/jsr.d, * testsuite/gas/s12z/ld-imm-page2.d, * testsuite/gas/s12z/ld-imm.d, * testsuite/gas/s12z/ld-immu18.d, * testsuite/gas/s12z/ld-large-direct.d, * testsuite/gas/s12z/ld-opr.d, * testsuite/gas/s12z/ld-s-opr.d, * testsuite/gas/s12z/ld-small-direct.d, * testsuite/gas/s12z/lea-immu18.d, * testsuite/gas/s12z/lea.d, * testsuite/gas/s12z/mac.d, * testsuite/gas/s12z/min-max.d, * testsuite/gas/s12z/mod.d, * testsuite/gas/s12z/mov.d, * testsuite/gas/s12z/mul-imm.d, * testsuite/gas/s12z/mul-opr-opr.d, * testsuite/gas/s12z/mul-opr.d, * testsuite/gas/s12z/mul-reg.d, * testsuite/gas/s12z/mul.d, * testsuite/gas/s12z/neg-opr.d, * testsuite/gas/s12z/not-so-simple-shifts.d, * testsuite/gas/s12z/opr-18u.d, * testsuite/gas/s12z/opr-expr.d, * testsuite/gas/s12z/opr-ext-18.d, * testsuite/gas/s12z/opr-idx-24-reg.d, * testsuite/gas/s12z/opr-idx3-reg.d, * testsuite/gas/s12z/opr-idx3-xysp-24.d, * testsuite/gas/s12z/opr-indirect-expr.d, * testsuite/gas/s12z/opr-symbol.d, * testsuite/gas/s12z/or-imm.d, * testsuite/gas/s12z/or-opr.d, * testsuite/gas/s12z/p2-mul.d, * testsuite/gas/s12z/page2-inh.d, * testsuite/gas/s12z/psh-pul.d, * testsuite/gas/s12z/qmul.d, * testsuite/gas/s12z/rotate.d, * testsuite/gas/s12z/sat.d, * testsuite/gas/s12z/sbc-imm.d, * testsuite/gas/s12z/sbc-opr.d, * testsuite/gas/s12z/shift.d, * testsuite/gas/s12z/simple-shift.d, * testsuite/gas/s12z/single-ops.d, * testsuite/gas/s12z/specd6.d, * testsuite/gas/s12z/st-large-direct.d, * testsuite/gas/s12z/st-opr.d, * testsuite/gas/s12z/st-s-opr.d, * testsuite/gas/s12z/st-small-direct.d, * testsuite/gas/s12z/st-xy.d, * testsuite/gas/s12z/sub-imm.d, * testsuite/gas/s12z/sub-opr.d, * testsuite/gas/s12z/tfr.d, * testsuite/gas/s12z/trap.d, * testsuite/gas/sh/fdpic.d, * testsuite/gas/sh/sh2a-pic.d, * testsuite/gas/sh/sh2a.d: Don't match object file name. * testsuite/gas/wasm32/disass-2.d, * testsuite/gas/wasm32/disass.d: Likewise, and tidy regexps. |
||
|
Alan Modra
|
e643ed088a |
gas run_dump_test rename stderr and error-output
Use warning_output and error_output, like the ld version of run_dump_test. Note that some tests used the wrong option, and this went undetected since the gas version of run_dump_test doesn't properly check tool error status. This patch corrects wrong options, in preparation for a later patch that will check error status. * testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.d, * testsuite/gas/aarch64/armv8_2-a-illegal.d, * testsuite/gas/aarch64/armv8_4-a-illegal.d, * testsuite/gas/aarch64/armv8_4-a-registers-illegal.d, * testsuite/gas/aarch64/deprecated.d, * testsuite/gas/aarch64/diagnostic.d, * testsuite/gas/aarch64/illegal-2.d, * testsuite/gas/aarch64/illegal-by-element.d, * testsuite/gas/aarch64/illegal-crypto-nofp.d, * testsuite/gas/aarch64/illegal-fcmla.d, * testsuite/gas/aarch64/illegal-fjcvtzs.d, * testsuite/gas/aarch64/illegal-fp16-nofp.d, * testsuite/gas/aarch64/illegal-ldapr.d, * testsuite/gas/aarch64/illegal-ldraa.d, * testsuite/gas/aarch64/illegal-lse.d, * testsuite/gas/aarch64/illegal-nofp-armv8_3.d, * testsuite/gas/aarch64/illegal-nofp16.d, * testsuite/gas/aarch64/illegal-ras-1.d, * testsuite/gas/aarch64/illegal-sysreg-2.d, * testsuite/gas/aarch64/illegal-sysreg-3.d, * testsuite/gas/aarch64/illegal.d, * testsuite/gas/aarch64/legacy_reg_names.d, * testsuite/gas/aarch64/pan-illegal.d, * testsuite/gas/aarch64/pr22529.d, * testsuite/gas/aarch64/rm-simd-ext.d, * testsuite/gas/aarch64/sve-invalid.d, * testsuite/gas/aarch64/sve-reg-diagnostic.d, * testsuite/gas/aarch64/sve-sysreg-invalid.d, * testsuite/gas/aarch64/sysreg-diagnostic.d, * testsuite/gas/aarch64/verbose-error.d, * testsuite/gas/all/byte.d, * testsuite/gas/all/org-1.d, * testsuite/gas/all/org-2.d, * testsuite/gas/all/org-3.d, * testsuite/gas/all/sleb128-9.d, * testsuite/gas/arc/asm-errors-2.d, * testsuite/gas/arc/asm-errors-3.d, * testsuite/gas/arc/asm-errors.d, * testsuite/gas/arc/attr-rf16.d, * testsuite/gas/arc/relocs-errors.d, * testsuite/gas/arc/textinsn-errors.d, * testsuite/gas/arm/addsw-bad.d, * testsuite/gas/arm/addthumb2err.d, * testsuite/gas/arm/adr-invalid.d, * testsuite/gas/arm/arch7em-bad-1.d, * testsuite/gas/arm/arch7em-bad-2.d, * testsuite/gas/arm/arch7em-bad-3.d, * testsuite/gas/arm/arch7m-bad.d, * testsuite/gas/arm/archv6s-m-bad.d, * testsuite/gas/arm/archv6t2-bad.d, * testsuite/gas/arm/arm-idiv-bad.d, * testsuite/gas/arm/arm-it-bad-2.d, * testsuite/gas/arm/arm-it-bad-3.d, * testsuite/gas/arm/arm-it-bad.d, * testsuite/gas/arm/arm3-bad.d, * testsuite/gas/arm/arm7-bad.d, * testsuite/gas/arm/armv1-bad.d, * testsuite/gas/arm/armv1.d, * testsuite/gas/arm/armv2-mp-bad.d, * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d, * testsuite/gas/arm/armv8-2-fp16-simd-warning-thumb.d, * testsuite/gas/arm/armv8-2-fp16-simd-warning.d, * testsuite/gas/arm/armv8-a+rdma-warning.d, * testsuite/gas/arm/armv8-a-bad.d, * testsuite/gas/arm/armv8-a-it-bad.d, * testsuite/gas/arm/armv8-r-bad.d, * testsuite/gas/arm/armv8-r-it-bad.d, * testsuite/gas/arm/armv8_2-a-fp16-illegal.d, * testsuite/gas/arm/armv8_3-a-fp-bad.d, * testsuite/gas/arm/armv8_3-a-simd-bad.d, * testsuite/gas/arm/barrier-bad-thumb.d, * testsuite/gas/arm/barrier-bad.d, * testsuite/gas/arm/bl-local-v4t.d, * testsuite/gas/arm/blx-bl-convert.d, * testsuite/gas/arm/blx-local.d, * testsuite/gas/arm/branch-reloc.d, * testsuite/gas/arm/copro-arm_v2plus-arm_v1.d, * testsuite/gas/arm/copro-arm_v5plus-arm_v4.d, * testsuite/gas/arm/copro-arm_v5teplus-arm_v5.d, * testsuite/gas/arm/copro-arm_v6plus-arm_v5te.d, * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-1.d, * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-2.d, * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-3.d, * testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v4t-4.d, * testsuite/gas/arm/crc32-armv8-a-bad.d, * testsuite/gas/arm/crc32-armv8-r-bad.d, * testsuite/gas/arm/depr-swp.d, * testsuite/gas/arm/dest-unpredictable.d, * testsuite/gas/arm/dotprod-illegal.d, * testsuite/gas/arm/dotprod-legacy-arch.d, * testsuite/gas/arm/forbid-armv7-idiv-ext.d, * testsuite/gas/arm/group-reloc-alu-encoding-bad.d, * testsuite/gas/arm/group-reloc-alu-parsing-bad.d, * testsuite/gas/arm/group-reloc-ldc-encoding-bad.d, * testsuite/gas/arm/group-reloc-ldc-parsing-bad.d, * testsuite/gas/arm/group-reloc-ldr-encoding-bad.d, * testsuite/gas/arm/group-reloc-ldr-parsing-bad.d, * testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d, * testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d, * testsuite/gas/arm/insn-error-a.d, * testsuite/gas/arm/insn-error-t.d, * testsuite/gas/arm/inst-po-2.d, * testsuite/gas/arm/iwmmxt-bad.d, * testsuite/gas/arm/iwmmxt-bad2.d, * testsuite/gas/arm/ld-sp-warn-cortex-m3.d, * testsuite/gas/arm/ld-sp-warn-cortex-m4.d, * testsuite/gas/arm/ld-sp-warn-v7.d, * testsuite/gas/arm/ld-sp-warn-v7a.d, * testsuite/gas/arm/ld-sp-warn-v7em.d, * testsuite/gas/arm/ld-sp-warn-v7m.d, * testsuite/gas/arm/ld-sp-warn-v7r.d, * testsuite/gas/arm/ld-sp-warn.d, * testsuite/gas/arm/ldgesb-bad.d, * testsuite/gas/arm/ldgesh-bad.d, * testsuite/gas/arm/ldr-bad.d, * testsuite/gas/arm/ldr-t-bad.d, * testsuite/gas/arm/ldrd-unpredictable.d, * testsuite/gas/arm/ldsgeb.d, * testsuite/gas/arm/ldsgeh.d, * testsuite/gas/arm/missing.d, * testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d, * testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d, * testsuite/gas/arm/msr-imm-bad.d, * testsuite/gas/arm/msr-reg-bad.d, * testsuite/gas/arm/mul-overlap.d, * testsuite/gas/arm/neon-addressing-bad.d, * testsuite/gas/arm/neon-cond-bad.d, * testsuite/gas/arm/neon-ldst-align-bad.d, * testsuite/gas/arm/neon-ldst-es-bad.d, * testsuite/gas/arm/neon-suffix-bad.d, * testsuite/gas/arm/neon-vmov-bad.d, * testsuite/gas/arm/noarm.d, * testsuite/gas/arm/pr18256.d, * testsuite/gas/arm/pr18347.d, * testsuite/gas/arm/pr20429.d, * testsuite/gas/arm/pr22773.d, * testsuite/gas/arm/r15-bad.d, * testsuite/gas/arm/reloc-bad.d, * testsuite/gas/arm/req.d, * testsuite/gas/arm/shift-bad-pc.d, * testsuite/gas/arm/shift-bad.d, * testsuite/gas/arm/simd_by_scalar_low_regbank.d, * testsuite/gas/arm/simd_by_scalar_low_regbank_thumb.d, * testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d, * testsuite/gas/arm/sp-pc-validations-bad-t.d, * testsuite/gas/arm/sp-pc-validations-bad.d, * testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d, * testsuite/gas/arm/srs-arm.d, * testsuite/gas/arm/srs-t2.d, * testsuite/gas/arm/strex-bad-t.d, * testsuite/gas/arm/t16-bad.d, * testsuite/gas/arm/thumb-b-bad.d, * testsuite/gas/arm/thumb-w-bad.d, * testsuite/gas/arm/thumb2_bad_reg.d, * testsuite/gas/arm/thumb2_it_bad.d, * testsuite/gas/arm/thumb2_it_bad_auto.d, * testsuite/gas/arm/thumb2_ldmstm_bad.d, * testsuite/gas/arm/thumb2_ldstd_unpredictable.d, * testsuite/gas/arm/thumb2_mul-bad.d, * testsuite/gas/arm/thumb2_str-bad.d, * testsuite/gas/arm/thumb32.d, * testsuite/gas/arm/udf-bad.d, * testsuite/gas/arm/udf.d, * testsuite/gas/arm/undefined.d, * testsuite/gas/arm/undefined_coff.d, * testsuite/gas/arm/vcmp-zero-bad.d, * testsuite/gas/arm/vcvt-bad.d, * testsuite/gas/arm/vfp-bad.d, * testsuite/gas/arm/vfp-bad_t2.d, * testsuite/gas/arm/vfpv3-d16-bad.d, * testsuite/gas/arm/vldm-thumb-bad.d, * testsuite/gas/arm/vldmw-arm-bad.d, * testsuite/gas/arm/vldmw-thumb-bad.d, * testsuite/gas/arm/vstr-arm-bad.d, * testsuite/gas/arm/vstr-thumb-bad.d, * testsuite/gas/arm/weakdef-2.d, * testsuite/gas/avr/pr21621.d, * testsuite/gas/elf/bad-bss.d, * testsuite/gas/elf/bad-group.d, * testsuite/gas/elf/bad-group.err, * testsuite/gas/elf/bad-section-flag.d, * testsuite/gas/elf/bad-section-flag.err, * testsuite/gas/elf/bad-size.d, * testsuite/gas/elf/bad-size.err, * testsuite/gas/elf/common1.d, * testsuite/gas/elf/common2.d, * testsuite/gas/elf/common5a.d, * testsuite/gas/elf/common5b.d, * testsuite/gas/elf/common5c.d, * testsuite/gas/elf/common5d.d, * testsuite/gas/elf/dwarf2-10.d, * testsuite/gas/elf/dwarf2-8.d, * testsuite/gas/elf/dwarf2-9.d, * testsuite/gas/elf/pr21661.d, * testsuite/gas/elf/pseudo.d, * testsuite/gas/elf/section13.d, * testsuite/gas/i386/bad-size.d, * testsuite/gas/i386/bundle-bad.d, * testsuite/gas/i386/ilp32/x86-64-sse-check-warn.d, * testsuite/gas/i386/intel-intel.d, * testsuite/gas/i386/intel.d, * testsuite/gas/i386/intelok.d, * testsuite/gas/i386/mpx-add-bnd-prefix.d, * testsuite/gas/i386/sse-check-warn.d, * testsuite/gas/i386/string-ok.d, * testsuite/gas/i386/vgather-check-warn.d, * testsuite/gas/i386/x86-64-mpx-add-bnd-prefix.d, * testsuite/gas/i386/x86-64-sse-check-warn.d, * testsuite/gas/i386/x86-64-vgather-check-warn.d, * testsuite/gas/mips/addiu-error.d, * testsuite/gas/mips/branch-extern-3.d, * testsuite/gas/mips/branch-extern-4.d, * testsuite/gas/mips/branch-local-2.d, * testsuite/gas/mips/branch-local-3.d, * testsuite/gas/mips/branch-local-5.d, * testsuite/gas/mips/branch-local-6.d, * testsuite/gas/mips/branch-local-n32-2.d, * testsuite/gas/mips/branch-local-n32-3.d, * testsuite/gas/mips/branch-local-n32-5.d, * testsuite/gas/mips/branch-local-n32-6.d, * testsuite/gas/mips/branch-local-n64-2.d, * testsuite/gas/mips/branch-local-n64-3.d, * testsuite/gas/mips/branch-local-n64-5.d, * testsuite/gas/mips/branch-local-n64-6.d, * testsuite/gas/mips/branch-section-3.d, * testsuite/gas/mips/branch-section-4.d, * testsuite/gas/mips/branch-weak-3.d, * testsuite/gas/mips/branch-weak-4.d, * testsuite/gas/mips/break-error.d, * testsuite/gas/mips/crc-err.d, * testsuite/gas/mips/crc64-err.d, * testsuite/gas/mips/ginv-err.d, * testsuite/gas/mips/interaptiv-mr2@isa-override-1.d, * testsuite/gas/mips/interaptiv-mr2@isa-override-2.d, * testsuite/gas/mips/isa-override-2.d, * testsuite/gas/mips/lui-1.d, * testsuite/gas/mips/lui-2.d, * testsuite/gas/mips/macro-warn-1-n32.d, * testsuite/gas/mips/macro-warn-1.d, * testsuite/gas/mips/macro-warn-2.d, * testsuite/gas/mips/macro-warn-3.d, * testsuite/gas/mips/macro-warn-4.d, * testsuite/gas/mips/micromips-branch-delay.d, * testsuite/gas/mips/micromips-branch-relax-insn32-pic.d, * testsuite/gas/mips/micromips-branch-relax-insn32.d, * testsuite/gas/mips/micromips-branch-relax-pic.d, * testsuite/gas/mips/micromips-branch-relax.d, * testsuite/gas/mips/micromips-compact.d, * testsuite/gas/mips/micromips-insn32.d, * testsuite/gas/mips/micromips-noinsn32.d, * testsuite/gas/mips/micromips-size-1.d, * testsuite/gas/mips/micromips-trap.d, * testsuite/gas/mips/micromips-warn-branch-delay.d, * testsuite/gas/mips/micromips.d, * testsuite/gas/mips/micromips@addiu-error.d, * testsuite/gas/mips/micromips@mips5-fp.d, * testsuite/gas/mips/micromips@msa-relax.d, * testsuite/gas/mips/micromips@relax-at.d, * testsuite/gas/mips/micromips@relax-offset.d, * testsuite/gas/mips/micromips@relax.d, * testsuite/gas/mips/mips-gp32-fp64-pic.d, * testsuite/gas/mips/mips-gp32-fp64.d, * testsuite/gas/mips/mips-gp64-fp32-pic.d, * testsuite/gas/mips/mips-gp64-fp32.d, * testsuite/gas/mips/mips-gp64-fp64.d, * testsuite/gas/mips/mips16-32@mips16-insn-e.d, * testsuite/gas/mips/mips16-32@mips16-insn-t.d, * testsuite/gas/mips/mips16-32@mips16-macro-e.d, * testsuite/gas/mips/mips16-32@mips16-macro-t.d, * testsuite/gas/mips/mips16-32@mips16-macro.d, * testsuite/gas/mips/mips16-64@mips16-insn-e.d, * testsuite/gas/mips/mips16-64@mips16-insn-t.d, * testsuite/gas/mips/mips16-absolute-reloc-2.d, * testsuite/gas/mips/mips16-absolute-reloc-3.d, * testsuite/gas/mips/mips16-branch-addend-5.d, * testsuite/gas/mips/mips16-branch-unextended-1.d, * testsuite/gas/mips/mips16-branch-unextended-2.d, * testsuite/gas/mips/mips16-insn-e.d, * testsuite/gas/mips/mips16-insn-t.d, * testsuite/gas/mips/mips16-jal-t.d, * testsuite/gas/mips/mips16-macro-e.d, * testsuite/gas/mips/mips16-macro-t.d, * testsuite/gas/mips/mips16-pcrel-2.d, * testsuite/gas/mips/mips16-pcrel-3.d, * testsuite/gas/mips/mips16-pcrel-4.d, * testsuite/gas/mips/mips16-pcrel-5.d, * testsuite/gas/mips/mips16-pcrel-absolute-n64-4.d, * testsuite/gas/mips/mips16-pcrel-absolute-n64-6.d, * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-4.d, * testsuite/gas/mips/mips16-pcrel-absolute-pic-n64-6.d, * testsuite/gas/mips/mips16-pcrel-addend-n64-8.d, * testsuite/gas/mips/mips16-pcrel-addend-n64-9.d, * testsuite/gas/mips/mips16-pcrel-addend-pic-8.d, * testsuite/gas/mips/mips16-pcrel-addend-pic-9.d, * testsuite/gas/mips/mips16-pcrel-delay-0.d, * testsuite/gas/mips/mips16-pcrel-delay-1.d, * testsuite/gas/mips/mips16-pcrel-n64-0.d, * testsuite/gas/mips/mips16-pcrel-n64-1.d, * testsuite/gas/mips/mips16-pcrel-pic-0.d, * testsuite/gas/mips/mips16-pcrel-pic-1.d, * testsuite/gas/mips/mips16-reg-error.d, * testsuite/gas/mips/mips16-relax-unextended-1.d, * testsuite/gas/mips/mips16-relax-unextended-2.d, * testsuite/gas/mips/mips16-reloc-error.d, * testsuite/gas/mips/mips16-sdrasp.d, * testsuite/gas/mips/mips16@addiu-error.d, * testsuite/gas/mips/mips16e-32@mips16-insn-e.d, * testsuite/gas/mips/mips16e-32@mips16-insn-t.d, * testsuite/gas/mips/mips16e-32@mips16-macro-e.d, * testsuite/gas/mips/mips16e-32@mips16-macro-t.d, * testsuite/gas/mips/mips16e-32@mips16-macro.d, * testsuite/gas/mips/mips16e-32@mips16e-64.d, * testsuite/gas/mips/mips16e2-32@mips16-insn-e.d, * testsuite/gas/mips/mips16e2-32@mips16-insn-t.d, * testsuite/gas/mips/mips16e2-32@mips16-macro-e.d, * testsuite/gas/mips/mips16e2-32@mips16-macro-t.d, * testsuite/gas/mips/mips16e2-32@mips16-macro.d, * testsuite/gas/mips/mips16e2-32@mips16e-64.d, * testsuite/gas/mips/mips16e2-copy-err.d, * testsuite/gas/mips/mips16e2-imm-error.d, * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.d, * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.d, * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.d, * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.d, * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.d, * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.d, * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.d, * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64.d, * testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.d, * testsuite/gas/mips/mips16e2-mt-err.d, * testsuite/gas/mips/mips16e2-reloc-error.d, * testsuite/gas/mips/mips16e2@lui-2.d, * testsuite/gas/mips/mips16e2@mips16-pcrel-2.d, * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-0.d, * testsuite/gas/mips/mips16e2@mips16-pcrel-delay-1.d, * testsuite/gas/mips/mips1@isa-override-2.d, * testsuite/gas/mips/mips1@relax-offset.d, * testsuite/gas/mips/mips2@isa-override-2.d, * testsuite/gas/mips/mips32-mt.d, * testsuite/gas/mips/mips32@isa-override-2.d, * testsuite/gas/mips/mips32r2@isa-override-2.d, * testsuite/gas/mips/mips32r3@isa-override-2.d, * testsuite/gas/mips/mips32r5@isa-override-2.d, * testsuite/gas/mips/mips32r6@isa-override-2.d, * testsuite/gas/mips/mips5-fp.d, * testsuite/gas/mips/mips64-mips3d-incl.d, * testsuite/gas/mips/mips64-mips3d.d, * testsuite/gas/mips/mipsr6@mips5-fp.d, * testsuite/gas/mips/msa-relax.d, * testsuite/gas/mips/octeon3@isa-override-1.d, * testsuite/gas/mips/octeon3@isa-override-2.d, * testsuite/gas/mips/option-pic-relax-2.d, * testsuite/gas/mips/option-pic-relax-3.d, * testsuite/gas/mips/option-pic-relax-4.d, * testsuite/gas/mips/option-pic-relax-5.d, * testsuite/gas/mips/org-1.d, * testsuite/gas/mips/org-10.d, * testsuite/gas/mips/org-4.d, * testsuite/gas/mips/org-5.d, * testsuite/gas/mips/org-6.d, * testsuite/gas/mips/r3000@isa-override-2.d, * testsuite/gas/mips/r3000@relax-offset.d, * testsuite/gas/mips/r3900@isa-override-2.d, * testsuite/gas/mips/r3900@relax-offset.d, * testsuite/gas/mips/reginfo-2-n32.d, * testsuite/gas/mips/reginfo-2.d, * testsuite/gas/mips/relax-at.d, * testsuite/gas/mips/relax-offset.d, * testsuite/gas/mips/relax-swap1-mips1.d, * testsuite/gas/mips/relax-swap1-mips2.d, * testsuite/gas/mips/relax-swap2.d, * testsuite/gas/mips/relax.d, * testsuite/gas/mips/save-err.d, * testsuite/gas/mips/set-arch.d, * testsuite/gas/mips/xpa-err.d, * testsuite/gas/mips/xpa-virt-err.d, * testsuite/gas/msp430/bad.d, * testsuite/gas/msp430/errata_warns.d, * testsuite/gas/msp430/pr22133.d, * testsuite/gas/ppc/lsp-checks.d, * testsuite/gas/ppc/misalign.d, * testsuite/gas/ppc/spe2-checks.d, * testsuite/gas/riscv/bad-csr.d, * testsuite/gas/riscv/c-addi16sp-fail.d, * testsuite/gas/riscv/c-addi4spn-fail.d, * testsuite/gas/riscv/c-fld-fsd-fail.d, * testsuite/gas/riscv/c-lui-fail.d, * testsuite/gas/riscv/c-nonzero-imm.d, * testsuite/gas/riscv/c-nonzero-reg.d, * testsuite/gas/riscv/fence-fail.d, * testsuite/gas/riscv/lla64-fail.d, * testsuite/gas/riscv/rouding-fail.d, * testsuite/gas/sh/pcrel-hms.d, * testsuite/gas/sh/pcrel.d, * testsuite/gas/sparc/dcti-couples-v8.d, * testsuite/gas/sparc/dcti-couples-v9c.d, * testsuite/gas/tic6x/arch-invalid-1.d, * testsuite/gas/tic6x/arch-invalid-2.d, * testsuite/gas/tic6x/dir-junk.d, * testsuite/gas/tic6x/insns-bad-1.d, * testsuite/gas/tic6x/insns-bad-2.d, * testsuite/gas/tic6x/parallel-bad-1.d, * testsuite/gas/tic6x/parallel-bad-2.d, * testsuite/gas/tic6x/parallel-bad-3.d, * testsuite/gas/tic6x/parallel-bad-4.d, * testsuite/gas/tic6x/predicate-bad-1.d, * testsuite/gas/tic6x/predicate-bad-2.d, * testsuite/gas/tic6x/predicate-bad-3.d, * testsuite/gas/tic6x/reloc-bad-1.d, * testsuite/gas/tic6x/reloc-bad-2.d, * testsuite/gas/tic6x/reloc-bad-3.d, * testsuite/gas/tic6x/reloc-bad-4.d, * testsuite/gas/tic6x/reloc-bad-5.d, * testsuite/gas/tic6x/reloc-bad-6.d, * testsuite/gas/tic6x/resource-func-unit-1.d, * testsuite/gas/tic6x/resource-func-unit-2.d, * testsuite/gas/tic6x/sploop-bad-1.d, * testsuite/gas/tic6x/sploop-bad-2.d, * testsuite/gas/tic6x/sploop-bad-3.d, * testsuite/gas/tic6x/sploop-bad-4.d, * testsuite/gas/tic6x/sploop-bad-5.d, * testsuite/gas/tic6x/sploop-bad-6.d, * testsuite/gas/tic6x/sploop-bad-7.d, * testsuite/gas/tic6x/unwind-bad-1.d, * testsuite/gas/tic6x/unwind-bad-2.d, * testsuite/lib/gas-defs.exp (run_dump_tests): Replace stderr and error-output with warning_output and error_output. (slurp_options): Accept underscore rather than dash. |
||
|
Alan Modra
|
b47b60aad8 |
gas run_dump_test rename not-target and not-skip
Use notarget and noskip, like the ld testsuite. * testsuite/gas/aarch64/codealign.d, * testsuite/gas/aarch64/litpool.d, * testsuite/gas/aarch64/mapmisc.d, * testsuite/gas/aarch64/mapping.d, * testsuite/gas/aarch64/mapping2.d, * testsuite/gas/aarch64/mapping3.d, * testsuite/gas/aarch64/mapping4.d, * testsuite/gas/all/align.d, * testsuite/gas/all/fill-1.d, * testsuite/gas/all/incbin.d, * testsuite/gas/all/redef2.d, * testsuite/gas/all/redef3.d, * testsuite/gas/all/relax.d, * testsuite/gas/all/sleb128-2.d, * testsuite/gas/all/sleb128-4.d, * testsuite/gas/all/sleb128-5.d, * testsuite/gas/all/sleb128-7.d, * testsuite/gas/all/sleb128-9.d, * testsuite/gas/all/weakref1.d, * testsuite/gas/all/weakref1g.d, * testsuite/gas/all/weakref1l.d, * testsuite/gas/all/weakref1u.d, * testsuite/gas/all/weakref1w.d, * testsuite/gas/arm/abs12.d, * testsuite/gas/arm/arch4t.d, * testsuite/gas/arm/arch7.d, * testsuite/gas/arm/arch7a-mp.d, * testsuite/gas/arm/arch7em.d, * testsuite/gas/arm/archv8m-main-dsp-5.d, * testsuite/gas/arm/armv8a-automatic-hlt.d, * testsuite/gas/arm/armv8a-automatic-lda.d, * testsuite/gas/arm/attr-syntax.d, * testsuite/gas/arm/automatic-bw.d, * testsuite/gas/arm/automatic-cbz.d, * testsuite/gas/arm/automatic-clrex.d, * testsuite/gas/arm/automatic-lda.d, * testsuite/gas/arm/automatic-ldaex.d, * testsuite/gas/arm/automatic-ldaexb.d, * testsuite/gas/arm/automatic-ldrex.d, * testsuite/gas/arm/automatic-ldrexd.d, * testsuite/gas/arm/automatic-movw.d, * testsuite/gas/arm/automatic-sdiv.d, * testsuite/gas/arm/automatic-strexb.d, * testsuite/gas/arm/barrier-thumb.d, * testsuite/gas/arm/barrier.d, * testsuite/gas/arm/bignum1.d, * testsuite/gas/arm/blx-bad.d, * testsuite/gas/arm/blx-local.s, * testsuite/gas/arm/crc32-armv8-a-bad.d, * testsuite/gas/arm/crc32-armv8-a.d, * testsuite/gas/arm/crc32-armv8-r-bad.d, * testsuite/gas/arm/crc32-armv8-r.d, * testsuite/gas/arm/eabi_attr_1.d, * testsuite/gas/arm/fp-save.d, * testsuite/gas/arm/local_function.d, * testsuite/gas/arm/local_label_coff.d, * testsuite/gas/arm/local_label_wince.d, * testsuite/gas/arm/mapping.d, * testsuite/gas/arm/mapping2.d, * testsuite/gas/arm/mapping3.d, * testsuite/gas/arm/mapping4.d, * testsuite/gas/arm/mapshort-elf.d, * testsuite/gas/arm/mask_1-armv8-a.d, * testsuite/gas/arm/mask_1-armv8-r.d, * testsuite/gas/arm/mrs-msr-thumb-v6t2.d, * testsuite/gas/arm/mrs-msr-thumb-v7-m.d, * testsuite/gas/arm/mrs-msr-thumb-v7e-m.d, * testsuite/gas/arm/nomapping.d, * testsuite/gas/arm/pic.d, * testsuite/gas/arm/pic_vxworks.d, * testsuite/gas/arm/plt-1.d, * testsuite/gas/arm/reloc-bad.d, * testsuite/gas/arm/reloc-fdpic.d, * testsuite/gas/arm/t2-branch-global.d, * testsuite/gas/arm/thumb.d, * testsuite/gas/arm/thumb2_ldr_immediate_armv6.d, * testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d, * testsuite/gas/arm/thumb2_pool.d, * testsuite/gas/arm/thumb2_vpool.d, * testsuite/gas/arm/thumb2_vpool_be.d, * testsuite/gas/arm/thumb32.d, * testsuite/gas/arm/thumbver.d, * testsuite/gas/arm/tls.d, * testsuite/gas/arm/tls_vxworks.d, * testsuite/gas/arm/undefined_coff.d, * testsuite/gas/arm/unwind.d, * testsuite/gas/arm/unwind_vxworks.d, * testsuite/gas/arm/v4bx.d, * testsuite/gas/arm/vfma1.d, * testsuite/gas/arm/vldm-arm.d, * testsuite/gas/arm/weakdef-1.d, * testsuite/gas/arm/weakdef-2.d, * testsuite/gas/arm/wince.d, * testsuite/gas/arm/wince_inst.d, * testsuite/gas/elf/bignums.d, * testsuite/gas/elf/common5a.d, * testsuite/gas/elf/common5b.d, * testsuite/gas/elf/common5c.d, * testsuite/gas/elf/common5d.d, * testsuite/gas/elf/dwarf2-1.d, * testsuite/gas/elf/dwarf2-10.d, * testsuite/gas/elf/dwarf2-11.d, * testsuite/gas/elf/dwarf2-12.d, * testsuite/gas/elf/dwarf2-13.d, * testsuite/gas/elf/dwarf2-14.d, * testsuite/gas/elf/dwarf2-15.d, * testsuite/gas/elf/dwarf2-16.d, * testsuite/gas/elf/dwarf2-17.d, * testsuite/gas/elf/dwarf2-18.d, * testsuite/gas/elf/dwarf2-2.d, * testsuite/gas/elf/dwarf2-3.d, * testsuite/gas/elf/dwarf2-4.d, * testsuite/gas/elf/dwarf2-5.d, * testsuite/gas/elf/dwarf2-6.d, * testsuite/gas/elf/dwarf2-7.d, * testsuite/gas/elf/dwarf2-8.d, * testsuite/gas/elf/dwarf2-9.d, * testsuite/gas/elf/group0c.d, * testsuite/gas/elf/group1a.d, * testsuite/gas/elf/group2.d, * testsuite/gas/elf/groupautoa.d, * testsuite/gas/elf/ifunc-1.d, * testsuite/gas/elf/section11.d, * testsuite/gas/elf/section4.d, * testsuite/gas/elf/section7.d, * testsuite/gas/elf/syms.d, * testsuite/gas/elf/symver.d, * testsuite/gas/i386/iamcu-1.d, * testsuite/gas/i386/iamcu-2.d, * testsuite/gas/i386/iamcu-3.d, * testsuite/gas/i386/iamcu-4.d, * testsuite/gas/i386/iamcu-5.d, * testsuite/gas/i386/ilp32/rex.d, * testsuite/gas/i386/k1om.d, * testsuite/gas/i386/l1om.d, * testsuite/gas/i386/rex.d, * testsuite/gas/mach-o/sections-3.d, * testsuite/gas/macros/irp.d, * testsuite/gas/macros/repeat.d, * testsuite/gas/macros/rept.d, * testsuite/gas/macros/semi.d, * testsuite/gas/macros/test2.d, * testsuite/gas/macros/test3.d, * testsuite/gas/macros/vararg.d, * testsuite/gas/mips/jal-svr4pic-local.d, * testsuite/gas/mips/micromips@jal-svr4pic-local.d, * testsuite/gas/mips/mips1@jal-svr4pic-local.d, * testsuite/gas/mips/r3000@jal-svr4pic-local.d, * testsuite/gas/ppc/machine.d, * testsuite/lib/gas-defs.exp (run_dump_test): Replace not-target and not-skip with notarget and noskip. |
||
|
Alan Modra
|
04ade4bc66 |
Remove run_dump_test support for objcopy as a dump program
We have three copies of run_dump_test in the testsuite. This is a first step towards consolidating them. A few tests use objcopy to convert to verilog or srec output, then check that output is as expected. Those tests can just as easily use objdump, keeping the set of dump programs (addr2line, nm, objdump, readelf, size) separate from utilities under test. That in turn makes auto-detecting the dump program possible in more places. binutils/ * testsuite/binutils-all/group-7a.d, * testsuite/binutils-all/group-7b.d, * testsuite/binutils-all/group-7c.d, * testsuite/binutils-all/symbols-1.d, * testsuite/binutils-all/symbols-2.d, * testsuite/binutils-all/symbols-3.d, * testsuite/binutils-all/symbols-4.d: Remove DUMPPROG. gas/ * testsuite/gas/mri/char.d: Don't objcopy to srec, objdump instead. * testsuite/gas/mri/float.d: Likewise. * testsuite/lib/gas-defs.exp (run_dump_test): Remove support for objcopy as a dump tool. ld/ * testsuite/ld-elf/interleave-0.d, * testsuite/ld-elf/interleave-4.d: Don't objcopy to srec, objdump instead. * testsuite/ld-gc/all-debug-sections.d, * testsuite/ld-scripts/provide-4.d, * testsuite/ld-scripts/provide-5.d, * testsuite/ld-scripts/provide-6.d, * testsuite/ld-scripts/provide-7.d, * testsuite/ld-scripts/provide-8.d, * testsuite/ld-scripts/segment-start.d: Remove PROG, specify nm instead. * testsuite/lib/ld-lib.exp (run_dump_test): Remove support for objcopy as a dump tool. |
||
|
H.J. Lu
|
606cc04085 |
x86: Check non-WIG EVEX instruction encoding with -mevexwig=1
Verify that -mevexwig=1 has no impact on non-WIG EVEX instruction encoding. PR gas/23642 * testsuite/gas/i386/evex-wig2.d: New file. * testsuite/gas/i386/evex-wig2.s: Likewise. * testsuite/gas/i386/x86-64-evex-wig2.d: Likewise. * testsuite/gas/i386/x86-64-evex-wig2.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex-wig2 and x86-64-evex-wig2. |
||
|
H.J. Lu
|
70df6fc9bc |
x86: Handle unsupported static rounding in vcvt[u]si2sd in 32-bit mode
Update x86 disassembler to handle the unsupported static rounding in vcvt[u]si2sd in 32-bit mode. gas/ PR binutils/23655 * testsuite/gas/i386/evex.d: Updated. opcodes/ PR binutils/23655 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for vcvtsi2sd%LQ and vcvtusi2sd%LQ. * i386-dis.c (EXxEVexR64): New. (evex_rounding_64_mode): Likewise. (OP_Rounding): Handle evex_rounding_64_mode. |
||
|
H.J. Lu
|
d20dee9efa |
x86: Properly decode EVEX.W in vcvt[u]si2s[sd] in 32-bit mode
Update x86 disassembler to ignore the EVEX.W bit in EVEX vcvt[u]si2s[sd] instructions in 32-bit mode. gas/ PR binutils/23655 * testsuite/gas/i386/evex.d: New file. * testsuite/gas/i386/evex.s: Likewise. * testsuite/gas/i386/i386.exp: Run evex. opcodes/ PR binutils/23655 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ. * i386-dis.c (Edqa): New. (dqa_mode): Likewise. (intel_operand_size): Handle dqa_mode as m_mode. (OP_E_register): Handle dqa_mode as dq_mode. (OP_E_memory): Set shift for dqa_mode based on address_mode. |
||
|
Jan Beulich
|
dbbc8b7e62 |
x86: use D attribute also for SIMD templates
Various moves come in load and store forms, and just like on the GPR and FPU sides there would better be only one pattern. In some cases this is not feasible because the opcodes are too different, but quite a few cases follow a similar standard scheme. Introduce Opcode_SIMD_FloatD and Opcode_SIMD_IntD, generalize handling in operand_size_match() (reverse operand handling there simply needs to match "straight" operand one), and fix a long standing, but so far only latent bug with when to zap found_reverse_match. Also once again drop IgnoreSize where pointlessly applied to templates touched anyway as well as *word when redundant with Reg*. |