* config/tc-arm.c (do_neon_cvt_1): Parse vcvtne as vcvt-ne for
NS_FD shape when MVE is present
* testsuite/gas/arm/mve-vcvtne-it-bad.d: New test.
* testsuite/gas/arm/mve-vcvtne-it-bad.l: New test.
* testsuite/gas/arm/mve-vcvtne-it-bad.s: New test.
* testsuite/gas/arm/mve-vcvtne-it.d: New test.
* testsuite/gas/arm/mve-vcvtne-it.s: New test.
This patch fixes an assertion failure on long system register operands
in the AArch64 backend. See the new testcase for an input which
reproduces the issue.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sys_reg): Don't assert when parsing
a long system register.
(parse_sys_ins_reg): Likewise.
(sysreg_hash_insert): New.
(md_begin): Use sysreg_hash_insert() to ensure all system
registers are no longer than the maximum length at startup.
* testsuite/gas/aarch64/invalid-sysreg-assert.d: New test.
* testsuite/gas/aarch64/invalid-sysreg-assert.l: Error output.
* testsuite/gas/aarch64/invalid-sysreg-assert.s: Input.
include/ChangeLog:
* opcode/aarch64.h (AARCH64_MAX_SYSREG_NAME_LEN): New.
The MSP430 GAS option "-md" is supposed to indicate that the CRT startup
code should copy data from ROM to RAM at startup. However, this option
has no effect; GAS handles the related behaviour automatically by
looking for the presence of certain symbols in the input file.
gas/ChangeLog:
* config/tc-msp430.c (OPTION_MOVE_DATA): Remove.
(md_parse_option): Remove case for OPTION_MOVE_DATA.
(md_longopts): Remove "md" entry.
(md_show_usage): Likewise.
Since (%bp)/(%ebp)/(%rbp) are encoded as 0(%bp)/0(%ebp)/0(%rbp), use
disp32/disp16 on 0(%bp)/0(%ebp)/0(%rbp) for {disp32}.
Note: Since there is no disp32 on 0(%bp), use disp16 instead.
PR gas/26305
* config/tc-i386.c (build_modrm_byte): Use disp32/disp16 on
(%bp)/(%ebp)/(%rbp) for {disp32}.
* doc/c-i386.texi: Update {disp32} documentation.
* testsuite/gas/i386/pseudos.s: Add (%bp)/(%ebp) tests.
* testsuite/gas/i386/x86-64-pseudos.s: Add (%ebp)/(%rbp) tests.
* testsuite/gas/i386/pseudos.d: Updated.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
Ever since commit 4d7206a284 ("Rework MIPS macro relaxation, fix string
merging bug"), <https://sourceware.org/ml/binutils/2004-01/msg00248.html>,
`prev_reloc_op_frag' has only been set and never used. Remove it then.
gas/
* config/tc-mips.c (prev_reloc_op_frag): Remove variable.
(my_getSmallExpression): Adjust accordingly.
PR gas/4572
When / is a comment character, its use as binary "divide" operator needs
escaping by a backslash. Besides the scrubber needing to support this
(addressed in an earlier change), there are also a few provisions needed
in target specific operator handling.
As the spec calls for % and * to also be escaped because of being
"overloaded", also recognize these, despite the overloading there not
really preventing their use as operators in most (%) or all (*) cases,
given the way how the rest of the assembler works.
To bring source and testsuite in line, also drop the TE_I386AIX part of
the respective conditional, as i?86-*-aix* support had been removed a
while ago.
Various provisions exist for insns to be placed in the absolute section,
yet actually trying to do so didn't work. While data emission (of non-
zero values) is not allowed by generic code, I think this functionality
is useful for the programmer to be able to determine the size of insns.
Therefore, rather than turning the silnet failure into a verbose one,
make things mostly work; the one class of insns not supported (yet) are
branches (JMP and Jcc) with dynamically determined displacement widths.
In this one case, an error now gets reported instead of silently
ignoring the code.
Also avoid recording ISA / feature usage for insns emitted to the
absolute section.
When encoding a 32-bit offset, there is no need to sign-extend it to 64
bits since only the lower 32 bits are used.
* config/tc-i386.c (offset_in_range): Remove 32-bit sign
extension.
Extract extended states from operand types in instruction template. Set
xstate_zmm for master register move.
* config/tc-i386.c (_i386_insn): Remove has_regmmx, has_regxmm,
has_regymm, has_regzmm and has_regtmm. Add xstate.
(md_assemble): Set i.xstate from operand types in instruction
template.
(build_modrm_byte): Updated.
(output_insn): Check i.xstate.
* testsuite/gas/i386/i386.exp: Run property-6 and
x86-64-property-6.
* testsuite/gas/i386/property-6.d: New file.
* testsuite/gas/i386/property-6.s: Updated.
* testsuite/gas/i386/x86-64-property-6.d: Likewise.
Since VEX/EVEX vector instructions will always update the full YMM/ZMM
registers, set YMM/ZMM features for VEX/EVEX vector instructions.
* config/tc-i386.c (output_insn): Set YMM/ZMM features for
VEX/EVEX vector instructions.
* testsuite/gas/i386/property-4.d: New file.
* testsuite/gas/i386/property-4.s: Likewise.
* testsuite/gas/i386/property-5.d: Likewise.
* testsuite/gas/i386/property-5.s: Likewise.
* testsuite/gas/i386/x86-64-property-4.d: Likewise.
* testsuite/gas/i386/x86-64-property-5.d: Likewise.
We check register-only source operand to decide if two source operands of
VEX encoded instructions should be swapped. But source operands in AMX
instructions with two source operands swapped are all register-only
operand. Add SwapSources to indicate two source operands should be
swapped.
gas/
* config/tc-i386.c (build_modrm_byte): Check vexswapsources to
swap two source operands.
opcodes/
* i386-gen.c (opcode_modifiers): Add VexSwapSources.
* i386-opc.h (VexSwapSources): New.
(i386_opcode_modifier): Add vexswapsources.
* i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
with two source operands swapped.
* i386-tbl.h: Regenerated.
This patch fixes a segfault which occurs when the AArch64 backend parses
a symbol operand that begins with a register name and ends with a
unicode byte (byte value > 127).
For example, the following input causes the crash:
x0é: udf x0é
gas/ChangeLog:
2020-07-02 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (reg_name_p): Fix cast so that we don't
segfault on negative chars.
* testsuite/gas/aarch64/reglike-label-unicode-segv.d: New test.
* testsuite/gas/aarch64/reglike-label-unicode-segv.s: Input.
The xc16x md_apply_fix code is just so broken that in my opinion the
target should never have been accepted, and from a quick look at
commit logs for the target it appears that no one has ever contributed
fixes for anything. This target has just been a 14 year burden on
global binutils and cgen maintainers. That's not how free software is
supposed to work.
bfd/
* config.bfd: Obsolete xc16x.
gas/
* config/tc-xc16x.c (md_apply_fix): Add FIXME.
The unprivileged CSR should be controlled by other specific specs rather
than the privileged spec. For example, the debug CSR should be controlled
by the debug spec, and the float CSR should be controlled by the float
spec. User may use assembler options to choose what the debug and other
specs they want, or may encode the versions of specs into the architecture
string directly. Since we haven't decided which one is better, we set the
defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE
in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec
versions for them. However, these PRIV_SPEC_CLASS_NONE will be changed
to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future.
gas/
* config/tc-riscv.c (riscv_csr_class_check): Removed. Move the
checking into riscv_csr_address.
(riscv_csr_version_check): Likewise.
(riscv_csr_address): New function. Return the suitable CSR address
after checking the ISA dependency and versions. Issue warnings if
we find any conflict and -mcsr-check is set. CSR_CLASS_F and
CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
priv spec versions for them.
(reg_csr_lookup_internal): Call riscv_csr_address to find the
suitable CSR address.
* testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the
priv spec warnings here. These warnings are added by accident.
Remove them and only focus on the ISA dependency warnings.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
than the privileged ones.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR.
* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
include/
* opcode/riscv-opc.h: Support the unprivileged CSR. The versions
of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now.
* opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG.
opcodes/
* riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
unprivileged CSR can also be initialized.
Finally; sorry for the delay. There were a few false starts, where I
misinterpreted the error-messages and the comment that Alan added:
it's not the fix size that's too large (and the frag too small), it's
stating the wrong size of what will be "fixed up" - that of the actual
target value, not the size of the field that needs to be adjusted.
Comments added for clarity.
Test-suite committed separately.
gas:
PR gas/25331
* config/tc-mmix.c (md_assemble) <fixup for
BFD_RELOC_MMIX_BASE_PLUS_OFFSET>: This fixup affects 1 byte, not 8.
Also, set its fx_no_overflow.
(md_convert_frag) <case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO)>:
Similarly this fixup affects 4 bytes, not 8 and needs its
fx_no_overflow set.
* config/tc-mmix.h (TC_FX_SIZE_SLACK): Don't define.
To support Intel AMX instructions with 8-bit immediate opcode extension,
but without operands:
tilerelease, 0, 0x49, 0xc0, 1, CpuAMX_TILE|Cpu64, Vex|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { 0 }
process ImmExt without operands.
* config/tc-i386.c (md_assemble): Process ImmExt without
operands.
Rename VecSIB to SIB to support Intel Advanced Matrix Extensions which
introduces instructions with a mandatory SIB byte which isn't a vector
SIB (VSIB).
gas/
* config/tc-i386.c (check_VecOperands): Replace vecsib with sib.
Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128,
VECSIB256 and VECSIB512, respectively.
(build_modrm_byte): Replace vecsib with sib.
opcodes/
* i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
(VecSIB128): Renamed to ...
(VECSIB128): This.
(VecSIB256): Renamed to ...
(VECSIB256): This.
(VecSIB512): Renamed to ...
(VECSIB512): This.
(VecSIB): Renamed to ...
(SIB): This.
(i386_opcode_modifier): Replace vecsib with sib.
* i386-opc.tbl (VexSIB128): New.
(VecSIB256): Likewise.
(VecSIB512): Likewise.
Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VexSIB128, VecSIB256
and VecSIB512, respectively.
This patch adds GNU attribute support to m68k and utilises it to tag the
floating-point calling convention used (hard-float or soft-float). It enables
the linker to ensure linked objects use a consistent floating-point ABI and
allows tools like GDB to infer the ABI used from the ELF file. It is based on
similar work done for PowerPC.
bfd/
* elf32-m68k.c (m68k_elf_merge_obj_attributes): New function.
(elf32_m68k_merge_private_bfd_data): Merge GNU attributes.
binutils/
* readelf.c (display_m68k_gnu_attribute): New function.
(process_arch_specific): Call display_m68k_gnu_attribute for EM_68K.
gas/
* config/tc-m68k.c (m68k_elf_gnu_attribute): New function.
(md_pseudo_table): Handle "gnu_attribute".
* doc/as.texi: Document GNU attribute for M68K.
include/
* elf/m68k.h: Add enum for GNU object attribute with floating point
tag name and values.
ld/
* testsuite/ld-m68k/attr-gnu-4-0.s: New file.
* testsuite/ld-m68k/attr-gnu-4-1.s: Likewise.
* testsuite/ld-m68k/attr-gnu-4-2.s: Likewise.
* testsuite/ld-m68k/attr-gnu-4-00.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-01.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-02.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-10.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-11.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-12.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-20.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-21.d: Likewise.
* testsuite/ld-m68k/attr-gnu-4-22.d: Likewise.
* testsuite/ld-m68k/m68k.exp: Run the new tests.
With abuses of ImmExt gone, all templates using it have operands. Move
its main invocation into process_operands(), matching its secondary one
for the SSE2AVX case.
Use of an explicit data size or REX.W prefix is sufficient indication of
the intended operation when operand size can't be derived from suffix or
register operands. Avoid the ambiguity warning and make in particular
immediate handling (sizing) cope with explicitly specified prefixes.
Extending/reusing the noreg16 test made me notice a few cases of
unintentional 32-bit addressing, which gets corrected at the same time.
Just like for the data size prefix (see commit 7a8655d2bb ["x86: don't
abort() upon DATA16 prefix on (E)VEX encoded insn"]), any form of REX
prefix is invalid with VEX/XOP/EVEX.
Legacy encoded insns do so, and their automatic conversion to AVX ones
ought to produce functionally identical code. Therefore explicit REX
prefixes cannot simply be ignored. This is in particular relevant
because at least PCMPESTR{I,M}'s 64-bit forms couldn't be expressed in
older gas by other than using a REX64 prefix.
The data size prefix alters the meaning of legacy encoded SIMD insns,
and hence shouldn't be accepted there. Use of it also leads to
inconsistencies in SSE2AVX mode. Don't match insns with data size prefix
against SSE2AVX templates.
We should generate the ELF priv attributes only if,
1. The priv attributes are already set in the assembly file.
2. The CSR are explicited used.
3. The privileged instruction are explicited used.
* There are four privileged instruction defined in the v1.11 priv spec:
`mret`, `sret`, `wfi` and `sfence.vma`.
* `sfence.vm` is dropped in the v1.10 priv spec.
* `uret` is actually a N-ext instruction. So it is better to regard it as
an user instruction rather than the priv instruction.
* `hret` is used to return from traps in H-mode. H-mode is removed since
the v1.10 priv spec, but probably be added in the new hypervisor spec.
Therefore, `hret` should be controlled by the hypervisor spec rather than
priv spec in the future.
* `dret` is a debug instruction. We should record the debug spec versions
once it is explicited used in the future.
gas/
* config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to
explicit_priv_attr. It used to indicate CSR or priv instructions are
explictly used.
(riscv_is_priv_insn): Return True if it is a privileged instruction.
(riscv_ip): Call riscv_is_priv_insn to check whether the instruction
is privileged or not. If it is, then set explicit_priv_attr to TRUE.
(riscv_write_out_attrs): Clarification of when to generate the elf
priv spec attributes.
* testsuite/gas/riscv/attribute-11.s: Add comments.
* testsuite/gas/riscv/attribute-14.s: New testcase. Use symbol
`priv_insn_<n>` to decide which priv instruction is expected to used.
(<n> is a to g.)
* testsuite/gas/riscv/attribute-14a.d: Likewise.
* testsuite/gas/riscv/attribute-14b.d: Likewise.
* testsuite/gas/riscv/attribute-14c.d: Likewise.
* testsuite/gas/riscv/attribute-14d.d: Likewise.
* testsuite/gas/riscv/attribute-14e.d: Likewise.
We do know some conflicts among different privileged specs. For linker,
the safest approach is that don't allow the object linked with others which
may cause conflicts. But this may cause inconvenience since not all objects
with conflicting priv specs are linked will cause problems. But it is hard
to know the detailed conflict cases for linker, so we probably need a option
to tell linker that we do know there are no conflicts, or we are willing to
take risks to link the objects with conflicted priv specs. But the option
is still under discussion.
Therefore, we can report warnings rather than errors when linking the objects
with conflicted priv specs. This not only makes the linker more flexible,
but also warns people that the conflicts may happen. We also need to update
the output priv spec version once the input priv spec is newer.
bfd/
* elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from
opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker.
(riscv_get_priv_spec_class): Likewise.
(riscv_get_priv_spec_name): Likewise.
(riscv_get_priv_spec_class_from_numbers): New function, convert
the version numbers into string, then call riscv_get_priv_spec_class
to get the priv spec class.
* elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration
from include/opcode/riscv.h to bfd/elfxx-riscv.h.
(riscv_get_priv_spec_name): Likewise.
(riscv_get_priv_spec_class_from_numbers): New forward declaration.
(opcode/riscv.h): Include it in the header rather than elfxx-riscv.c.
* elfnn-riscv.c (riscv_merge_attributes): Get the priv spec classes
of input and output objects form their priv spec attributes by
riscv_get_priv_spec_class_from_numbers. Report warning rather than
errors when linking objects with differnet priv spec versions. We do
know v1.9.1 may have conflicts to other versions, so report the
warning, too. After that, update the output priv spec version to the
newest one so far.
gas/
* config/tc-riscv.c (buf_size, buf): Remove the unused variables.
(riscv_set_default_priv_spec): Get the priv spec version from the
priv spec attributes by riscv_get_priv_spec_class_from_numbers.
include/
* opcode/riscv.h (riscv_get_priv_spec_class): Move the function
forward declarations to bfd/elfxx-riscv.h.
(riscv_get_priv_spec_name): Likewise.
opcodes/
* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
* riscv-dis.c: Include elfxx-riscv.h.
ld/
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
Upon re-consideration in commit 569d50f1c6 ("x86: further refine SSE
check (SSE4a, SHA, GFNI)") I went too far: Mixing of SSE and AVX insns
doesn't suffer as bad a penalty on AMD CPUs as on Intel ones. SSE4a
being an AMD-only extension, it shouldn't be part of the ISA extensions
set for which the diagnostic may get issued. Undo that part.
2020-06-15 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* elf32-xtensa.c (XSHAL_ABI, XTHAL_ABI_UNDEFINED)
(XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New macros.
(elf32xtensa_abi): New global variable.
(xtensa_abi_choice): New function.
(elf_xtensa_create_plt_entry): Use xtensa_abi_choice instead of
XSHAL_ABI to select PLT code.
gas/
* config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(option_abi_windowed, option_abi_call0): New enum constants.
(md_longopts): Add entries for --abi-windowed and --abi-call0.
(md_parse_option): Add handlers for --abi-windowed and
--abi-call0.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
* doc/as.texi (Target Xtensa options): Add --abi-windowed and
--abi-call0 to the list of options.
* doc/c-xtensa.texi: Add description for options --abi-windowed
and --abi-call0.
* testsuite/gas/xtensa/abi-call0.d: New test definition.
* testsuite/gas/xtensa/abi-windowed.d: New test definition.
* testsuite/gas/xtensa/abi.s: New test source.
include/
* elf/xtensa.h (xtensa_abi_choice): New declaration.
ld/
* emultempl/xtensaelf.em (XSHAL_ABI): Remove macro definition.
(XTHAL_ABI_UNDEFINED, XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
macros.
(elf32xtensa_abi): New declaration.
(xt_config_info_unpack_and_check): Set elf32xtensa_abi if it is
undefined. Use xtensa_abi_choice instead of XSHAL_ABI to test
ABI tag consistency.
(xtensa_add_config_info): Use xtensa_abi_choice instead of
XSHAL_ABI to format ABI tag.
(PARSE_AND_LIST_PROLOGUE): Define OPTION_ABI_WINDOWED,
OPTION_ABI_CALL0 and declare elf32xtensa_abi.
(PARSE_AND_LIST_LONGOPTS): Add entries for --abi-windowed and
--abi-call0.
(PARSE_AND_LIST_OPTIONS): Add help text for --abi-windowed and
--abi-call0.
(PARSE_AND_LIST_ARGS_CASES): Add handlers for --abi-windowed and
--abi-call0.
* ld.texi: Add description for options --abi-windowed and
--abi-call0.
An unwanted side effect of 5990e377e5 ("x86-64: Intel64 adjustments
for insns dealing with far pointers") was that with -mintel64 LCALL and
LJMP would now default to 64-bit operand size. Since 64-bit far branches
aren't portable, the default operand size should still be 32-bit.
However, since the 64-bit variant is permitted, an ambiguous operand
warning should be issued.
As to the actual code change, please note that the conditional
surrounding the switch() that gets adjusted covers several cases which
are of no interest to or benign in 64-bit mode, hence the new
conditional added can be quite a bit less involved.
{vex}, {vex3}, and {evex} are mandatory prefixes, and hence should not
be randomly ignored. Fix this for insns without operands as well as for
insns referencing the high 16 [XYZ]MM registers. To achieve the former,
re-purpose VEX_check_operands(), renaming it to VEX_check_encoding() and
moving its only operand check to check_VecOperands().
This involves fixing a testcase relying on {vex2} to get ignored.
With the introduction of what right now is the very first conditional
in the function's loop (commit dc821c5f9a ["x86: replace Reg8, Reg16,
Reg32, and Reg64"]), the last if() in the same loop has become
pointless - retain just its body.
First of all, these registers have never been available on any 64-bit
CPU, and hence should not be recognized in 64-bit mode. But even before
that they had already disappeared - also don't recognize them when 586
or 686 architectures were explicitly set.
