After thread support over core files was added for GNU/Linux was added,
we started noticing the following type of crash when trying to perform
task switches (this is a bit accademic, since task switching is not
supported when debugging core files - this is what our testcase was
verifying).
(please check out the comment inside ada-tasks.c:task_command for
more details on this topic)
The reason for the crash comes from the fact that the GNU/Linux thread
layer now gets pushed on the target stack, causing the associated
to_get_ada_task_ptid target method to be activated. This routine
makes the assumption that, for all threads, the private area is not
NULL. This is incorrect in the case of core files, as the core layer
creates some threads with no private data.
But, taking a step back, we don't need to try to compute the task ptid,
as we'll never be using it anyways (we only use it for task switching).
So the fix is to avoid the ptid computation altogether when debugging
a core file.
gdb/ChangeLog:
* ada-tasks.c (read_atcb): Do not compute the task ptid when
debugging a core file.
The Blackfin ISA is very exact with regards to address truncation when
under/over flowing its 32bit range. On a 32bit system, things work the
same and so addresses are decoded properly. On a 64bit system though,
the decoded addresses may include the bits that are supposed to have
been truncated. So force a 32bit truncation after the address has been
calculated.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Many register move insns were not being decoded properly, so rewrite
the whole function to be a bit more manageable in terms of valid
combinations.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin disassembler was originally based on the premise of parsing
valid opcodes all the time, so some of the opcode checking can be a bit
fuzzy. This is exemplified in decoding of parallel insns where many
times things are decoded as invalid when in reality, they may not be
used in parallel combinations. So add parallel checking to most insn
decoding routines so we see ILLEGAL and not just whatever insn happens
to be close to a valid mnemonic, as well as some additional sub-opcode
checks.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The push/pop multiple insn has a 3 bit field for the P register range,
but only values of 0...5 are valid (P0 - P5). There is no such P6 or
P7 register, so mark these insns as illegal.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The saturation bit was missed when decoding a vector shift insn
leading to the output looking the same as the non-saturating insn.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
All ASTAT bits work in the hardware even though they aren't part of the
official Blackfin ISA. So decode every ASTAT field to make the output
a bit nicer when working with hand generated opcodes.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Sometimes the encoding in the opcode is a 4 bit field which defines a
register number. However, register numbers are only 0-7, so make sure
we call illegal for when the opcode register number is greater than 8.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
I know a thing or two about Blackfin parts, and if I can't find the
answer, I can usually locate someone who does. Especially since Jie
and Bernd no longer work for ADI :(.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Check for & reject attempts to use multiple store insns in a single
parallel insn combination. These are illegal per the Blackfin ISA.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin ISA supports moving just about anything to/from EMUDAT, so
make sure the assembler accepts these insns too.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Using "Register mismatch" everywhere can be a bit vague, so clarify
why exactly we're barfing on these unsupported insns.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some extended registers when given to the DBG/DBGCMPLX pseudo insns are
not encoded properly. So fix them, fix the display of them when being
disassembled, and add testcases.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Accept any 8bit char with the high bit set so as to support multibyte
characters. Also use the locale safe regular expressions to match
chars/digits. This brings the Blackfin assembler inline with the
behavior of other assemblers.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Support a few more ASTAT bits with the standard insns that operate on
ASTAT bits directly.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The disassembler has partial (but incomplete/broken) support already for
the pseudo debug insn OUTC, so let's fix it up and finish it. And now
that the disassembler can handle it, make sure our assembler can output
it too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT,
ASHIFT, or BXORSHIFT. So be specific when disassembling.
As fall out of this change, we need to update some assembler tests.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
No need for these local structures related to formatting of output to
be writable, so constify the whole shebang.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
There is a pseudo debug insn named ABORT that is commonly used in
simulation, so support it in the assembler too. The disassembler
already supports it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* dwarf2read.c (die_needs_namespace) <DW_TAG_variable>: Add also
DW_TAG_constant.
gdb/testsuite/
* gdb.fortran/module.exp (fully qualified name of DW_TAG_constant):
New test.
* gdb.fortran/module.f90 (mod1) <var_const>: New constant.
We don't use the # character in the Blackfin assembly language, so let it
start end-of-line comments like most other assemblers.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The testcase was failing on various 64bit platforms, because the
debugging info said that the target type for a const type is a
4-byte reference. In the asm file, I used a .long directive, but
the size of .long is of course dependent on the platform. This
replaces this .long by a .4byte directive.
gdb/testsuite/ChangeLog:
* gdb.dwarf2/dw2-const.S: Use .4byte to reference the target
type of our const type.
This patch adds a new --enable-gdbserver=yes/no/auto command-line switch
in gdb/configure. The primary purpose is to allow a user to disable the
build & install of gdbserver when not desired. It also allows the user
to request gdbserver in which case the configure script will abort if
automatic building of gdbserver is not supported for that configuration.
The default keeps things as is: We automatically build gdbserver if
building for a native configuration and if gdbserver is supported for
that configuration.
gdb/ChangeLog:
* configure.ac: Add support for --enable-gdbserver.
* configure: Regenerate.
At AdaCore, this is mostly intended for ia64-linux, where we currently
do not want to distribute gdbserver. This will be useful in the context
of I417-033, where we are now using "make install" to determine what
needs to be packaged inside the GNAT Pro package.
* ldlang.c (lang_add_section): Allow for debugging
section to be marked as noload but to keep content.
(IGNORE_SECTION): Likewise.
(lang_check_section_addresses): Likewise.
* ldwrite.c (build_link_order): Likewise.
* coffcode.h (sec_to_styp_flags): Adjust debug
sections to be conform to pe-coff specification
and avoid marking them as excluded.
(styp_to_sec_flags): Doing reverse mapping.
* gas/testsuite/gas/arm/attr-cpu-directive.d: Update test for change in canonical
CPU name.
* gas/testsuite/gas/arm/attr-mcpu.d: Likewise.
* ld/testsuite/ld-arm/attr-merge-6.attr: Update tests for change in canonical
CPU name.
* ld/testsuite/ld-arm/attr-merge-7.attr: Likewise.
* ld/testsuite/ld-arm/attr-merge-2.attr: Likewise.
* ld/testsuite/ld-arm/attr-merge-arch-2.attr: Likewise.
