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116 Commits

Author SHA1 Message Date
Nelson Chu
e7e599a156 RISC-V: Replace .option rvc/norvc with .option arch, +c/-c. 
Since the .option rvc/norvc directives are obsolete, replace them with
the new proposed diretives: .option arch, +c/-c.  And also reset the
riscv_opts.rvc flag for the .option arch directives.

gas/
	* config/tc-riscv.c (s_riscv_option): Reset the riscv_opts.rvc
	for the .option arch directives.
	* testsuite/gas/riscv/align-1.s: Replace the obsolete .option
	rvc/norvc with .option arch, +c/-c.
	* testsuite/gas/riscv/c-add-addi.s: Likewise.
	* testsuite/gas/riscv/c-nonzero-imm.s: Likewise.
	* testsuite/gas/riscv/c-nonzero-reg.s: Likewise.
	* testsuite/gas/riscv/c-zero-imm-64.s: Likewise.
	* testsuite/gas/riscv/c-zero-imm.s: Likewise.
	* testsuite/gas/riscv/c-zero-reg.s: Likewise.
	* testsuite/gas/riscv/ext.s: Likewise.
	* testsuite/gas/riscv/mapping-01.s: Likewise.
	* testsuite/gas/riscv/mapping-02.s: Likewise.
	* testsuite/gas/riscv/mapping-03.s: Likewise.
	* testsuite/gas/riscv/mapping-04.s: Likewise.
	* testsuite/gas/riscv/no-relax-align-2.s: Likewise.
	* testsuite/gas/riscv/shamt-32.s: Likewise.
	* testsuite/gas/riscv/shamt-64.s: Likewise.
 2021-11-22 19:31:29 +08:00
Nelson Chu
d3ffd7f776 RISC-V: Support new .option arch directive. 
https://github.com/riscv/riscv-asm-manual/pull/67

Format:
.option arch, +<extension><version>, ...
.option arch, -<extension>
.option arch, =<ISA string>

The new direcitve is used to enable/disable extensions for the specific
code region.  For example,

.attribute arch, "rv64ic"   # arch = rv64i2p0_c2p0
.option push
.option arch, +d2p0, -c     # arch = rv64i2p0_f2p0_d2p0, f is added implied
.option arch, =rv32gc       # arch = rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0
.option pop                 # arch = rv64i2p0_c2p0

Note that,
1. ".option rvc/norvc" have the same behavior as ".option arch +c/-c".
2. ".option arch -i" is illegal, since we cannot remove base i extension.
3. If arch=rv64i2p0, then ".option arch, +i3p0" will update the i's version
   from 2.0 to 3.0.
4. If arch=rv64i3p0, then ".option arch, +i" will update the i's version
   from 2.0 to the default one according to the chosen isa spec.

bfd/
	* elfxx-riscv.c (riscv_add_subset): If the subset is already added,
	and the new versions are not RISCV_UNKNOWN_VERSION, then update the
	versions to the subset list.
	(riscv_copy_subset): New function.  Copy the subset from list.
	(riscv_copy_subset_list): New function.  Return the new copyed list.
	(riscv_update_subset): Updated to make .option arch directives workable.
	* elfxx-riscv.h: Updated.
gas/
	* config/tc-riscv.c (riscv_subsets): Defined as a pointer.
	(riscv_rps_as): Init the subset_list to NULL, we will set it later
	once riscv_opts_stack is created or updated.
	(struct riscv_option_stack, riscv_opts_stack): Moved forward.
	(riscv_set_arch): Updated.
	(s_riscv_option): Support new .option arch directive, to add, remove
	or update subsets for the specific code region.
	(riscv_write_out_attrs): Updated.
	* doc/c-riscv.texi: Added document for new .option arch directive.
	* testsuite/gas/riscv/option-arch-01a.d: New testcase.
	* testsuite/gas/riscv/option-arch-01b.d: Likewise.
	* testsuite/gas/riscv/option-arch-01.s: Likewise..
	* testsuite/gas/riscv/option-arch-02.d: Likewise.
	* testsuite/gas/riscv/option-arch-02.s: Likewise.
	* testsuite/gas/riscv/option-arch-fail.d: Likewise.
	* testsuite/gas/riscv/option-arch-fail.l: Likewise.
	* testsuite/gas/riscv/option-arch-fail.s: Likewise.
 2021-11-19 18:50:27 +08:00
Nelson Chu
8155b8539b RISC-V: Support STO_RISCV_VARIANT_CC and DT_RISCV_VARIANT_CC. 
This is the original discussion,
https://github.com/riscv/riscv-elf-psabi-doc/pull/190

And here is the glibc part,
https://sourceware.org/pipermail/libc-alpha/2021-August/129931.html

For binutils part, we need to support a new direcitve: .variant_cc.
The function symbol marked by .variant_cc means it need to be resolved
directly without resolver for dynamic linker.  We also add a new dynamic
entry, STO_RISCV_VARIANT_CC, to indicate there are symbols with the
special attribute in the dynamic symbol table of the object.

I heard that llvm already have supported this in their mainline, so
I think it's time to commit this.

bfd/
	* elfnn-riscv.c (riscv_elf_link_hash_table): Added variant_cc
	flag. It is used to check if relocations for variant CC symbols
	may be present.
	(allocate_dynrelocs): If the symbol has STO_RISCV_VARIANT_CC
	flag, then raise the variant_cc flag of riscv_elf_link_hash_table.
	(riscv_elf_size_dynamic_sections): Added dynamic entry for
	variant_cc.
	(riscv_elf_merge_symbol_attribute): New function, used to merge
	non-visibility st_other attributes, including STO_RISCV_VARIANT_CC.
binutils/
	* readelf.c (get_riscv_dynamic_type): New function.
	(get_dynamic_type): Called get_riscv_dynamic_type for riscv targets.
	(get_riscv_symbol_other): New function.
	(get_symbol_other): Called get_riscv_symbol_other for riscv targets.
gas/
	* config/tc-riscv.c (s_variant_cc): Marked symbol that it follows a
	variant CC convention.
	(riscv_elf_copy_symbol_attributes): Same as elf_copy_symbol_attributes,
	but without copying st_other.  If a function symbol has special st_other
	value set via directives, then attaching an IFUNC resolver to that symbol
	should not override the st_other setting.
	(riscv_pseudo_table): Support variant_cc diretive.
	* config/tc-riscv.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Defined.
	* testsuite/gas/riscv/variant_cc-set.d: New testcase.
	* testsuite/gas/riscv/variant_cc-set.s: Likewise.
	* testsuite/gas/riscv/variant_cc.d: Likewise.
	* testsuite/gas/riscv/variant_cc.s: Likewise.
include/
	* elf/riscv.h (DT_RISCV_VARIANT_CC): Defined to (DT_LOPROC + 1).
	(STO_RISCV_VARIANT_CC): Defined to 0x80.
ld/
	* testsuite/ld-riscv-elf/variant_cc-1.s: New testcase.
	* testsuite/ld-riscv-elf/variant_cc-2.s: Likewise.
	* testsuite/ld-riscv-elf/variant_cc-now.d: Likewise.
	* testsuite/ld-riscv-elf/variant_cc-r.d: Likewise.
	* testsuite/ld-riscv-elf/variant_cc-shared.d: Likewise.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
 2021-11-19 09:32:19 +08:00
jiawei
de83e5142d RISC-V: Add instructions and operand set for z[fdq]inx 
Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to
verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.

bfd/ChangeLog:

* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
  z*inx extension.

gas/ChangeLog:

* config/tc-riscv.c (riscv_ip): Added register choice for z*inx.

include/ChangeLog:

* opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.

opcodes/ChangeLog:

* riscv-dis.c (riscv_disassemble_insn): Added disassemble check for
  z*inx.
* riscv-opc.c: Reused INSN_CLASS_* for z*inx.

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
 2021-11-18 14:43:23 +08:00
Nelson Chu
65e4a99a26 RISC-V: Support rvv extension with released version 1.0. 
2021-11-17  Jim Wilson  <jimw@sifive.com>
            Kito Cheng  <kito.cheng@sifive.com>
            Nelson Chu  <nelson.chu@sifive.com>

This patch is porting from the following riscv github,
https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x

And here is the vector spec,
https://github.com/riscv/riscv-v-spec

bfd/
	* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules
	of v, zve and zvl extensions.
	(riscv_supported_std_ext): Updated verison of v to  1.0.
	(riscv_supported_std_z_ext): Added zve and zvl extensions.
	(riscv_parse_check_conflicts): The zvl extensions need to
	enable either v or zve extension.
	(riscv_multi_subset_supports): Check the subset list to know
	if the INSN_CLASS_V and INSN_CLASS_ZVEF instructions are supported.
gas/
	* config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_V.
	(enum reg_class): Added RCLASS_VECR and RCLASS_VECM.
	(validate_riscv_insn): Check whether the rvv operands are valid.
	(md_begin): Initialize register hash for rvv registers.
	(macro_build): Added rvv operands when expanding rvv pseudoes.
	(vector_macro): Expand rvv macros into one or more instructions.
	(macro): Likewise.
	(my_getVsetvliExpression): Similar to my_getVsetvliExpression,
	but used for parsing vsetvli operands.
	(riscv_ip): Parse and encode rvv operands.  Besides, The rvv loads
	and stores with EEW 64 cannot be used when zve32x is enabled.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated -march
	to rv32ifv_zkr.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg.s: Added rvv csr testcases.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/march-imply-v.d: New testcase.
	* testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Likewise.
	* testsuite/gas/riscv/vector-insns-fail-zve32xf.l: Likewise.
	* testsuite/gas/riscv/vector-insns-fail-zvl.d: Likewise.
	* testsuite/gas/riscv/vector-insns-fail-zvl.l: Likewise.
	* testsuite/gas/riscv/vector-insns-vmsgtvx.d: Likewise.
	* testsuite/gas/riscv/vector-insns-vmsgtvx.s: Likewise.
	* testsuite/gas/riscv/vector-insns-zero-imm.d: Likewise.
	* testsuite/gas/riscv/vector-insns-zero-imm.s: Likewise.
	* testsuite/gas/riscv/vector-insns.d: Likewise.
	* testsuite/gas/riscv/vector-insns.s: Likewise.
include/
	* opcode/riscv-opc.h: Defined mask/match encodings and csrs for rvv.
	* opcode/riscv.h: Defined rvv immediate encodings and fields.
	(enum riscv_insn_class): Added INSN_CLASS_V and INSN_CLASS_ZVEF.
	(INSN_V_EEW64): Defined.
	(M_VMSGE, M_VMSGEU): Added for the rvv pseudoes.
opcodes/
	* riscv-dis.c (print_insn_args): Dump the rvv operands.
	* riscv-opc.c (riscv_vecr_names_numeric): Defined rvv registers.
	(riscv_vecm_names_numeric): Likewise.
	(riscv_vsew): Likewise.
	(riscv_vlmul): Likewise.
	(riscv_vta): Likewise.
	(riscv_vma): Likewise.
	(match_vs1_eq_vs2): Added for rvv Vu operand.
	(match_vd_eq_vs1_eq_vs2): Added for rvv Vv operand.
	(riscv_opcodes): Added rvv v1.0 instructions.
 2021-11-17 20:18:11 +08:00
jiawei
3d1cafa0c6 RISC-V: Scalar crypto instructions and operand set. 
Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from
zbb,zbc, we just change the class attribute to make them both support.
The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd
and Zkne extensions on rv64.  Add new operand letter 'y' to present 'bs'
symbol and 'Y' to present 'rnum' symbolc  for zkn instructions.  Also add
a new Entropy Source CSR define 'seed' located at address 0x015.

bfd/
	* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
	crypto extension.
gas/
	*config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_ZKR.
	(riscv_csr_address): Checked for CSR_CLASS_ZKR.
	(validate_riscv_insn): Added y and Y for bs and rnum operands.
	(riscv_ip): Handle y and Y operands.
include/
	* opcode/riscv-opc.h: Added encodings of crypto instructions.
	Also defined new csr seed, which address is 0x15.
	* opcode/riscv.h: Defined OP_* and INSN_CLASS_* for crypto.
opcodes/
	* riscv-dis.c (print_insn_args): Recognized new y and Y operands.
	* riscv-opc.c (riscv_opcodes): Added crypto instructions.
 2021-11-16 11:47:55 +08:00
Nelson Chu
f786c359c1 RISC-V: Dump objects according to the elf architecture attribute. 
For now we should always generate the elf architecture attribute both for
elf and linux toolchains, so that we could dump the objects correctly
according to the generated architecture string.  This patch resolves the
problem that we probably dump an object with c.nop instructions, but
in fact the c extension isn't allowed.  Consider the following case,

nelson@LAPTOP-QFSGI1F2:~/test$ cat temp.s
.option norvc
.option norelax
.text
add     a0, a0, a0
.byte   0x1
.balign 16
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-as temp.s -o temp.o
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o

temp.o:     file format elf32-littleriscv

Disassembly of section .text:

00000000 <.text>:
   0:   00a50533                add     a0,a0,a0
   4:   01                      .byte   0x01
   5:   00                      .byte   0x00
   6:   0001                    nop
   8:   00000013                nop
   c:   00000013                nop
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-readelf -A temp.o
Attribute Section: riscv
File Attributes
  Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"

The c.nop at address 0x6 is generated for alignment, but since the rvc isn't
allowed for this object, dump it as a c.nop instruction looks wrong.  After
applying this patch, I get the following result,

nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o

temp.o:     file format elf32-littleriscv

Disassembly of section .text:

00000000 <.text>:
   0:   00a50533                add     a0,a0,a0
   4:   01                      .byte   0x01
   5:   00                      .byte   0x00
   6:   0001                    .2byte  0x1
   8:   00000013                nop
   c:   00000013                nop

For the current objdump, we dump data to .byte/.short/.word/.dword, and
dump the unknown or unsupported instructions to .2byte/.4byte/.8byte, which
respectively are 2, 4 and 8 bytes instructions.  Therefore, we shouldn't
dump the 0x0001 as a c.nop instruction in the above case, we should dump
it to .2byte 0x1 as a unknown instruction, since the rvc is disabled.

However, consider that some people may use the new objdump to dump the old
objects, which don't have any elf attributes.  We usually set the default
architecture string to rv64g by bfd/elfxx-riscv.c:riscv_set_default_arch.
But this will cause rvc instructions to be unrecognized.  Therefore, we
set the default architecture string to rv64gc for disassembler, to keep
the previous behavior.

This patch pass the riscv-gnu-toolchain gcc/binutils regressions for
rv32emc-elf, rv32gc-linux, rv32i-elf, rv64gc-elf and rv64gc-linux
toolchains.  Also, tested by --enable-targets=all and can build
riscv-gdb successfully.

bfd/
	* elfnn-riscv.c (riscv_merge_arch_attr_info): Tidy the
	codes for riscv_parse_subset_t setting.
	* elfxx-riscv.c (riscv_get_default_ext_version): Updated.
	(riscv_subset_supports): Moved from gas/config/tc-riscv.c.
	(riscv_multi_subset_supports): Likewise.
	* elfxx-riscv.h: Added extern for riscv_subset_supports and
	riscv_multi_subset_supports.
gas/
	* config/tc-riscv.c (riscv_subset_supports): Moved to
	bfd/elfxx-riscv.c.
	(riscv_multi_subset_supports): Likewise.
	(riscv_rps_as): Defined for architectrue parser.
	(riscv_set_arch): Updated.
	(riscv_set_abi_by_arch): Likewise.
	(riscv_csr_address): Likewise.
	(reg_lookup_internal): Likewise.
	(riscv_ip): Likewise.
	(s_riscv_option): Updated.
	* testsuite/gas/riscv/mapping-04b.d: Updated.
	* testsuite/gas/riscv/mapping-norelax-03b.d: Likewise.
	* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
opcodes/
	* riscv-dis.c: Include elfxx-riscv.h since we need the
	architecture parser.  Also removed the cpu-riscv.h, it
	is already included in elfxx-riscv.h.
	(default_isa_spec): Defined since the parser need this
	to set the default architecture string.
	(xlen): Moved out from riscv_disassemble_insn as a global
	variable, it is more convenient to initialize riscv_rps_dis.
	(riscv_subsets): Defined to recoed the supported
	extensions.
	(riscv_rps_dis): Defined for architectrue parser.
	(riscv_disassemble_insn): Call riscv_multi_subset_supports
	to make sure if the instructions are valid or not.
	(print_insn_riscv): Initialize the riscv_subsets by parsing
	the elf architectrue attribute.  Otherwise, set the default
	architectrue string to rv64gc.
 2021-11-11 16:59:13 +08:00
Nelson Chu
edc77c591a RISC-V: Clarify the behavior of .option rvc or norvc. 
Add/Remove the rvc extension to/from the riscv_subsets once the
.option rvc/norvc is set.  So that we don't need to always check
the riscv_opts.rvc in the riscv_subset_supports, just call the
riscv_lookup_subset to search the subset list is enough.

Besides, we will need to dump the instructions according to the
elf architecture attributes.  That means the dis-assembler needs
to parse the architecture string from the elf attribute before
dumping any instructions, and also needs to recognized the
INSN_CLASS* classes from riscv_opcodes.  Therefore, I suppose
some functions will need to be moved from gas/config/tc-riscv.c
to bfd/elfxx-riscv.c, including riscv_multi_subset_supports and
riscv_subset_supports.  This is one of the reasons why we need
this patch.

This patch passes the gcc/binutils regressions of rv32emc-elf,
rv32i-elf, rv64gc-elf and rv64gc-linux toolchains.

bfd/
	* elfxx-riscv.c (riscv_remove_subset): Remove the extension
	from the subset list.
	(riscv_update_subset): Add/Remove an extension to/from the
	subset list.  This is used for the .option rvc or norvc.
	* elfxx-riscv.h: Added the extern bool riscv_update_subset.
gas/
	* config/tc-riscv.c (riscv_set_options): Removed the unused
	rve flag.
	(riscv_opts): Likewise.
	(riscv_set_rve): Removed.
	(riscv_subset_supports): Removed the riscv_opts.rvc check.
	(riscv_set_arch): Don't need to call riscv_set_rve.
	(reg_lookup_internal): Call riscv_subset_supports to check
	whether the rve is supported.
	(s_riscv_option): Add/Remove the rvc extension to/from the
	subset list once the .option rvc/norvc is set.
 2021-11-04 17:46:09 +08:00
Nelson Chu
437e2ff1ad RISC-V: Tidy riscv assembler and disassembler. 
Tidy the gas/config/tc-riscv.c and opcodes/riscv-dis.c, to prepare for
moving the released extensions (including released vendor extensions)
from integration branch back to mainline.

* Added parts of missing comments.

* Updated md_show_usage.

* For validate_riscv_insn, riscv_ip and print_insn_args, unify the
  following pointer names,
  - oparg: pointed to the parsed operand defined in the riscv_opcodes.
  - asarg: pointed to the parsed operand from assembly.
  - opargStart: recorded the parsed operand name from riscv_opcodes.
  - asargStart: recorded the parsed operand name from assembly.

gas/
	* config/tc-riscv.c: Added parts of missind comments and updated
	the md_show_usage.
	(riscv_multi_subset_supports): Tidy codes.
	(validate_riscv_insn): Unify the pointer names, oparg, asarg,
	opargStart and asargStart, to prepare for moving the released
	extensions from integration branch back to mainline.
	(riscv_ip): Likewise.
	(macro_build): Added fmtStart, also used to prepare for moving
	released extensions.
	(md_show_usage): Added missing descriptions for new options.
opcodes/
	* riscv-dis.c (print_insn_args): Unify the pointer names,
	oparg and opargStart, to prepare for moving the released
	extensions from integration branch back to mainline.
 2021-10-27 21:22:26 +08:00
Philipp Tomsich
9455c91957 RISC-V: Add support for Zbs instructions 
This change adds the Zbs instructions from the Zbs 1.0.0 specification.
See
  https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
for the frozen specification.

2021-01-09  Philipp Tomsich  <philipp.tomsich@vrull.eu>

    bfd/
	* elfxx-riscv.c (riscv_supported_std_z_ext): Added zbs.
    gas/
	* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZBS.
	* testsuite/gas/riscv/b-ext.d: Test Zbs instructions.
	* testsuite/gas/riscv/b-ext.s: Likewise.
	* testsuite/gas/riscv/b-ext-64.d: Likewise.
	* testsuite/gas/riscv/b-ext-64.s: Likewise.
    include/
	* opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for Zbs.
	* opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZBS.
    opcodes/
	* riscv-opc.c (riscv_supported_std_z_ext): Add zbs.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 2021-10-07 17:09:25 +08:00
Nelson Chu
c9f2799101 RISC-V: Merged extension string tables and their version tables into one. 
There are two main reasons for this patch,

* In the past we had two extension tables, one is used to record all
supported extensions in bfd/elfxx-riscv.c, another is used to get the
default extension versions in gas/config/tc-riscv.c.  It is hard to
maintain lots of tables in different files, but in fact we can merge
them into just one table.  Therefore, we now define many riscv_supported_std*
tables, which record names and versions for all supported extensions.
We not only use these tables to initialize the riscv_ext_order, but
also use them to get the default versions of extensions, and decide if
the extensions should be enbaled by default.

* We add a new filed `default_enable' for the riscv_supported_std* tables,
to decide if the extension should be enabled by default.  For now if the
`default_enable' field of the extension is set to EXT_DEFAULT, then we
should enable the extension when the -march and elf architecture attributes
are not set.  In the future, I suppose the `default_enable' can be set
to lots of EXT_<VENDOR>, each vendor can decide to open which extensions,
when the target triple of vendor is chosen.

The elf/linux regression tests of riscv-gnu-toolchain are passed.

bfd/
	* elfnn-riscv.c (cpu-riscv.h): Removed sine it is included in
	bfd/elfxx-riscv.h.
	(riscv_merge_std_ext): Updated since the field of rpe is changed.
	* elfxx-riscv.c (cpu-riscv.h): Removed.
	(riscv_implicit_subsets): Added implicit extensions for g.
	(struct riscv_supported_ext): Used to be riscv_ext_version.  Moved
	from gas/config/tc-riscv.c, and added new field `default_enable' to
	decide if the extension should be enabled by default.
	(EXT_DEFAULT): Defined for `default_enable' field.
	(riscv_supported_std_ext): It used to return the supported standard
	architecture string, but now we move ext_version_table from
	gas/config/tc-riscv.c to here, and rename it to riscv_supported_std_ext.
	Currently we not only use the table to initialize riscv_ext_order, but
	also get the default versions of extensions, and decide if the extensions
	should be enbaled by default.
	(riscv_supported_std_z_ext): Likewise, but is used for z* extensions.
	(riscv_supported_std_s_ext): Likewise, but is used for s* extensions.
	(riscv_supported_std_h_ext): Likewise, but is used for h* extensions.
	(riscv_supported_std_zxm_ext): Likewise, but is used for zxm* extensions.
	(riscv_all_supported_ext): Includes all supported extension tables.
	(riscv_known_prefixed_ext): Updated.
	(riscv_valid_prefixed_ext): Updated.
	(riscv_init_ext_order): Init the riscv_ext_order table according to
	riscv_supported_std_ext.
	(riscv_get_default_ext_version): Moved from gas/config/tc-riscv.c.
	Get the versions of extensions from riscv_supported_std* tables.
	(riscv_parse_add_subset): Updated.
	(riscv_parse_std_ext): Updated.
	(riscv_set_default_arch): Set the default subset list according to
	the default_enable field of riscv_supported_*ext tables.
	(riscv_parse_subset): If the input ARCH is NULL, then we call
	riscv_set_default_arch to set the default subset list.
	* elfxx-riscv.h (cpu-riscv.h): Included.
	(riscv_parse_subset_t): Removed get_default_version field, and added
	isa_spec field to replace it.
	(extern riscv_supported_std_ext): Removed.
gas/
	* (bfd/cpu-riscv.h): Removed.
	(struct riscv_ext_version): Renamed and moved to bfd/elfxx-riscv.c.
	(ext_version_table): Likewise.
	(riscv_get_default_ext_version): Likewise.
	(ext_version_hash): Removed.
	(init_ext_version_hash): Removed.
	(riscv_set_arch): Updated since the field of rps is changed.  Besides,
	report error when the architecture string is empty.
	(riscv_after_parse_args): Updated.
 2021-09-17 16:33:54 +08:00
Nelson Chu
a262b82fdb RISC-V: Extend .insn directive to support hardcode encoding. 
The .insn directive can let users use their own instructions, or
some new instruction, which haven't supported in the old binutils.
For example, if users want to use sifive cache instruction, they
cannot just write "cflush.d1.l1" in the assembly code, they should
use ".insn i SYSTEM, 0, x0, x10, -0x40".  But the .insn directive
may not easy to use for some cases, and not so friendly to users.
Therefore, I believe most of the users will use ".word 0xfc050073",
to encode the instructions directly, rather than use .insn.  But
once we have supported the mapping symbols, the .word directives
are marked as data, so disassembler won't dump them as instructions
as usual.  I have discussed this with Kito many times, we all think
extend the .insn direcitve to support the hardcode encoding, is the
easiest way to resolve the problem.  Therefore, there are two more
.insn formats are proposed as follows,

(original) .insn <type>, <operand1>, <operand2>, ...
           .insn <insn-length>, <value>
           .insn <value>

The <type> is string, and the <insn-length> and <value> are constants.

gas/
	* config/tc-riscv.c (riscv_ip_hardcode): Similar to riscv_ip,
	but assembles an instruction according to the hardcode values
	of .insn directive.
	* doc/c-riscv.texi: Document two new .insn formats.
	* testsuite/gas/riscv/insn-fail.d: New testcases.
	* testsuite/gas/riscv/insn-fail.l: Likewise.
	* testsuite/gas/riscv/insn-fail.s: Likewise.
	* testsuite/gas/riscv/insn.d: Updated.
	* testsuite/gas/riscv/insn.s: Likewise.
 2021-08-31 12:50:27 +08:00
Nelson Chu
9b9b1092f0 RISC-V: PR27916, Support mapping symbols. 
Similar to ARM/AARCH64, we add mapping symbols in the symbol table,
to mark the start addresses of data and instructions.  The $d means
data, and the $x means instruction.  Then the disassembler uses these
symbols to decide whether we should dump data or instruction.

Consider the mapping-04 test case,
$ cat tmp.s
  .text
  .option norelax
  .option norvc
  .fill 2, 4, 0x1001
  .byte 1
  .word 0
  .balign 8
  add a0, a0, a0
  .fill 5, 2, 0x2002
  add a1, a1, a1
  .data
  .word 0x1             # No need to add mapping symbols.
  .word 0x2

$ riscv64-unknown-elf-as tmp.s -o tmp.o
$ riscv64-unknown-elf-objdump -d tmp.o

Disassembly of section .text:

0000000000000000 <.text>:
   0:   00001001         .word   0x00001001  # Marked $d, .fill directive.
   4:   00001001         .word   0x00001001
   8:   00000001         .word   0x00000001  # .byte + part of .word.
   c:   00               .byte   0x00        # remaining .word.
   d:   00               .byte   0x00        # Marked $d, odd byte of alignment.
   e:   0001             nop                 # Marked $x, nops for alignment.
  10:   00a50533         add     a0,a0,a0
  14:   20022002         .word   0x20022002  # Marked $d, .fill directive.
  18:   20022002         .word   0x20022002
  1c:   2002             .short  0x2002
  1e:   00b585b3         add     a1,a1,a1    # Marked $x.
  22:   0001             nop                 # Section tail alignment.
  24:   00000013         nop

* Use $d and $x to mark the distribution of data and instructions.
  Alignments of code are recognized as instructions, since we usually
  fill nops for them.

* If the alignment have odd bytes, then we cannot just fill the nops
  into the spaces.  We always fill an odd byte 0x00 at the start of
  the spaces.  Therefore, add a $d mapping symbol for the odd byte,
  to tell disassembler that it isn't an instruction.  The behavior
  is same as Arm and Aarch64.

The elf/linux toolchain regressions all passed.  Besides, I also
disable the mapping symbols internally, but use the new objudmp, the
regressions passed, too.  Therefore, the new objudmp should dump
the objects corretly, even if they don't have any mapping symbols.

bfd/
	pr 27916
	* cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols.
	* cpu-riscv.h: extern riscv_elf_is_mapping_symbols.
	* elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping
	symbols as a function name.
	(riscv_elf_is_target_special_symbol): Add mapping symbols.
binutils/
	pr 27916
	* testsuite/binutils-all/readelf.s: Updated.
	* testsuite/binutils-all/readelf.s-64: Likewise.
	* testsuite/binutils-all/readelf.s-64-unused: Likewise.
	* testsuite/binutils-all/readelf.ss: Likewise.
	* testsuite/binutils-all/readelf.ss-64: Likewise.
	* testsuite/binutils-all/readelf.ss-64-unused: Likewise.
gas/
	pr 27916
	* config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol.
	(riscv_mapping_state): Decide whether to create mapping symbol for
	frag_now.  Only add the mapping symbols to text sections.
	(riscv_add_odd_padding_symbol): Add the mapping symbols for the
	riscv_handle_align, which have odd bytes spaces.
	(riscv_check_mapping_symbols): Remove any excess mapping symbols.
	(md_assemble): Marked as MAP_INSN.
	(riscv_frag_align_code): Marked as MAP_INSN.
	(riscv_init_frag): Add mapping symbols for frag, it usually called
	by frag_var.  Marked as MAP_DATA for rs_align and rs_fill, and
	marked as MAP_INSN for rs_align_code.
	(s_riscv_insn): Marked as MAP_INSN.
	(riscv_adjust_symtab): Call riscv_check_mapping_symbols.
	* config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state
	with MAP_DATA.
	(TC_SEGMENT_INFO_TYPE): Record mapping state for each segment.
	(TC_FRAG_TYPE): Record the first and last mapping symbols for the
	fragments.  The first mapping symbol must be placed at the start
	of the fragment.
	(TC_FRAG_INIT): Defined to riscv_init_frag.
	* testsuite/gas/riscv/mapping-01.s: New testcase.
	* testsuite/gas/riscv/mapping-01a.d: Likewise.
	* testsuite/gas/riscv/mapping-01b.d: Likewise.
	* testsuite/gas/riscv/mapping-02.s: Likewise.
	* testsuite/gas/riscv/mapping-02a.d: Likewise.
	* testsuite/gas/riscv/mapping-02b.d: Likewise.
	* testsuite/gas/riscv/mapping-03.s: Likewise.
	* testsuite/gas/riscv/mapping-03a.d: Likewise.
	* testsuite/gas/riscv/mapping-03b.d: Likewise.
	* testsuite/gas/riscv/mapping-04.s: Likewise.
	* testsuite/gas/riscv/mapping-04a.d: Likewise.
	* testsuite/gas/riscv/mapping-04b.d: Likewise.
	* testsuite/gas/riscv/mapping-norelax-04a.d: Likewise.
	* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
	* testsuite/gas/riscv/no-relax-align.d: Updated.
	* testsuite/gas/riscv/no-relax-align-2.d: Likewise.
include/
	pr 27916
	* opcode/riscv.h (enum riscv_seg_mstate): Added.

opcodes/
	pr 27916
	* riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state):
	Added to dump sections with mapping symbols.
	(riscv_get_map_state): Get the mapping state from the symbol.
	(riscv_search_mapping_symbol): Check the sorted symbol table, and
	then find the suitable mapping symbol.
	(riscv_data_length): Decide which data size we should print.
	(riscv_disassemble_data): Dump the data contents.
	(print_insn_riscv): Handle the mapping symbols.
	(riscv_symbol_is_valid): Marked mapping symbols as invalid.
 2021-08-30 17:36:11 +08:00
Alan Modra
4bf094292c as_bad_subtract 
Many places report errors of the nature "can't resolve a - b".
This provides a utility function to report such errors consistently.
I removed the section reporting and quotes around symbol names while I
was at it.  Compare
ifunc-2.s:4: Error: can't resolve `bar1' {.text.1 section} - `foo1' {.text.1 section}
with
ifunc-2.s:4: Error: can't resolve bar1 - foo1

In many cases the section names don't help the user very much in
figuring out what went wrong, and the quotes if present arguably ought
to be placed around the entire expression:
can't resolve `bar1 - foo1'

The patch also tidies some tc_get_reloc functions that leak memory on
error paths.

	* write.h (as_bad_subtract): Declare.
	* write.c (as_bad_subtract): New function.
	(fixup_segment): Use as_bad_subtract.
	* config/tc-arc.c (md_apply_fix): Likewise.
	* config/tc-avr.c (md_apply_fix, tc_gen_reloc): Likewise.
	* config/tc-cris.c (md_apply_fix): Likewise.
	* config/tc-d10v.c (md_apply_fix): Likewise.
	* config/tc-d30v.c (md_apply_fix): Likewise.
	* config/tc-ft32.c (md_apply_fix): Likewise.
	* config/tc-h8300.c (tc_gen_reloc): Likewise.
	* config/tc-m68hc11.c (md_apply_fix): Likewise.
	* config/tc-mmix.c (mmix_frob_file): Likewise.
	* config/tc-mn10200.c (tc_gen_reloc): Likewise.
	* config/tc-nds32.c (nds32_apply_fix): Likewise.
	* config/tc-pru.c (md_apply_fix): Likewise.
	* config/tc-riscv.c (md_apply_fix): Likewise.
	* config/tc-s12z.c (md_apply_fix): Likewise.
	* config/tc-s390.c (md_apply_fix): Likewise.
	* config/tc-tilegx.c (md_apply_fix): Likewise.
	* config/tc-tilepro.c (md_apply_fix): Likewise.
	* config/tc-v850.c (md_apply_fix): Likewise.
	* config/tc-vax.c (md_apply_fix): Likewise.
	* config/tc-xc16x.c (tc_gen_reloc): Likewise.
	* config/tc-xgate.c (md_apply_fix): Likewise.
	* config/tc-xstormy16.c (xstormy16_md_apply_fix): Likewise.
	* config/tc-xtensa.c (md_apply_fix): Likewise.
	* config/tc-z80.c (tc_gen_reloc): Likewise.
	* config/tc-spu.c (md_apply_fix): Likewise.
	(tc_gen_reloc): Delete dead code.  Free memory on error.
	* config/tc-cr16.c (tc_gen_reloc): Use as_bad_subtract.  Free
	on error.
	* config/tc-crx.c (tc_gen_reloc): Likewise.
	* config/tc-ppc.c (tc_gen_reloc): Likewise.
	* testsuite/gas/i386/ifunc-2.l: Adjust to suit changed error message.
	* testsuite/gas/mips/lui-2.l: Likewise.
	* testsuite/gas/tic6x/reloc-bad-1.l: Likewise.
 2021-07-21 19:35:34 +09:30
Yuri Chornoivan
579f0281f3 PR 28053: Fix spelling mistakes: usupported -> unsupported and relocatation -> relocation. 2021-07-06 14:56:05 +01:00
Nelson Chu
28b2963ffb RISC-V: Update the riscv_opts.[rvc|rve] in the riscv_set_arch. 
We also need to update the riscv_opts.[rvc|rve] for elf attributes.
Otherwise, the following case will fail,

$ cat cadd.s
.attribute arch, "rv64gc"
c.add   a0, a1
$ riscv64-unknown-elf-as cadd.s -o cadd.o
cadd.s: Assembler messages:
cadd.s:2: Error: illegal operands `c.add a0,a1

After applying this patch,

$ riscv64-unknown-elf-as cadd.s -o cadd.o
$ riscv64-unknown-elf-objdump -d cadd.o

cadd.o:     file format elf64-littleriscv

Disassembly of section .text:

0000000000000000 <.text>:
   0:   952e                    add     a0,a0,a1
        ...

gas/
    * config/tc-riscv.c (riscv_set_arch): Call riscv_set_rvc
    and riscv_set_rve both for -march and elf attributes.
    (riscv_after_parse_args): Likewise.
 2021-06-11 17:34:54 +08:00
Nelson Chu
fe1f847d9a RISC-V: Allow to link the objects with unknown prefixed extensions. 
Since the policies of GNU and llvm toolchain are different for now,
current binutils mainline cannot accept any draft extensions, including
rvv, zfh, ....  The Clang/LLVM allows these draft stuff on mainline,
but the GNU ld might be used with them, so this causes the link time
problems.

The patch allows ld to link the objects with unknown prefixed extensions,
which are probably generated by LLVM or customized toolchains.

bfd/
    * elfxx-riscv.h (check_unknown_prefixed_ext): New bool.
    * elfxx-riscv.c (riscv_parse_prefixed_ext): Do not check the
    prefixed extension name if check_unknown_prefixed_ext is false.
    * elfnn-riscv.c (riscv_merge_arch_attr_info): Set
    check_unknown_prefixed_ext to false for linker.
gas/
    * config/tc-riscv.c (riscv_set_arch): Set
    check_unknown_prefixed_ext to true for assembler.
 2021-05-26 11:02:29 +08:00
Nelson Chu
5d0ed830d3 RISC-V: PR25212, Report errors for invalid march and mabi combinations. 
This patch clarify the following invalid combinations of march and mabi,
* ilp32f/lp64f abi without f extension.
* ilp32d/lp64d abi without d extension.
* ilp32q/lp64q abi without q extension.
* e extension with any abi except ilp32e

GNU assembler reports errors when finding the above invalid combinations.
But LLVM-MC reports warnings and ignores these invalid cases.  It help to
set the correct ilp32/lp64/ilp32e abi according to rv32/rv64/rve.  This
looks good and convenient, so perhaps we can do the same things.  However,
if you don't set the mabi, GNU assembler also try to set the suitable
ABI according to march/elf-attribute.  Compared to LLVM-MC, we will choose
double/quad abi if d/f extension is set.

gas/
    PR 25212
    * config/tc-riscv.c (riscv_set_abi_by_arch): If -mabi isn't set, we
    will choose ilp32e abi for rv32e.  Besides, report errors for the
    invalid march and mabi combinations.
    * testsuite/gas/riscv/mabi-attr-rv32e.s: New testcase.  Only accept
    ilp32e abi for rve extension.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.d: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.d: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
    * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.q: Likewise.
    Renamed all mabi testcases to their march-mabi settings.
 2021-05-24 11:47:18 +08:00
Nelson Chu
768589d180 RISC-V: PR27436, make operand C> work the same as >. 
gas/
    PR 27436
    * config/tc-riscv.c (riscv_ip): make operand C> work the same as >.
    * testsuite/gas/riscv/shamt-32.d: New testcase.
    * testsuite/gas/riscv/shamt-32.l: Likewise.
    * testsuite/gas/riscv/shamt-32.s: Likewise.
    * testsuite/gas/riscv/shamt-64.d: Likewise.
    * testsuite/gas/riscv/shamt-64.l: Likewise.
    * testsuite/gas/riscv/shamt-64.s: Likewise.
 2021-04-16 17:03:29 +08:00
Alan Modra
5b7c81bd8c Use bool in gas 
* as.h (POISON_BFD_BOOLEAN): Define.
	* as.c, * as.h, * atof-generic.c, * config/atof-ieee.c,
	* config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c,
	* config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c,
	* config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c,
	* config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h,
	* config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c,
	* config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c,
	* config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c,
	* config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h,
	* config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c,
	* config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h,
	* config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c,
	* config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c,
	* config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c,
	* config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h,
	* config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c,
	* config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h,
	* config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c,
	* config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h,
	* config/tc-metag.c, * config/tc-metag.h,
	* config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h,
	* config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c,
	* config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c,
	* config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h,
	* config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c,
	* config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h,
	* config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c,
	* config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h,
	* config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c,
	* config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c,
	* config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c,
	* config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c,
	* config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c,
	* config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h,
	* config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c,
	* config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c,
	* config/tc-xstormy16.c, * config/tc-xstormy16.h,
	* config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c,
	* config/tc-z8k.c, * config/xtensa-istack.h,
	* config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c,
	* dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c,
	* frags.h, * listing.c, * macro.c, * output-file.c, * read.c,
	* read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean
	with bool, FALSE with false, and TRUE with true.
 2021-03-31 10:49:23 +10:30
Kuan-Lin Chen
80d49d6a1b RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions 
bfd/
	* elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc.

gas/
	* config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc.
	(riscv_multi_subset_supports): Add INSN_CLASS_ZB*.
	* testsuite/gas/riscv/b-ext-64.s: Bitmanip test case.
	* testsuite/gas/riscv/b-ext-64.d: Likewise.
	* testsuite/gas/riscv/b-ext.s: Likewise.
	* testsuite/gas/riscv/b-ext.d: Likewise.

include/
	* opcode/riscv-opc.h: Support zba, zbb and zbc extensions.
	* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*.

opcodes/
	* riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 2021-03-16 14:38:19 +08:00
Nick Clifton
0257c2ff4f Fix compile time warnings when building riscv assembler. 
* config/tc-riscv.c (riscv_ip): Fix compile time warnings about
	misleading indentation.
 2021-02-19 10:14:09 +00:00
Nelson Chu
5a9f5403c7 RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. 
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,

[VALID/EXTRACT/ENCODE macros]
BTYPE_IMM:            Renamed from SBTYPE_IMM.
JTYPE_IMM:            Renamed from UJTYPE_IMM.
CITYPE_IMM:           Renamed from RVC_IMM.
CITYPE_LUI_IMM:       Renamed from RVC_LUI_IMM.
CITYPE_ADDI16SP_IMM:  Renamed from RVC_ADDI16SP_IMM.
CITYPE_LWSP_IMM:      Renamed from RVC_LWSP_IMM.
CITYPE_LDSP_IMM:      Renamed from RVC_LDSP_IMM.
CIWTYPE_IMM:          Renamed from RVC_UIMM8.
CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
CSSTYPE_IMM:          Added for .insn without special encoding.
CSSTYPE_SWSP_IMM:     Renamed from RVC_SWSP_IMM.
CSSTYPE_SDSP_IMM:     Renamed from RVC_SDSP_IMM.
CLTYPE_IMM:           Added for .insn without special encoding.
CLTYPE_LW_IMM:        Renamed from RVC_LW_IMM.
CLTYPE_LD_IMM:        Renamed from RVC_LD_IMM.
RVC_SIMM3:            Unused and removed.
CBTYPE_IMM:           Renamed from RVC_B_IMM.
CJTYPE_IMM:           Renamed from RVC_J_IMM.

* Added new operands and removed the unused ones,

C5: Unsigned CL(CS) immediate, added for .insn directive.
C6: Unsigned CSS immediate, added for .insn directive.
Ci: Unused and removed.
C<: Unused and removed.

bfd/
    PR 27158
    * elfnn-riscv.c (perform_relocation): Updated encoding macros.
    (_bfd_riscv_relax_call): Likewise.
    (_bfd_riscv_relax_lui): Likewise.
    * elfxx-riscv.c (howto_table): Likewise.
gas/
    PR 27158
    * config/tc-riscv.c (riscv_ip): Updated encoding macros.
    (md_apply_fix): Likewise.
    (md_convert_frag_branch): Likewise.
    (validate_riscv_insn): Likewise.  Also arranged operands, including
    added C5 and C6 operands, and removed unused Ci and C< operands.
    * doc/c-riscv.texi: Updated and added CSS/CL/CS types.
    * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
    * testsuite/gas/riscv/insn.s: Likewise.
gdb/
    PR 27158
    * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
    (decode_j_type_insn): Likewise.
    (decode_cj_type_insn): Likewise.
    (decode_b_type_insn): Likewise.
    (decode): Likewise.
include/
    PR 27158
    * opcode/riscv.h: Updated encoding macros.
opcodes/
    PR 27158
    * riscv-dis.c (print_insn_args): Updated encoding macros.
    * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
    (match_c_addi16sp): Updated encoding macros.
    (match_c_lui): Likewise.
    (match_c_lui_with_hint): Likewise.
    (match_c_addi4spn): Likewise.
    (match_c_slli): Likewise.
    (match_slli_as_c_slli): Likewise.
    (match_c_slli64): Likewise.
    (match_srxi_as_c_srxi): Likewise.
    (riscv_insn_types): Added .insn css/cl/cs.
sim/
    PR 27158
    * riscv/sim-main.c (execute_i): Updated encoding macros.
 2021-02-19 11:44:49 +08:00
Nelson Chu
3d73d29e4e RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling. 
Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the
spec versions stuff to bfd/cpu-riscv.h.  Also move the csr stuff and
ext_version_table to gas/config/tc-riscv.c for internal use.  To avoid
too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS
macros.  Therefore, assembler/dis-assembler/linker/gdb can get all spec
versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff
are defined there uniformly.

bfd/
    * Makefile.am: Added cpu-riscv.h.
    * Makefile.in: Regenerated.
    * po/SRC-POTFILES.in: Regenerated.
    * cpu-riscv.h: Added to support spec versions controlling.
    Also added extern arrays and functions for cpu-riscv.c.
    (enum riscv_spec_class): Define all spec classes here uniformly.
    (struct riscv_spec): Added for all specs.
    (RISCV_GET_SPEC_CLASS): Added to reduce repeated code.
    (RISCV_GET_SPEC_NAME): Likewise.
    (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class.
    (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class.
    (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name.
    * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec.
    (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS.
    (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME.
    (riscv_priv_specs): Moved below.
    (riscv_get_priv_spec_class_from_numbers): Likewise, updated.
    (riscv_isa_specs): Moved from include/opcode/riscv.h.
    * elfnn-riscv.c: Included cpu-riscv.h.
    (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec.
    * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h.
    (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h.
    * elfxx-riscv.h: Removed extern functions to cpu-riscv.h.
gas/
    * config/tc-riscv.c: Included cpu-riscv.h.
    (enum riscv_csr_clas): Moved from include/opcode/riscv.h.
    (struct riscv_csr_extra): Likewise.
    (struct riscv_ext_version): Likewise.
    (ext_version_table): Moved from opcodes/riscv-opc.c.
    (default_isa_spec): Updated type to riscv_spec_class.
    (default_priv_spec): Likewise.
    (riscv_set_default_isa_spec): Updated.
    (init_ext_version_hash): Likewise.
    (riscv_init_csr_hash): Likewise, also fixed indent.
include/
    * opcode/riscv.h: Moved stuff and make the file tidy.
opcodes/
    * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
    (default_priv_spec): Updated type to riscv_spec_class.
    (parse_riscv_dis_option): Updated.
    * riscv-opc.c: Moved stuff and make the file tidy.
 2021-02-18 15:09:16 +08:00
Nelson Chu
24075dcc85 RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions. 
bfd/
    * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb*.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Removed
    INSN_CLASS_ZB*.
    * testsuite/gas/riscv/bitmanip-insns-32.d: Removed.
    * testsuite/gas/riscv/bitmanip-insns-64.d: Removed.
    * testsuite/gas/riscv/bitmanip-insns.s: Removed.
include/
    * opcode/riscv-opc.h: Removed macros for zb* extensions.
    * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB*.
opcodes/
    * riscv-opc.c (MASK_RVB_IMM): Removed.
    (riscv_opcodes): Removed zb* instructions.
    (riscv_ext_version_table): Removed versions for zb*.
 2021-02-04 16:52:13 +08:00
Nelson Chu
1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned the code. 
bfd/
    * elfnn-riscv.c: Indent, labels and GNU coding standards tidy,
    also aligned the code.
gas/
    * config/tc-riscv.c: Indent and GNU coding standards tidy,
    also aligned the code.
    * config/tc-riscv.h: Likewise.
include/
    * opcode/riscv.h: Indent and GNU coding standards tidy,
    also aligned the code.
opcodes/
    * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
    (riscv_fpr_names_abi): Likewise.
    (riscv_opcodes): Likewise.
    (riscv_insn_types): Likewise.
 2021-01-15 17:41:18 +08:00
Nelson Chu
b800637e76 RISC-V: Error and warning messages tidy. 
Error and warning messages usually starting with lower case letter,
and without the period at the end.  Besides, add the prefixed "internel:"
at the beginning of the messages when they are caused internally.
Also fix indents and typos.

bfd/
    * elfnn-riscv.c (riscv_merge_attributes): Fix typos of messages.
gas/
    * config/tc-riscv.c: Error and warning messages tidy.
    * testsuite/gas/riscv/priv-reg-fail-fext.l: Updated.
    * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
    * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
    * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
    * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
    * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
    * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
ld/
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Likewise.
opcodes/
    * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 2021-01-15 17:33:59 +08:00
Nelson Chu
dcd709e056 RISC-V: Comments tidy and improvement. 
The GNU coding standards said the comments should be complete sentences
and end with a period and two spaces.  But sometimes it should be more
cleaner when the comments only include a word or codes.  Therefore, I made
the following changes after referring to other target/generic codes,

* Try to write sentences in comments, must end with a period and two spaces.
* End with two spaces without a period for codes/instructions only.
* End with one space without a period for a single word/variable only.

Besids, also rewrite/remove some comments which are obsolete or too long,
and fix indents for comments.

bfd/
    * elfnn-riscv.c: Comments tidy and improvement.
    * elfxx-riscv.c: Likewise.
    * elfxx-riscv.h: Likewise.
gas/
    * config/tc-riscv.c: Comments tidy and improvement.  Also update
    comment "fallthru" to "Fall through" that end with a period and
    two spaces.
include/
    * elf/riscv.h: Comments tidy and improvement.
    * opcode/riscv-opc.h: Likewise.
    * opcode/riscv.h: Likewise.
opcodes/
    * riscv-dis.c: Comments tidy and improvement.
    * riscv-opc.c: Likewise.
 2021-01-15 17:28:07 +08:00
Philipp Tomsich
aa881ecde4 RISC-V: Add pause hint instruction. 
Add support for the pause hint instruction, as specified in the
Zihintpause extension.  The pause instruction is encoded as a
special form of a memory fence (which is available as part of the
base instruction set).  The chosen encoding does not mandate any
particular memory ordering and therefore is a true hint.

bfd/
    * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Added
    INSN_CLASS_ZIHINTPAUSE.
    * testsuite/gas/riscv/pause.d: New testcase.  Adding coverage for
    the pause hint instruction.
    * testsuite/gas/riscv/pause.s: Likewise.
include/
    * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN
    for pause hint instruction.
    * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE.
opcodes/
    * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 2021-01-07 16:45:43 +08:00
Claire Xenia Wolf
2652cfad8d RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). 
In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we
should update them to INSN_ALIAS when we have supported their true instruction
in the future.  Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW]
to encode them.  Besides, the orc.b has the same encoding both in rv32 and
rv64, so we just keep one of them in the opcode table.

This patch is implemented according to the following link,
https://github.com/riscv/riscv-bitmanip/pull/101

2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
            Jim Wilson  <jimw@sifive.com>
            Andrew Waterman  <andrew@sifive.com>
            Maxim Blinov  <maxim.blinov@embecosm.com>
            Kito Cheng  <kito.cheng@sifive.com>
            Nelson Chu  <nelson.chu@sifive.com>

bfd/
    * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*.
    (riscv_get_default_ext_version): Do not check the default_isa_spec when
    the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT.
    * testsuite/gas/riscv/bitmanip-insns-32.d: New testcase.
    * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
    * testsuite/gas/riscv/bitmanip-insns.s: Likewise.
include/
    * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC.
    * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB*.
    (enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the
    frozen extensions.
opcodes/
    * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
    (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 2021-01-07 11:44:54 +08:00
Marcus Comstedt
fbc09e7af7 RISC-V: Implement support for big endian targets. 
RISC-V instruction/code is always little endian, but data might be
big-endian.  Therefore, we can not use the original bfd_get/bfd_put
to get/put the code for big endian targets.  Add new riscv_get_insn
and riscv_put_insn to always get/put code as little endian can resolve
the problem.  Just remember to update them once we have supported
the 48-bit/128-bit instructions in the future patches.

bfd/
    * config.bfd: Added targets riscv64be*-*-*, riscv32be*-*-* and
    riscvbe*-*-*.  Also added riscv_elf[32|64]_be_vec.
    * configure.ac: Handle riscv_elf[32|64]_be_vec.
    * configure: Regenerate.
    * elfnn-riscv.c: Include <limits.h> and define CHAR_BIT for
    riscv_is_insn_reloc.
    (riscv_get_insn): RISC-V instructions are always little endian, but
    bfd_get may be used for big-endian, so add new riscv_get_insn to handle
    the insturctions.
    (riscv_put_insn): Likewsie.
    (riscv_is_insn_reloc): Check if we are relocaing an instruction.
    (perform_relocation): Call riscv_is_insn_reloc to decide if we should
    use riscv_[get|put]_insn or bfd_[get|put].
    (riscv_zero_pcrel_hi_reloc): Use riscv_[get|put]_insn, bfd_[get|put]l32
    or bfd_[get|put]l16 for code.
    (riscv_elf_relocate_section): Likewise.
    (riscv_elf_finish_dynamic_symbol): Likewise.
    (riscv_elf_finish_dynamic_sections): Likewise.
    (_bfd_riscv_relax_call): Likewise.
    (_bfd_riscv_relax_lui): Likewise.
    (_bfd_riscv_relax_align): Likewise.
    (_bfd_riscv_relax_pc): Likewise.
    (riscv_elf_object_p): Handled for big endian.
    (TARGET_BIG_SYM, TARGET_BIG_NAME): Defined.
    * targets.c: Add riscv_elf[32|64]_be_vec.
    (_bfd_target_vector): Likewise.

gas/
    * config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv and
    elf32-bigriscv.
    (install_insn): Always write instructions as little endian.
    (riscv_make_nops): Likewise.
    (md_convert_frag_branch): Likewise.
    (md_number_to_chars): Write data in target endianness.
    (options, md_longopts): Add -mbig-endian and -mlittle-endian options.
    (md_parse_option): Handle the endian options.
    * config/tc-riscv.h: Only define TARGET_BYTES_BIG_ENDIAN if not
    already defined.
    * configure.tgt: Added riscv64be*, riscv32be*, riscvbe*.

ld/
    * configure.tgt: Added riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,
    riscv32be*-*-linux*, and riscv64be*-*-linux*.
    * Makefile.am: Added eelf32briscv.c, eelf32briscv_ilp32f.c and
    eelf32briscv_ilp32.c.
    * Makefile.in: Regenerate.
    * emulparams/elf32briscv.sh: Added.
    * emulparams/elf32briscv_ilp32.sh: Likewise.
    * emulparams/elf32briscv_ilp32f.sh: Likewise.
    * emulparams/elf64briscv.sh: Likewise.
    * emulparams/elf64briscv_lp64.sh: Likewise.
    * emulparams/elf64briscv_lp64f.sh: Likewise.
 2021-01-06 17:57:52 +08:00
Alan Modra
f9a6a8f09d PR27116, Spelling errors found by Debian style checker 
PR 27116
bfd/
	* xcofflink.c: Correct spelling in comments.
binutils/
	* coffgrok.c (do_type): Correct spelling of auxiliary in errors.
	* doc/binutils.texi: Correct grammar.
	* readelf.c (process_version_sections): Correct spelling of auxiliary
	in warning.
	* testsuite/binutils-all/vax/objdump.exp: Comment grammar fix.
config/
	* override.m4: Correct comment grammar.
gas/
	* config/tc-i386.c: Correct comment spelling.
	* config/tc-riscv.c: Likewise.
	* config/tc-s390.c: Correct comment grammar.
	* doc/c-i386.texi: Correct spelling.
	* doc/c-s390.texi: Correct grammar.
gold/
	* tilegx.cc: Correct comment spelling.
gprof/
	* README: Correct grammar.
	* gprof.texi: Likewise.
include/
	* coff/internal.h: Correct comment spelling.
	* coff/sym.h: Likewise.
	* opcode/aarch64.h: Likewise.
ld/
	* configure.tgt: Correct comment grammar.
	* emultempl/m68hc1xelf.em: Likewise.
	* ld.texi: Correct grammar.
 2021-01-01 14:36:35 +10:30
Alan Modra
250d07de5c Update year range in copyright notice of binutils files 2021-01-01 10:31:05 +10:30
Nelson Chu
c2137f55ad RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. 
https://github.com/riscv/riscv-asm-manual/pull/61

We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h
and zext.w.  In a certain sense, zext.b is not a pseudo - It is an
alias of andi.  Similarly, sext.b and sext.h are aliases of other
rvb instructions, when we enable b extension; But they are pseudos
when we just enable rvi.  However, this patch does not consider the
rvb cases.  Besides, zext.w is only valid in rv64.

gas/
    * config/tc-riscv.c (riscv_ext): New function.  Use md_assemblef
    to expand the zext and sext pseudos, to give them a chance to be
    expanded into c-ext instructions.
    (macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH.
    * testsuite/gas/riscv/ext.s: New testcase.
    * testsuite/gas/riscv/ext-32.d: Likewise.
    * testsuite/gas/riscv/ext-64.d: Likewise.
include/
    * opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added.
opcodes/
    * riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw].
 2020-12-10 10:50:44 +08:00
Nelson Chu
729a53530e RISC-V: Control fence.i and csr instructions by zifencei and zicsr. 
bfd/
    * elfxx-riscv.c (riscv_ext_dont_care_version): New function.  Return
    TRUE if we don't care the versions of the extensions.  These extensions
    are added to the subset list for special purposes, with the explicit
    versions or the RISCV_UNKNOWN_VERSION versions.
    (riscv_parse_add_subset): If we do care the versions of the extension,
    and the versions are unknown, then report errors for the non-implicit
    extensions, and return directly for the implicit one.
    (riscv_arch_str1): Do not output i extension after e, and the extensions
    which versions are unknown.
gas/
    * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR
    and INSN_CLASS_ZIFENCEI.
    * testsuite/gas/riscv/march-imply-i.s: New testcase.
    * testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase.  The version
    of i is less than 2.1, and zi* are supported in the chosen spec, so
    enable the fence.i and csr instructions, also output the implicit zi* to
    the arch string.
    * testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are
    not supported in the spec 2.2.  Enable the related instructions since
    i's version is less than 2.1, but do not output them.
    * testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase.  The version
    of i is 2.1, so don't add it's implicit zi*, and disable the related
    instructions.
    * testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise.
    * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi*
    explicitly, so enable the related instructions.
    * testsuite/gas/riscv/march-imply-i2p0.d: Removed.
    * testsuite/gas/riscv/march-imply-i2p1.d: Removed.
include/
    * opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI.
opcodes/
    * riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by
    zifencei and zicsr.
 2020-12-10 10:37:43 +08:00
Nelson Chu
dfe9249667 RISC-V: Support to add implicit extensions. 
We have to parse and add all arch string extensions at first, and then
start to add their implicit extensions.  That means we can always add
arch string extensions at the end of the subset list, but we need to
search the right place to add their implicit extensions.  For now we
follow the following rules to add the implicit extensions,

* Add zicsr and zifencei only when the i's version less than 2.1.
* Add d, f and zicsr when q is found.
* Add f and zicsr when d is found.
* Add zicsr when f is found.

Besides, we do not add the implicit extensions if they are already added
in the subset list, or we cannot find their default versions according to
the chosen ISA spec.

	bfd/
	* elfnn-riscv.c (riscv_merge_std_ext): Updated since
	riscv_lookup_subset is changed.
	* elfxx-riscv.c (riscv_ext_order): New Array used to compare the
	extensions' order quickly.
	(riscv_init_ext_order): New function.  Init the riscv_ext_order
	according to the riscv_supported_std_ext and parse_config[i].class
	automatically.
	(riscv_compare_subsets): New function.  Similar to the strcmp, but
	compare the subsets with the specific order.
	(riscv_lookup_subset): Return TRUE and set `current` to the subset
	if it is found.  Otherwise, return FALSE and set `current` to the
	place where we should insert the subset.
	(riscv_add_implicit_subset): New function.  Search the list first,
	and then find the right place to add the implicit_subset.
	(riscv_parse_add_subset): Since We have to add all arch string
	extensions first, and then start to add their implicit extensions.
	We can add arch string extensions in order by the original
	riscv_add_subset, and then add the implicit subsets by the
	riscv_add_implicit_subset.  Besides, do not add the implicit
	extensions if we failed to find their default versions.
	(riscv_parse_std_ext): Updated.
	(riscv_parse_add_implicit_subsets): New function.  Add all implicit
	extensions according to the arch string extensions.
	(riscv_parse_subset): Call riscv_init_ext_order and
	riscv_parse_add_implicit_subsets, before and after parsing the
	arch string.  Remove parts of the ISA conflict checking since
	the implicit extensions are added.
	* elfxx-riscv.h (riscv_lookup_subset): Updated.

	gas/
	* config/tc-riscv.c (riscv_subset_supports): Updated.
	* testsuite/gas/riscv/march-imply-i2p0.d: New testcase.  Need to
	add the implicit zicsr and zifencei when i's version less than 2.1.
	* testsuite/gas/riscv/march-imply-i2p1.d: New testcase.
	* testsuite/gas/riscv/march-imply-d.d: Likewise.
	* testsuite/gas/riscv/march-imply-f.d: Likewise.
	* testsuite/gas/riscv/march-imply-q.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iq.l: Updated.
	* testsuite/gas/riscv/march-fail-rv32id.d: Removed.
	* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
 2020-12-01 15:18:48 +08:00
Nelson Chu
7ef19aa616 RISC-V: Improve the version parsing for arch string. 
Keep the riscv_add_subset to do the same thing, and use a new
function, riscv_parse_add_subset, to cover most of the things
when parsing, including find the default versions for extensions,
and check whether the versions are valid.  The version 0p0 should
be an invalid version, that is the mistake I made before.  This
patch clarify the version rules as follows,

* We accept any version of extensions set by users, except 0p0.
* The non-standard x extensions must be set with versions in arch string.
* If user don't set the versions, or set 0p0 for the extensions, then try
  to find the supported versions according to the chosen ISA spec.
  Otherwise, report errors rather than output 0p0 for them.

Besides, we use as_bad rather than as_fatal to report more errors
for assembler.

	bfd/
	* elfxx-riscv.c (riscv_lookup_subset): Moved to front.
	(riscv_add_subset): Likewise.
	(riscv_release_subset_list): Likewise.
	(riscv_parse_add_subset): New function.  Find and check the
	versions before adding them by riscv_add_subset.
	(riscv_parsing_subset_version): Remove use_default_version
	and change the version type from unsigned to int.  Set the
	versions to RISCV_UNKNOWN_VERSION if we can not find them
	in the arch string.
	(riscv_parse_std_ext): Updated.
	(riscv_parse_prefixed_ext): Updated.  Since we use as_bad
	rather than as_fatal to report more errors, return NULL
	string if the parsed end_of_version is NULL, too.
	(riscv_parse_subset): Use a new boolean, no_conflict, to
	report more errors when we have more than one ISA conflicts.

	* elfxx-riscv.h (RISCV_DONT_CARE_VERSION): Changed to
	RISCV_UNKNOWN_VERSION.
	(riscv_lookup_subset_version): Removed.
	(riscv_parse_subset_t): Updated.

	gas/
	* config/tc-riscv.c (riscv_get_default_ext_version):
	Change the version type from unsigned to int.
	(riscv_set_arch): Use as_bad rather than as_fatal to
	report more errors.

	* testsuite/gas/riscv/attribute-02.d: Updated since x must be
	set with versions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/march-ok-two-nse.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: zicsr wasn't supported
	in the spec 2.2, so choose the newer spec.
	* testsuite/gas/riscv/march-fail-base-01.l: Updated since as_bad.
	* testsuite/gas/riscv/march-fail-base-02.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
	* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
	* testsuite/gas/riscv/march-fail-porder.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32ef.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32id.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv64iq.l: Likewise.
	* testsuite/gas/riscv/march-fail-single-char.l: Likewise.
	* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
	* testsuite/gas/riscv/march-fail-unknown.l: Likewise.
	* testsuite/gas/riscv/march-fail-uppercase.l: Likewise.
	* testsuite/gas/riscv/march-fail-version.l: Likewise.
	* testsuite/gas/riscv/march-fail-isa-spec.d: Likewise.
	* testsuite/gas/riscv/march-fail-isa-spec.l: Likewise.

	include/
	* opcode/riscv.h (riscv_ext_version):
	Change the version type from unsigned to int.
 2020-12-01 15:16:25 +08:00
Nelson Chu
6e1605e430 RISC-V: Update ABI to the elf_flags after parsing elf attributes. 
Originally, if the -mabi option isn't set, then assembler will set the
abi according to the architecture string in the riscv_after_parse_args.
But we should also check and reset the abi later since the architecture
string may be reset by the elf attributes.  Therefore, set the abi to
the elf_flags in the riscv_after_parse_args seems too early.  Besides,
we have to set the abi_xlen before assembling any instruction, so it
should be safe to call riscv_set_abi_by_arch at the place that we set
start_assemble to TRUE.  However, one minor case is that we won't call
the md_assemble when we are assembling an file without any instruction.
It seems that we still need to set the abi in riscv_elf_final_processing,
to make sure that abi can be updated according to the elf arch attributes.

For the rv32i and most elf toolchains, this patch can fix the mis-matched
ABI errors for Run pr26391-5 and Run pr26391-6 testcases.  Besides, it
also correct the elf header flags of the output objects.  Consider the
new testcases, mabi-fail-02 and mabi-noabi-attr-[01|02|03], they are
failed before applying this patch.

But I still get the mis-matched ABI errors for the following toolchains
when runnung the riscv-gnu-toolchain regressions,

newlib-rv32imafc-ilp32f-[medlow|medany]
linux-rv32imac-ilp32-[medlow|medany]
linux-rv32imafdc-ilp32-[medlow|medany}
linux-rv64imac-lp64-[medlow|medany]
linux-rv64imafdc-lp64-[medlow|medany}

For the newlib-rv32imafc-ilp32f, although we try to choose the abi
according to the elf attributes, we will use FLOAT_ABI_SOFT rather
than the FLOAT_ABI_SINGLE for the assmebly file wihtout setting the
-mabi, but compiler will set the abi to FLOAT_ABI_SINGLE for the
C files.

As for the linux toolchains, we also get fails for Run pr26391-5 and
Run pr26391-6 testcases.  Since the linux toolchain won't generate elf
attributes to correct the ISA, and the --with-arch configure option
isn't set, assembler will try to set the default arch to rv[32|64]g,
which means the FLOAT_ABI_DOUBLE will be choosed, and may be conflict
with the abi set by the toolchain.

Therefore, I would suggest that it's is more safe to set the --with-arch
when building binutils, but it may break some testcases.  For example,
ld-scripts/fill and ld-scripts/empty-address-2 may be broken when c-ext
is set.  We might insert R_RISCV_ALIGN to make sure the 4-byte alignment,
but the dump result will be a bit different from what the testcase expected.

However, this patch only fix the problem - the abi, elf_flags and the
instruction, which is generated according to the abi_xlen, are all fixed
once the elf attributes are set for most elf toolchains. Other mis-matched
ABI problems should be fixed when we always build the binutils with the
--with-arch= configure option.

	gas/
	* config/tc-riscv.c (explicit_mabi): New boolean to indicate if
	the -mabi= option is explictly set.
	(md_parse_option): Set explicit_mabi to TRUE if -mabi is set.
	(riscv_set_abi_by_arch): New function.  If the -mabi option isn't
	set, then we set the abi according to the architecture string.
	Otherwise, check if there are conflicts between architecture
	and abi setting.
	(riscv_after_parse_args): Move the abi setting to md_assemble nad
	riscv_elf_final_processing.
	(md_assemble): Call the riscv_set_abi_by_arch when we set the
	start_assemble to TRUE.
	(riscv_elf_final_processing): Likewise, in case the file without
	any instruction.

	* testsuite/gas/riscv/mabi-attr-01.s: New testcase.
	* testsuite/gas/riscv/mabi-attr-02.s: Likewise.
	* testsuite/gas/riscv/mabi-attr-03.s: Likewise.
	* testsuite/gas/riscv/mabi-fail-01.d: Likewise.
	* testsuite/gas/riscv/mabi-fail-01.l: Likewise.
	* testsuite/gas/riscv/mabi-fail-02.d: Likewise.
	* testsuite/gas/riscv/mabi-fail-02.l: Likewise.
	* testsuite/gas/riscv/mabi-noabi-attr-01a.d: Likewise.
	* testsuite/gas/riscv/mabi-noabi-attr-01b.d: Likewise.
	* testsuite/gas/riscv/mabi-noabi-attr-02a.d: Likewise.
	* testsuite/gas/riscv/mabi-noabi-attr-02b.d: Likewise.
	* testsuite/gas/riscv/mabi-noabi-attr-03a.d: Likewise.
	* testsuite/gas/riscv/mabi-noabi-attr-03b.d: Likewise.
	* testsuite/gas/riscv/mabi-noabi-march-01.d: Likewise.
	* testsuite/gas/riscv/mabi-noabi-march-02.d: Likewise.
	* testsuite/gas/riscv/mabi-noabi-march-03.d: Likewise.
 2020-11-09 09:48:56 +08:00
Jim Wilson
743f5cfc00 RISC-V: Error for relaxable branch in absolute section. 
Emit an error instead of crashing in frag_new, handling this same as the
i386 port.

gas/
	PR 26400
	* config/tc-riscv.c (append_insn): If in absolute section, emit
	error before add_relaxed_insn call.
	* testsuite/gas/riscv/absolute-sec.d: New.
	* testsuite/gas/riscv/absolute-sec.l: New.
	* testsuite/gas/riscv/absolute-sec.s: New.
 2020-09-24 15:16:54 -07:00
Alan Modra
b1b11e922b PR26569, R_RISCV_RVC_JUMP results in buffer overflow 
This patch corrects "size" and "bitsize" in R_RISCV_RVC_* reloc howtos
so that elfnn-riscv.c:perform_relocation doesn't access past the end
of a section.  I've also corrected "size" in the R_RISCV_CALL* reloc
howtos since these relocs apply to two consecutive instructions.  That
caused fallout in the assembler with complaints about "fixup not
contained within frag" due to tc-riscv.c:append_insn finishing off a
frag after the auipc insn making up a "call" macro.  Which is a little
rude since the CALL reloc also relocates the following jalr.  Fixed by
changing the frag handling a little.

I've also changed R_RISCV_ALIGN and R_RISCV_TPREL_ADD marker reloc
howtos to look like R_RISCV_NONE, and corrected dst_mask for numerous
relocs, not that it matters very much.

bfd/
	PR 26569
	* elfxx-riscv.c (howto_table): Correct size and bitsize of
	R_RISCV_RVC_BRANCH, R_RISCV_RVC_JUMP, and R_RISCV_RVC_LUI.
	Correct size for R_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPREL32,
	R_RISCV_CALL, and R_RISCV_CALL_PLT.  Make R_RISCV_TPREL_ADD and
	R_RISCV_ALIGN like R_RISCV_NONE.  Correct dst_mask many relocs.
gas/
	* config/tc-riscv.c (append_insn): Don't tie off frags at CALL
	relocs.
	(riscv_call): Tie them off after the jalr.
	(md_apply_fix): Zero fx_size of RELAX fixup.
 2020-09-21 09:41:05 +09:30
Alan Modra
169ec51259 PR26493 UBSAN: tc-riscv.c left shift negative and not representable 
PR 26493
	* config/tc-riscv.c (riscv_ip): Cast X_add_number passed to
	VALID_* macros to unsigned.
 2020-08-31 20:28:11 +09:30
Alan Modra
fe0e921f00 PR26513, 629310abec breaks assembling PowerPC Linux kernels 
Inserting with replacement is wrong for some gas hash table uses.
This patch implements an htab_insert that conditionally replaces, and
similarly for str_hash_insert.  str_hash_insert with replace=0 is
roughly equivalent to the older hash_insert, and str_hash_insert with
replace=1 to the older hash_jam, but return values are different.  I
found it useful to know whether the slot was occupied prior to
inserting/replacing.  I've also reinstated the fatal errors on messing
up opcode tables with duplicates.

	PR 26513
	* hash.h (htab_insert): Update prototype and comment.
	(struct string_tuple): Make "value" a const void*.
	(string_tuple_alloc): Likewise.
	(str_hash_find, str_hash_find_n): Cast returned value.
	(str_hash_insert): Add "replace" parameter, and return slot pointer.
	Free alloc'd element when not inserted.
	* hash.c (htab_insert): Likewise.  Return slot when element exists,
	otherwise return NULL.
	* read.c (pop_insert): Insert into hash table without first searching.
	* config/tc-avr.c (md_begin): Likewise.
	* config/tc-msp430.c (md_begin): Likewise.
	* config/tc-nds32.c (nds32_init_nds32_pseudo_opcodes): Likewise.
	* config/tc-v850.c (md_begin): Likewise.
	* macro.c (do_formals, define_macro, macro_expand_body): Likewise.
	(delete_macro): Delete from hash table.
	* config/tc-tic54x.c (subsym_create_or_replace): Correct logic.

	* symbols.c (local_symbol_make, symbol_table_insert): Allow
	replacement of hash table entries.
	* config/obj-coff-seh.c (seh_hash_insert): Likewise.
	* config/obj-coff.c (tag_insert): Likewise.
	* config/tc-iq2000.c (iq2000_add_macro): Likewise.
	* config/tc-m68k.c (md_begin): Likewise for aliases.
	* config/tc-tic4x.c (tic4x_asg): Likewise.
	* config/tc-tic6x.c (md_begin): Likewise.

	* dw2gencfi.c (dwcfi_hash_find_or_make): Disallow replacement of
	hash table entries.
	* ecoff.c (add_string, get_tag): Likewise.
	* macro.c (expand_irp): Likewise.
	* config/obj-elf.c (build_additional_section_info): Likewise.
	* config/tc-aarch64.c (insert_reg_alias): Likewise.
	(checked_hash_insert): Likewise.
	* config/tc-alpha.c (get_alpha_reloc_tag, md_begin): Likewise.
	* config/tc-arc.c (arc_insert_opcode, declare_register): Likewise.
	(declare_addrtype, md_begin, arc_extcorereg): Likewise.
	* config/tc-arm.c (insert_reg_alias): Likewise.
	(arm_tc_equal_in_insn, md_begin): Likewise.
	* config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise.
	* config/tc-cris.c (md_begin): Likewise.
	* config/tc-crx.c (md_begin): Likewise.
	* config/tc-csky.c (md_begin): Likewise.
	* config/tc-d10v.c (md_begin): Likewise.
	* config/tc-dlx.c (md_begin): Likewise.
	* config/tc-ft32.c (md_begin): Likewise.
	* config/tc-h8300.c (md_begin): Likewise.
	* config/tc-hppa.c (md_begin): Likewise.
	* config/tc-i386.c (md_begin): Likewise.
	* config/tc-ia64.c (dot_rot, dot_entry, declare_register): Likewise.
	(md_begin, dot_alias): Likewise.
	* config/tc-m68hc11.c (md_begin): Likewise.
	* config/tc-m68k.c (md_begin): Likewise.
	* config/tc-mcore.c (md_begin): Likewise.
	* config/tc-microblaze.c (md_begin): Likewise.
	* config/tc-mips.c (md_begin): Likewise.
	* config/tc-mmix.c (md_begin): Likewise.
	* config/tc-mn10200.c (md_begin): Likewise.
	* config/tc-mn10300.c (md_begin): Likewise.
	* config/tc-moxie.c (md_begin): Likewise.
	* config/tc-nds32.c (nds32_relax_hint, md_begin): Likewise.
	* config/tc-nios2.c (md_begin): Likewise.
	* config/tc-ns32k.c (md_begin): Likewise.
	* config/tc-pdp11.c (md_begin): Likewise.
	* config/tc-pj.c (fake_opcode, md_begin): Likewise.
	* config/tc-ppc.c (ppc_setup_opcodes): Likewise.
	* config/tc-pru.c (md_begin): Likewise.
	* config/tc-riscv.c (init_ext_version_hash): Likewise.
	(init_opcode_names_hash, hash_reg_name, init_opcode_hash): Likewise.
	(riscv_init_csr_hash): Likewise.
	* config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise.
	* config/tc-score.c (s3_insert_reg): Likewise.
	(s3_build_score_ops_hsh, s3_build_dependency_insn_hsh): Likewise.
	* config/tc-score7.c (s7_build_score_ops_hsh): Likewise.
	(s7_build_dependency_insn_hsh, s7_insert_reg): Likewise.
	* config/tc-sh.c (md_begin): Likewise.
	* config/tc-sparc.c (md_begin): Likewise.
	* config/tc-spu.c (md_begin): Likewise.
	* config/tc-tic30.c (md_begin): Likewise.
	* config/tc-tic4x.c (tic4x_inst_insert): Likewise.
	* config/tc-tic54x.c (stag_add_field_symbols, md_begin): Likewise.
	(tic54x_endstruct, tic54x_var, tic54x_macro_info): Likewise.
	(subsym_substitute): Likewise.
	* config/tc-tilegx.c (md_begin): Likewise.
	* config/tc-tilepro.c (md_begin): Likewise.
	* config/tc-vax.c (vip_begin): Likewise.
	* config/tc-wasm32.c (md_begin): Likewise.
	* config/tc-xgate.c (md_begin): Likewise.
	* config/tc-z8k.c (md_begin): Likewise.
	* testsuite/gas/ppc/dcbt.d,
	* testsuite/gas/ppc/dcbt.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.

	* ecoff.c (add_string): Report fatal error on duplicates.
	* config/tc-alpha.c (md_begin): Likewise.
	* config/tc-arc.c (arc_insert_opcode, declare_register): Likewise.
	(declare_addrtype, md_begin, arc_extcorereg): Likewise.
	* config/tc-cr16.c (initialise_reg_hash_table, md_begin): Likewise.
	* config/tc-cris.c (md_begin): Likewise.
	* config/tc-crx.c (md_begin): Likewise.
	* config/tc-dlx.c (md_begin): Likewise.
	* config/tc-hppa.c (md_begin): Likewise.
	* config/tc-i386.c (md_begin): Likewise.
	* config/tc-ia64.c (dot_rot, dot_entry, declare_register): Likewise.
	(md_begin): Likewise.
	* config/tc-m68k.c (md_begin): Likewise.
	* config/tc-mips.c (md_begin): Likewise.
	* config/tc-nios2.c (md_begin): Likewise.
	* config/tc-ns32k.c (md_begin): Likewise.
	* config/tc-ppc.c (ppc_setup_opcodes): Likewise.
	* config/tc-pru.c (md_begin): Likewise.
	* config/tc-riscv.c (init_ext_version_hash): Likewise.
	(init_opcode_names_hash, hash_reg_name, init_opcode_hash): Likewise.
	* config/tc-s390.c (s390_setup_opcodes, md_begin): Likewise.
	* config/tc-sparc.c (md_begin): Likewise.
	* config/tc-tic30.c (md_begin): Likewise.
	* config/tc-tic4x.c (tic4x_inst_insert): Likewise.
	* config/tc-tilegx.c (md_begin): Likewise.
	* config/tc-tilepro.c (md_begin): Likewise.
	* config/tc-vax.c (vip_begin): Likewise.

	* config/tc-alpha.c,
	* config/tc-arm.c,
	* config/tc-avr.c,
	* config/tc-cr16.c,
	* config/tc-csky.c,
	* config/tc-i386.c,
	* config/tc-m68hc11.c,
	* config/tc-m68k.c,
	* config/tc-microblaze.c,
	* config/tc-ns32k.c,
	* config/tc-pj.c,
	* config/tc-ppc.c,
	* config/tc-score.c,
	* config/tc-score7.c,
	* config/tc-tic4x.c,
	* config/tc-tic54x.c,
	* config/tc-tilegx.c,
	* config/tc-tilepro.c,
	* config/tc-xgate.c: Formatting.
 2020-08-23 21:38:05 +09:30
Alan Modra
e01e1cee39 Rearrange symbol_create parameters 
These functions take an offset within frag, frag within section, and
section parameter.  So it makes sense to order the parameters as
section, frag, offset.

	* symbols.h (symbol_new, symbol_create, local_symbol_make),
	(symbol_temp_new): Arrange params as section, frag, offset.
	* symbols.c: Adjust to suit.
	* as.c: Likewise.
	* cgen.c: Likewise.
	* dwarf2dbg.c: Likewise.
	* ecoff.c: Likewise.
	* expr.c: Likewise.
	* itbl-ops.c: Likewise.
	* read.c: Likewise.
	* stabs.c: Likewise.
	* subsegs.c: Likewise.
	* config/obj-coff.c: Likewise.
	* config/obj-elf.c: Likewise.
	* config/obj-macho.c: Likewise.
	* config/tc-aarch64.c: Likewise.
	* config/tc-alpha.c: Likewise.
	* config/tc-arc.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-avr.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-cris.c: Likewise.
	* config/tc-csky.c: Likewise.
	* config/tc-dlx.c: Likewise.
	* config/tc-hppa.c: Likewise.
	* config/tc-i386.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-m32r.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-mips.c: Likewise.
	* config/tc-mmix.c: Likewise.
	* config/tc-mn10200.c: Likewise.
	* config/tc-mn10300.c: Likewise.
	* config/tc-nds32.c: Likewise.
	* config/tc-nios2.c: Likewise.
	* config/tc-ppc.c: Likewise.
	* config/tc-riscv.c: Likewise.
	* config/tc-s390.c: Likewise.
	* config/tc-sh.c: Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-tic54x.c: Likewise.
	* config/tc-xtensa.c: Likewise.
 2020-08-21 18:26:35 +09:30
Martin Liska
629310abec Port gas/config/* to str_htab. 
* config/obj-coff-seh.c (seh_hash_insert): Port to use new
	str_htab type.
	(seh_hash_find): Likewise.
	(seh_hash_find_or_make): Likewise.
	* config/obj-coff.c (tag_init): Likewise.
	(tag_insert): Likewise.
	(tag_find): Likewise.
	* config/obj-elf.c (struct group_list): Likewise.
	(build_additional_section_info): Likewise.
	(free_section_idx): Likewise.
	(elf_adjust_symtab): Likewise.
	(elf_frob_file_after_relocs): Likewise.
	* config/tc-aarch64.c (INSN_SIZE): Likewise.
	(parse_reg): Likewise.
	(insert_reg_alias): Likewise.
	(create_register_alias): Likewise.
	(s_unreq): Likewise.
	(parse_shift): Likewise.
	(parse_pldop): Likewise.
	(parse_barrier): Likewise.
	(parse_barrier_psb): Likewise.
	(parse_bti_operand): Likewise.
	(parse_sys_reg): Likewise.
	(parse_sys_ins_reg): Likewise.
	(lookup_mnemonic): Likewise.
	(opcode_lookup): Likewise.
	(parse_operands): Likewise.
	(checked_hash_insert): Likewise.
	(sysreg_hash_insert): Likewise.
	(fill_instruction_hash_table): Likewise.
	(md_begin): Likewise.
	* config/tc-alpha.c (struct alpha_reloc_tag): Likewise.
	(get_alpha_reloc_tag): Likewise.
	(assemble_tokens_to_insn): Likewise.
	(assemble_tokens): Likewise.
	(md_begin): Likewise.
	* config/tc-arc.c (arc_find_opcode): Likewise.
	(arc_insert_opcode): Likewise.
	(find_opcode_match): Likewise.
	(declare_register): Likewise.
	(declare_addrtype): Likewise.
	(md_begin): Likewise.
	(arc_parse_name): Likewise.
	(tc_arc_regname_to_dw2regnum): Likewise.
	(arc_extcorereg): Likewise.
	* config/tc-arm.c (MVE_BAD_QREG): Likewise.
	(arm_reg_parse_multi): Likewise.
	(parse_reloc): Likewise.
	(insert_reg_alias): Likewise.
	(create_register_alias): Likewise.
	(s_unreq): Likewise.
	(parse_shift): Likewise.
	(parse_psr): Likewise.
	(parse_cond): Likewise.
	(parse_barrier): Likewise.
	(do_vfp_nsyn_opcode): Likewise.
	(opcode_lookup): Likewise.
	(arm_tc_equal_in_insn): Likewise.
	(md_begin): Likewise.
	* config/tc-avr.c (md_begin): Likewise.
	(avr_ldi_expression): Likewise.
	(md_assemble): Likewise.
	(avr_update_gccisr): Likewise.
	(avr_emit_insn): Likewise.
	* config/tc-cr16.c (get_register): Likewise.
	(get_register_pair): Likewise.
	(get_index_register): Likewise.
	(get_index_register_pair): Likewise.
	(get_pregister): Likewise.
	(get_pregisterp): Likewise.
	(initialise_reg_hash_table): Likewise.
	(md_begin): Likewise.
	(cr16_assemble): Likewise.
	(md_assemble): Likewise.
	* config/tc-cris.c (cris_insn_first_word_frag): Likewise.
	(md_begin): Likewise.
	(cris_process_instruction): Likewise.
	* config/tc-crx.c (get_register): Likewise.
	(get_copregister): Likewise.
	(md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-csky.c (md_begin): Likewise.
	(parse_opcode): Likewise.
	(get_operand_value): Likewise.
	(v1_work_jbsr): Likewise.
	(v2_work_rotlc): Likewise.
	(v2_work_bgeni): Likewise.
	(v2_work_not): Likewise.
	* config/tc-d10v.c (sizeof): Likewise.
	(md_begin): Likewise.
	(do_assemble): Likewise.
	(md_apply_fix): Likewise.
	* config/tc-d30v.c (sizeof): Likewise.
	(md_begin): Likewise.
	(do_assemble): Likewise.
	* config/tc-dlx.c (RELOC_DLX_VTENTRY): Likewise.
	(md_begin): Likewise.
	(machine_ip): Likewise.
	* config/tc-ft32.c (md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-h8300.c (md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-hppa.c (pa_ip): Likewise.
	(md_begin): Likewise.
	* config/tc-i386.c (md_begin): Likewise.
	(i386_print_statistics): Likewise.
	(parse_insn): Likewise.
	(process_operands): Likewise.
	(i386_index_check): Likewise.
	(parse_real_register): Likewise.
	* config/tc-ia64.c (dot_rot): Likewise.
	(dot_entry): Likewise.
	(declare_register): Likewise.
	(md_begin): Likewise.
	(ia64_parse_name): Likewise.
	(md_assemble): Likewise.
	(dot_alias): Likewise.
	(do_alias): Likewise.
	(ia64_adjust_symtab): Likewise.
	(do_secalias): Likewise.
	(ia64_frob_file): Likewise.
	* config/tc-m68hc11.c (m68hc11_print_statistics): Likewise.
	(md_begin): Likewise.
	(print_insn_format): Likewise.
	(md_assemble): Likewise.
	* config/tc-m68k.c (tc_gen_reloc): Likewise.
	(m68k_ip): Likewise.
	(md_begin): Likewise.
	* config/tc-mcore.c (md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-microblaze.c (md_begin): Likewise.
	(md_assemble): Likewise.
	(md_apply_fix): Likewise.
	* config/tc-mips.c (nopic_need_relax): Likewise.
	(md_begin): Likewise.
	(macro_build): Likewise.
	(mips16_macro_build): Likewise.
	(mips_lookup_insn): Likewise.
	(mips_ip): Likewise.
	(mips16_ip): Likewise.
	* config/tc-mmix.c (sizeof): Likewise.
	(mmix_md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-mn10200.c (md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-mn10300.c (HAVE_AM30): Likewise.
	(md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-moxie.c (md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-msp430.c (md_begin): Likewise.
	(msp430_operands): Likewise.
	(md_assemble): Likewise.
	* config/tc-nds32.c (PV_DONT_CARE): Likewise.
	(builtin_isreg): Likewise.
	(builtin_regnum): Likewise.
	(nds32_init_nds32_pseudo_opcodes): Likewise.
	(nds32_lookup_pseudo_opcode): Likewise.
	(nds32_relax_hint): Likewise.
	(md_begin): Likewise.
	(nds32_find_reloc_table): Likewise.
	(nds32_elf_append_relax_relocs_traverse): Likewise.
	(nds32_relax_branch_instructions): Likewise.
	(md_convert_frag): Likewise.
	(nds32_elf_analysis_relax_hint): Likewise.
	(tc_nds32_regname_to_dw2regnum): Likewise.
	* config/tc-nios2.c (nios2_opcode_lookup): Likewise.
	(nios2_reg_lookup): Likewise.
	(nios2_ps_lookup): Likewise.
	(md_begin): Likewise.
	* config/tc-ns32k.c (struct hash_control): Likewise.
	(parse): Likewise.
	(md_begin): Likewise.
	* config/tc-pdp11.c (md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-pj.c (fake_opcode): Likewise.
	(alias): Likewise.
	(md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-ppc.c (ppc_setup_opcodes): Likewise.
	(md_assemble): Likewise.
	* config/tc-pru.c (pru_opcode_lookup): Likewise.
	(pru_reg_lookup): Likewise.
	(md_begin): Likewise.
	(md_end): Likewise.
	* config/tc-riscv.c (init_ext_version_hash): Likewise.
	(riscv_get_default_ext_version): Likewise.
	(riscv_set_arch): Likewise.
	(init_opcode_names_hash): Likewise.
	(opcode_name_lookup): Likewise.
	(enum reg_class): Likewise.
	(hash_reg_name): Likewise.
	(riscv_init_csr_hash): Likewise.
	(reg_csr_lookup_internal): Likewise.
	(reg_lookup_internal): Likewise.
	(init_opcode_hash): Likewise.
	(md_begin): Likewise.
	(DECLARE_CSR): Likewise.
	(macro_build): Likewise.
	(riscv_ip): Likewise.
	* config/tc-s390.c (register_name): Likewise.
	(s390_setup_opcodes): Likewise.
	(md_begin): Likewise.
	(md_assemble): Likewise.
	(s390_insn): Likewise.
	* config/tc-score.c (struct s3_reg_map): Likewise.
	(s3_score_reg_parse): Likewise.
	(s3_dependency_type_from_insn): Likewise.
	(s3_parse_16_32_inst): Likewise.
	(s3_parse_48_inst): Likewise.
	(s3_insert_reg): Likewise.
	(s3_build_reg_hsh): Likewise.
	(s3_build_score_ops_hsh): Likewise.
	(s3_build_dependency_insn_hsh): Likewise.
	(s3_begin): Likewise.
	* config/tc-score7.c (struct s7_reg_map): Likewise.
	(s7_score_reg_parse): Likewise.
	(s7_dependency_type_from_insn): Likewise.
	(s7_parse_16_32_inst): Likewise.
	(s7_build_score_ops_hsh): Likewise.
	(s7_build_dependency_insn_hsh): Likewise.
	(s7_insert_reg): Likewise.
	(s7_build_reg_hsh): Likewise.
	(s7_begin): Likewise.
	* config/tc-sh.c (EMPTY): Likewise.
	(md_begin): Likewise.
	(find_cooked_opcode): Likewise.
	* config/tc-sparc.c (md_begin): Likewise.
	(sparc_ip): Likewise.
	* config/tc-spu.c (md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-tic30.c (md_begin): Likewise.
	(tic30_operand): Likewise.
	(tic30_parallel_insn): Likewise.
	(md_assemble): Likewise.
	* config/tc-tic4x.c (TIC4X_ALT_SYNTAX): Likewise.
	(tic4x_asg): Likewise.
	(tic4x_inst_insert): Likewise.
	(tic4x_inst_add): Likewise.
	(md_begin): Likewise.
	(tic4x_operand_parse): Likewise.
	(md_assemble): Likewise.
	* config/tc-tic54x.c (MAX_SUBSYM_HASH): Likewise.
	(stag_add_field_symbols): Likewise.
	(tic54x_endstruct): Likewise.
	(tic54x_tag): Likewise.
	(tic54x_remove_local_label): Likewise.
	(tic54x_clear_local_labels): Likewise.
	(tic54x_var): Likewise.
	(tic54x_macro_start): Likewise.
	(tic54x_macro_info): Likewise.
	(tic54x_macro_end): Likewise.
	(subsym_isreg): Likewise.
	(subsym_structsz): Likewise.
	(md_begin): Likewise.
	(is_mmreg): Likewise.
	(is_type): Likewise.
	(encode_condition): Likewise.
	(encode_cc3): Likewise.
	(encode_cc2): Likewise.
	(encode_operand): Likewise.
	(tic54x_parse_insn): Likewise.
	(tic54x_parse_parallel_insn_firstline): Likewise.
	(subsym_create_or_replace): Likewise.
	(subsym_lookup): Likewise.
	(subsym_substitute): Likewise.
	(tic54x_undefined_symbol): Likewise.
	* config/tc-tic6x.c (md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-tilegx.c (O_hw2_last_plt): Likewise.
	(INSERT_SPECIAL_OP): Likewise.
	(md_begin): Likewise.
	(tilegx_parse_name): Likewise.
	(parse_reg_expression): Likewise.
	(md_assemble): Likewise.
	* config/tc-tilepro.c (O_tls_ie_load): Likewise.
	(INSERT_SPECIAL_OP): Likewise.
	(tilepro_parse_name): Likewise.
	(parse_reg_expression): Likewise.
	(md_assemble): Likewise.
	* config/tc-v850.c (md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-vax.c (md_ri_to_chars): Likewise.
	(vip_begin): Likewise.
	(vip): Likewise.
	(main): Likewise.
	(md_begin): Likewise.
	* config/tc-wasm32.c (md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-xgate.c (xgate_parse_operand): Likewise.
	(md_begin): Likewise.
	(md_assemble): Likewise.
	* config/tc-z8k.c (md_begin): Likewise.
	(md_assemble): Likewise.
 2020-08-20 10:56:07 +09:30
Nick Clifton
ddc73fa987 Fix spelling mistakes in some of the binutils sub-directories. 
PR 26204
gas	* config/tc-arm.c: Fix spelling mistake.
	* config/tc-riscv.c: Likewise.
	* config/tc-z80.c: Likewise.
	* po/gas.pot: Regenerate.

ld	* lexsup.c: Fix spelling mistake.
	* po/ld.pot: Regenerate.

opcodes	* arc-dis.c: Fix spelling mistake.
	* po/opcodes.pot: Regenerate.
 2020-07-06 10:54:36 +01:00
Nelson Chu
08ccfccf0e RISC-V: Support debug and float CSR as the unprivileged ones. 
The unprivileged CSR should be controlled by other specific specs rather
than the privileged spec.  For example, the debug CSR should be controlled
by the debug spec, and the float CSR should be controlled by the float
spec.  User may use assembler options to choose what the debug and other
specs they want, or may encode the versions of specs into the architecture
string directly.  Since we haven't decided which one is better, we set the
defined and aborted versions of unprivileged CSR to PRIV_SPEC_CLASS_NONE
in the include/opcode/riscv-opc.h, to tell assembler don't check priv spec
versions for them.  However, these PRIV_SPEC_CLASS_NONE will be changed
to FLOAT_SPEC_CLASS_* and DEBUG_SPEC_CLASS_* in the future.

	gas/
	* config/tc-riscv.c (riscv_csr_class_check): Removed.  Move the
	checking into riscv_csr_address.
	(riscv_csr_version_check): Likewise.
	(riscv_csr_address): New function.  Return the suitable CSR address
	after checking the ISA dependency and versions.  Issue warnings	if
	we find any conflict and -mcsr-check is set.  CSR_CLASS_F and
	CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
	priv spec versions for them.
	(reg_csr_lookup_internal): Call riscv_csr_address to find the
	suitable CSR address.

	* testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-fext.l:  We don't care the
	priv spec warnings here.  These warnings are added by accident.
	Remove them and only focus on the ISA dependency warnings.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
	dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
	than the privileged ones.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* testsuite/gas/riscv/priv-reg.s: Likewise.  Add missing debug CSR.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
	* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.

	include/
	* opcode/riscv-opc.h: Support the unprivileged CSR.  The versions
	of the unprivileged CSR should be PRIV_SPEC_CLASS_NONE for now.
	* opcode/riscv.h (enum riscv_csr_class): Add CSR_CLASS_DEBUG.

	opcodes/
	* riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
	unprivileged CSR can also be initialized.
 2020-06-30 09:54:55 +08:00
Nelson Chu
1a79004f61 RISC-V: Generate ELF priv attributes if priv instruction are explicited used. 
We should generate the ELF priv attributes only if,

1. The priv attributes are already set in the assembly file.
2. The CSR are explicited used.
3. The privileged instruction are explicited used.

* There are four privileged instruction defined in the v1.11 priv spec:
`mret`, `sret`, `wfi` and `sfence.vma`.

* `sfence.vm` is dropped in the v1.10 priv spec.

* `uret` is actually a N-ext instruction.  So it is better to regard it as
an user instruction rather than the priv instruction.

* `hret` is used to return from traps in H-mode.  H-mode is removed since
the v1.10 priv spec, but probably be added in the new hypervisor spec.
Therefore, `hret` should be controlled by the hypervisor spec rather than
priv spec in the future.

* `dret` is a debug instruction.  We should record the debug spec versions
once it is explicited used in the future.

	gas/
	* config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to
	explicit_priv_attr.  It used to indicate CSR or priv instructions are
	explictly used.
	(riscv_is_priv_insn): Return True if it is a privileged instruction.
	(riscv_ip): Call riscv_is_priv_insn to check whether the instruction
	is privileged or not.  If it is, then set explicit_priv_attr to TRUE.
	(riscv_write_out_attrs): Clarification of when to generate the elf
	priv spec attributes.

	* testsuite/gas/riscv/attribute-11.s: Add comments.
	* testsuite/gas/riscv/attribute-14.s: New testcase.  Use symbol
	`priv_insn_<n>` to decide which priv instruction is expected to used.
	(<n> is a to g.)
	* testsuite/gas/riscv/attribute-14a.d: Likewise.
	* testsuite/gas/riscv/attribute-14b.d: Likewise.
	* testsuite/gas/riscv/attribute-14c.d: Likewise.
	* testsuite/gas/riscv/attribute-14d.d: Likewise.
	* testsuite/gas/riscv/attribute-14e.d: Likewise.
 2020-06-23 09:38:12 +08:00
Nelson Chu
39ff0b8123 RISC-V: Report warning when linking the objects with different priv specs. 
We do know some conflicts among different privileged specs.  For linker,
the safest approach is that don't allow the object linked with others which
may cause conflicts.  But this may cause inconvenience since not all objects
with conflicting priv specs are linked will cause problems.  But it is hard
to know the detailed conflict cases for linker, so we probably need a option
to tell linker that we do know there are no conflicts, or we are willing to
take risks to link the objects with conflicted priv specs.  But the option
is still under discussion.

Therefore, we can report warnings rather than errors when linking the objects
with conflicted priv specs.  This not only makes the linker more flexible,
but also warns people that the conflicts may happen.  We also need to update
the output priv spec version once the input priv spec is newer.

	bfd/
	* elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from
	opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker.
	(riscv_get_priv_spec_class): Likewise.
	(riscv_get_priv_spec_name): Likewise.
	(riscv_get_priv_spec_class_from_numbers): New function, convert
	the version numbers into string, then call riscv_get_priv_spec_class
	to get the priv spec class.
	* elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration
	from include/opcode/riscv.h to bfd/elfxx-riscv.h.
	(riscv_get_priv_spec_name): Likewise.
	(riscv_get_priv_spec_class_from_numbers): New forward declaration.
	(opcode/riscv.h): Include it in the header rather than elfxx-riscv.c.
	* elfnn-riscv.c (riscv_merge_attributes):  Get the priv spec classes
	of input and output objects form their priv spec attributes by
	riscv_get_priv_spec_class_from_numbers.  Report warning rather than
	errors when linking objects with differnet priv spec versions.  We do
	know v1.9.1 may have conflicts to other versions, so report the
	warning, too.  After that, update the output priv spec version to the
	newest one so far.

	gas/
	* config/tc-riscv.c (buf_size, buf): Remove the unused variables.
	(riscv_set_default_priv_spec): Get the priv spec version from the
	priv spec attributes by riscv_get_priv_spec_class_from_numbers.

	include/
	* opcode/riscv.h (riscv_get_priv_spec_class): Move the function
	forward declarations to bfd/elfxx-riscv.h.
	(riscv_get_priv_spec_name): Likewise.

	opcodes/
	* riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
	* riscv-dis.c: Include elfxx-riscv.h.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.
 2020-06-22 10:01:14 +08:00
Nelson Chu
3fc6c3dc2a RISC-V: Don't generate the ELF privilege attributes when no CSR are used. 
gas/
	* config/tc-riscv.c (explicit_csr): New static boolean.
	Used to indicate CSR are explictly used.
	(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
	(riscv_write_out_attrs): If we already have set elf priv
	attributes, then generate them.  Otherwise, don't generate
	them when no CSR are used.

	* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-11.s: New testcase.
	* testsuite/gas/riscv/attribute-11.d: New testcase.  The CSR is
	used, so we should output the ELF priv attributes.
	* testsuite/gas/riscv/attribute-12.d: New testcase.  The CSR is
	used, so output the priv attributes according to the -mpriv-spec.
	* testsuite/gas/riscv/attribute-13.d: New testcase.  The CSR isn't
	used, so ignore the -mpriv-spec setting.

	ld/
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
	* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
 2020-06-05 12:14:44 +08:00
Simon Cook
5c5055683b RISC-V: Fix missing initialization of riscv_csr_extra structs 
The next pointer of struct riscv_csr_extra was not always initilized
to NULL or a valid pointer, causing the assembler to attempt to read
through an uninitialized pointer on startup.

gas/ChangeLog:

        * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
        pointer when creating struct riscv_csr_extra.
 2020-05-27 16:38:37 -07:00