Commit Graph

6 Commits

Author SHA1 Message Date
Andrew Burgess
a143b0045c opcodes/cgen: Rework calculation of shift when inserting fields
The calculation of the shift amount, used to insert fields into the
instruction buffer, is not correct when the following conditions are all
true:
  - CGEN_INT_INSN_P is defined, and true.
  - CGEN_INSN_LSB0_P is true
  - Total instruction length is greater than the length of a single
    instruction word (the instruction is made of multiple words)
  - The word offset is non-zero (the field is outside the first word)

When the above conditions are all true, the calculated shift fails to
take account of the total instruction length.

After this commit the calculation of the shift amount is split into two
parts, first we calculate the shift required to get to BIT0 of the word
in which the field lives, then we calculate the shift required to place
the field within the instruction word.

The change in this commit only effects the CGEN_INT_INSN_P defined true
case, but changes the code for both CGEN_INSN_LSB0_P true, and false.

In the case of CGEN_INSN_LSB0_P being false, the code used to say:

	shift = total_length - (word_offset + start + length);

Now it says:

	shift_to_word = total_length - (word_offset + word_length);
	shift_within_word = word_length - start - length;
	shift = shift_to_word + shift_within_word;

From which we can see that in all cases the computed shift value should
be unchanged.

In the case of CGEN_INSN_LSB0_P being true, the code used to say:

	shift = (word_offset + start + 1) - length;

Now it says:

	shift_to_word = total_length - (word_offset + word_length);
	shift_within_word = start + 1 - length;
	shift = shift_to_word + shift_within_word;

In the case where 'total_length == word_length' AND 'word_offset ==
0' (which indicates an instruction of a single word), we see that the
computed shift value will be unchanged.  However, when the total_length
and word_length are different, and the word_offset is non-zero then the
computed shift value will be different (and correct).

opcodes/ChangeLog:

	* cgen-ibld.in (insert_normal): Rework calculation of shift.
	* epiphany-ibld.c: Regenerate.
	* fr30-ibld.c: Regenerate.
	* frv-ibld.c: Regenerate.
	* ip2k-ibld.c: Regenerate.
	* iq2000-ibld.c: Regenerate.
	* lm32-ibld.c: Regenerate.
	* m32c-ibld.c: Regenerate.
	* m32r-ibld.c: Regenerate.
	* mep-ibld.c: Regenerate.
	* mt-ibld.c: Regenerate.
	* or1k-ibld.c: Regenerate.
	* xc16x-ibld.c: Regenerate.
	* xstormy16-ibld.c: Regenerate.
2016-02-02 11:09:17 +00:00
Alan Modra
6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
H.J. Lu
43e65147c0 Remove trailing spaces in opcodes 2015-08-12 04:45:07 -07:00
Alan Modra
b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Alan Modra
c151b1c645 Whitespace fixes for cpu/or1k.opc
* or1k.opc: Whitespace fixes.
2014-06-12 12:30:57 +09:30
Christian Svensson
73589c9dbd Remove support for the (deprecated) openrisc and or32 configurations and replace
with support for the new or1k configuration.
2014-04-22 15:57:47 +01:00