Commit Graph

3762 Commits

Author SHA1 Message Date
Jan Beulich
a5aaedb9db x86: correct mis-named MOD_0F51 enumerator
This is for extension major opcode 50, so name it accordingly.
2020-06-09 08:55:50 +02:00
Alex Coplan
26417f1919 [PATCH] arm: Add DFB instruction for ARMv8-R
gas/ChangeLog:
2020-06-08  Alex Coplan  <alex.coplan@arm.com>

	* config/tc-arm.c (insns): Add dfb.
	* testsuite/gas/arm/dfb.d: New test.
	* testsuite/gas/arm/dfb.s: Input for test.

opcodes/ChangeLog:
2020-06-08  Alex Coplan  <alex.coplan@arm.com>

	* arm-dis.c (arm_opcodes): Add dfb.
	(thumb32_opcodes): Add dfb.
2020-06-08 15:16:29 +01:00
Jan Beulich
8a6fb3f9bb x86: restrict use of register aliases
Register aliases (created e.g. via .set) check their target register at
the time of creation of the alias. While this makes sense, it's not
enough: The underlying register must also be "visible" at the time of
use. Wrong use of such aliases would lead to internal errors in e.g.
add_prefix() or build_modrm_byte().

Split the checking part of parse_real_register() into a new helper
function and use it also from the latter part of parse_register() (at
the same time replacing a minor open coded part of it).

Since parse_register() returning NULL already has a meaning, a fake new
"bad register" indicator gets added, which all callers need to check
for.
2020-06-08 08:37:47 +02:00
Alan Modra
1424c35d07 Power10 tidies
binutils/
	* doc/binutils.texi (PowerPC -M option): Mention power10 and pwr10.
gas/
	* config/tc-ppc.c (md_show_usage): Mention -mpower10 and -mpwr10.
	* doc/c-ppc.texi: Likewise.
opcodes/
	* ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
2020-06-06 14:44:32 +09:30
Alan Modra
d3d1cc7b13 bpf stack smashing detected
* cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
	size is large enough.
2020-06-05 16:22:46 +09:30
Jose E. Marchesi
d8740be159 cpu,gas,opcodes: remove no longer needed workaround from the BPF port
cpu/ChangeLog:

2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
	* bpf.opc (bpf_print_insn): Do not set endian_code here.

gas/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
	bpf_cgen_cpu_open.
	(md_assemble): Remove no longer needed hack.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* disassemble.c (disassemble_init_for_target): Set endian_code for
	bpf targets.
	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.
2020-06-04 16:17:42 +02:00
Jose E. Marchesi
e9bffec9af opcodes: discriminate endianness and insn-endianness in CGEN ports
The CGEN support code in opcodes accesses instruction contents using a
couple of functions defined in cgen-opc.c: cgen_get_insn_value and
cgen_put_insn_value.  These functions use the "instruction endianness"
in the CPU description to order the read/written bytes.

The process of writing an instruction to the object file is:

  a) cgen_put_insn_value        ;; Writes out the opcodes.
  b) ARCH_cgen_insert_operand
       insert_normal
         insert_1
           cgen_put_insn_value  ;; Writes out the bytes of the
                                ;; operand.

Likewise, the process of reading an instruction from the object file
is:

  a) cgen_get_insn_value        ;; Reads the opcodes.
  b) ARCH_cgen_extract_operand
       extract_normal
         extract_1
           cgen_get_insn_value  ;; Reads in the bytes of the
                                ;; operand.

As can be seen above, cgen_{get,put}_insn_value are used to both
process the instruction opcodes (the constant fields conforming the
base instruction) and also the values of the instruction operands,
such as immediates.

This is problematic for architectures in which the endianness of
instructions is different to the endianness of data.  An example is
BPF, where instructions are always encoded big-endian but the data may
be either big or little.

This patch changes the cgen_{get,put}_insn_value functions in order to
get an extra argument with the endianness to use, and adapts the
existin callers to these functions in order to provide cd->endian or
cd->insn_endian, whatever appropriate.  Callers like extract_1 and
insert_1 pass cd->endian (since they are reading/writing operand
values) while callers reading/writing the base instruction pass
cd->insn_endian instead.

A few little adjustments have been needed in some existing CGEN based
ports:
* The BPF assembler uses cgen_put_insn_value.  It has been adapted to
  pass the new endian argument.
* The mep port has code in mep.opc that uses cgen_{get,put}_insn_value.
  It has been adapted to pass the new endianargument.  Ditto for a
  call in the assembler.

Tested with --enable-targets=all.
Regested in all supported targets.
No regressions.

include/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/cgen.h: Get an `endian' argument in both
	cgen_get_insn_value and cgen_put_insn_value.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
	(cgen_put_insn_value): Likewise.
	(cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
	* cgen-dis.in (print_insn): Likewise.
	* cgen-ibld.in (insert_1): Likewise.
	(insert_1): Likewise.
	(insert_insn_normal): Likewise.
	(extract_1): Likewise.
	* bpf-dis.c: Regenerate.
	* bpf-ibld.c: Likewise.
	* bpf-ibld.c: Likewise.
	* cgen-dis.in: Likewise.
	* cgen-ibld.in: Likewise.
	* cgen-opc.c: Likewise.
	* epiphany-dis.c: Likewise.
	* epiphany-ibld.c: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-ibld.c: Likewise.
	* frv-dis.c: Likewise.
	* frv-ibld.c: Likewise.
	* ip2k-dis.c: Likewise.
	* ip2k-ibld.c: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-ibld.c: Likewise.
	* lm32-dis.c: Likewise.
	* lm32-ibld.c: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-ibld.c: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-ibld.c: Likewise.
	* mep-dis.c: Likewise.
	* mep-ibld.c: Likewise.
	* mt-dis.c: Likewise.
	* mt-ibld.c: Likewise.
	* or1k-dis.c: Likewise.
	* or1k-ibld.c: Likewise.
	* xc16x-dis.c: Likewise.
	* xc16x-ibld.c: Likewise.
	* xstormy16-dis.c: Likewise.
	* xstormy16-ibld.c: Likewise.

gas/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* cgen.c (gas_cgen_finish_insn): Pass the endianness to
	cgen_put_insn_value.
	(gas_cgen_md_apply_fix): Likewise.
	(gas_cgen_md_apply_fix): Likewise.
	* config/tc-bpf.c (md_apply_fix): Pass data endianness to
	cgen_put_insn_value.
	* config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to
	cgen_put_insn_value.

cpu/ChangeLog:

2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* mep.opc (print_slot_insn): Pass the insn endianness to
	cgen_get_insn_value.
2020-06-04 16:17:42 +02:00
Jose E. Marchesi
b3db6d07be opcodes: support insn endianness in cgen_cpu_open
This patch adds support for a new CGEN_OPEN_INSN_ENDIAN argument
for @arch@_cgen_cpu_open.  This is useful for architectures in
which the endianness of the instruction words is not the same
than the endianness used for data.

An accompanying patch has been sent to the CGEN mailing list that
adds support for this argument on the CGEN side [1].  Its been
already pre-approved [2], and will be applied simultaneously with
this binutils series.

[1] https://sourceware.org/pipermail/cgen/2020q2/002733.html
[2] https://sourceware.org/pipermail/cgen/2020q2/002737.html

include/ChangeLog:

2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>

	* opcode/cgen.h (enum cgen_cpu_open_arg): New value
	CGEN_CPU_OPEN_INSN_ENDIAN.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>

	* cgen-dis.in (cpu_desc_list): New field `insn_endian'.
	(print_insn_): Handle instruction endian.
	* bpf-dis.c: Regenerate.
	* bpf-desc.c: Regenerate.
	* epiphany-dis.c: Likewise.
	* epiphany-desc.c: Likewise.
	* fr30-dis.c: Likewise.
	* fr30-desc.c: Likewise.
	* frv-dis.c: Likewise.
	* frv-desc.c: Likewise.
	* ip2k-dis.c: Likewise.
	* ip2k-desc.c: Likewise.
	* iq2000-dis.c: Likewise.
	* iq2000-desc.c: Likewise.
	* lm32-dis.c: Likewise.
	* lm32-desc.c: Likewise.
	* m32c-dis.c: Likewise.
	* m32c-desc.c: Likewise.
	* m32r-dis.c: Likewise.
	* m32r-desc.c: Likewise.
	* mep-dis.c: Likewise.
	* mep-desc.c: Likewise.
	* mt-dis.c: Likewise.
	* mt-desc.c: Likewise.
	* or1k-dis.c: Likewise.
	* or1k-desc.c: Likewise.
	* xc16x-dis.c: Likewise.
	* xc16x-desc.c: Likewise.
	* xstormy16-dis.c: Likewise.
	* xstormy16-desc.c: Likewise.

binutils/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* objdump.c (disassemble_data): Set disasm_info.endian_code to
        disasm_info.endian after the latter is initialized to the
        endianness reported by BFD.
2020-06-04 16:17:42 +02:00
Nick Clifton
4ee4189f86 Updated Serbian translation for the opcodes sub-directory 2020-06-03 15:29:09 +01:00
Nelson Chu
44730156af RISC-V: Fix the error when building RISC-V linux native gdbserver.
The original report is as follow,
https://sourceware.org/pipermail/binutils/2020-June/111383.html

Inlcude the bfd.h in the include/opcode/riscv.h may cause gdbserver fail
to build.  I just want to use the `bfd_boolean` in the opcodes/riscv-opc.c,
but I didn't realize this cause the build failed.  Fortunately, I can also
use the `int` as the function return types just like others in the
opcodes/riscv-opc.c.

	include/
	* opcode/riscv.h: Remove #include "bfd.h".  And change the return
	types of riscv_get_isa_spec_class and riscv_get_priv_spec_class
	from bfd_boolean to int.

	opcodes/
	* riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
	(riscv_get_priv_spec_class): Likewise.
2020-06-03 09:20:59 +08:00
Alan Modra
3c3d03769e Regen opcodes/bpf-desc.c
The last regen used an old version of cgen.

	* bpf-desc.c: Regenerate.
2020-06-01 19:53:05 +09:30
Jose E. Marchesi
78c1c35437 cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes
This patch adds semantic RTL descriptions to the eBPF instructions
defined in cpu/bpf.cpu.  It also contains a couple of minor
improvements.

Tested in bpf-unknown-none targets.
No regressions.

cpu/ChangeLog:

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf.cpu (define-alu-insn-un): Add definitions of semantics.
	(define-alu-insn-mov): Likewise.
	(daib): Likewise.
	(define-alu-instructions): Likewise.
	(define-endian-insn): Likewise.
	(define-lddw): Likewise.
	(dlabs): Likewise.
	(dlind): Likewise.
	(dxli): Likewise.
	(dxsi): Likewise.
	(dsti): Likewise.
	(define-ldstx-insns): Likewise.
	(define-st-insns): Likewise.
	(define-cond-jump-insn): Likewise.
	(dcji): Likewise.
	(define-condjump-insns): Likewise.
	(define-call-insn): Likewise.
	(ja): Likewise.
	("exit"): Likewise.
	(define-atomic-insns): Likewise.
	(sem-exchange-and-add): New macro.
	* bpf.cpu ("brkpt"): New instruction.
	(bpfbf): Set word-bitsize to 32 and insn-endian big.
	(h-gpr): Prefer r0 to `a' and r6 to `ctx'.
	(h-pc): Expand definition.
	* bpf.opc (bpf_print_insn): Set endian_code to BIG.

opcodes/ChangeLog:

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.
2020-05-28 21:52:31 +02:00
Alan Modra
efcf5fb585 ubsan: nios2: undefined shift
* nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
	values.
2020-05-28 22:08:42 +09:30
Alan Modra
ab382d6426 asan: ns32k: use of uninitialized value
* ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
	immediates.
	(print_insn_ns32k): Revert last change.
2020-05-28 21:11:32 +09:30
Nick Clifton
151f5de4a6 Fix a potential use of an uninitialised value in the ns32k disassembler.
* ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
	static.
2020-05-28 11:04:27 +01:00
Sandra Loosemore
25e1eca8fa Fix extraction of signed constants in nios2 disassembler (again).
In commit 6031ac352c I added some casts
to explicitly do conversions from unsigned to signed as 32-bit
quantities to address some bugs with different sizes of long and
bfd_signed_vma.  Those casts were removed in the rewrite of the
sign-extension logic in commit 1d61b03226,
reintroducing the same bugs.  This patch restores the casts.

2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>

	opcodes/
	* nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
	extractions of signed fields.
2020-05-26 23:23:03 -07:00
Stefan Schulze Frielinghaus
57b179405a ChangeLog entries for f687f5f563 2020-05-26 18:35:51 +02:00
Stefan Schulze Frielinghaus
f687f5f563 S/390: z13: Accept vector alignment hints
Accept vector alignment hints on z13 although they are ignored there.
The advantage is that any binary compiled for architecture level z13 may
run on z14 or later and benefit from vector alignment hints.

gas/ChangeLog:

2020-05-18  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector
	load/store instruction variants with alignment hints.
	* testsuite/gas/s390/zarch-z13.s: Emit new vector load/store
	instruction variants with alignment hints.

opcodes/ChangeLog:

2020-05-18  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>

	* s390-opc.txt: Relocate vector load/store instructions with
	additional alignment parameter and change architecture level
	constraint from z14 to z13.
2020-05-26 18:15:41 +02:00
Alan Modra
d96bf37ba8 Replace "if (x) free (x)" with "free (x)", opcodes
cpu/
	* mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace
	"if (x) free (x)" with "free (x)".
opcodes/
	* arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
	* sparc-dis.c: Likewise.
	* tic4x-dis.c: Likewise.
	* xtensa-dis.c: Likewise.
	* bpf-desc.c: Regenerate.
	* epiphany-desc.c: Regenerate.
	* fr30-desc.c: Regenerate.
	* frv-desc.c: Regenerate.
	* ip2k-desc.c: Regenerate.
	* iq2000-desc.c: Regenerate.
	* lm32-desc.c: Regenerate.
	* m32c-desc.c: Regenerate.
	* m32r-desc.c: Regenerate.
	* mep-asm.c: Regenerate.
	* mep-desc.c: Regenerate.
	* mt-desc.c: Regenerate.
	* or1k-desc.c: Regenerate.
	* xc16x-desc.c: Regenerate.
	* xstormy16-desc.c: Regenerate.
2020-05-21 10:45:33 +09:30
Nelson Chu
8f595e9b4f [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.

2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.

3. Spilt the patches to reduce the burdens of review.

[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.

[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.

4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.

include	* opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
	(enum riscv_isa_spec_class): New enum class.  All supported ISA spec
	belong to one of the class
	(struct riscv_ext_version): New structure holds version information
	for the specific ISA.
	* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
	define_version and abort_version.  The define_version means which
	privilege spec is started to define the CSR, and the abort_version
	means which privilege spec is started to abort the CSR.  If the CSR is
	valid for the newest spec, then the abort_version should be
	PRIV_SPEC_CLASS_DRAFT.
	(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
	* opcode/riscv.h (enum riscv_priv_spec_class): New enum class.  Define
	the current supported privilege spec versions.
	(struct riscv_csr_extra): Add new fields to store more information
	about the CSR.  We use these information to find the suitable CSR
	address when user choosing a specific privilege spec.

binutils * dwarf.c: Updated since DECLARE_CSR is changed.

opcodes	* riscv-opc.c (riscv_ext_version_table): The table used to store
	all information about the supported spec and the corresponding ISA
	versions.  Currently, only Zicsr is supported to verify the
	correctness of Z sub extension settings.  Others will be supported
	in the future patches.
	(struct isa_spec_t, isa_specs): List for all supported ISA spec
	classes and the corresponding strings.
	(riscv_get_isa_spec_class): New function.  Get the corresponding ISA
	spec class by giving a ISA spec string.
	* riscv-opc.c (struct priv_spec_t): New structure.
	(struct priv_spec_t priv_specs): List for all supported privilege spec
	classes and the corresponding strings.
	(riscv_get_priv_spec_class): New function.  Get the corresponding
	privilege spec class by giving a spec string.
	(riscv_get_priv_spec_name): New function.  Get the corresponding
	privilege spec string by giving a CSR version class.
	* riscv-dis.c: Updated since DECLARE_CSR is changed.
	* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
	according to the chosen version.  Build a hash table riscv_csr_hash to
	store the valid CSR for the chosen pirv verison.  Dump the direct
	CSR address rather than it's name if it is invalid.
	(parse_riscv_dis_option_without_args): New function.  Parse the options
	without arguments.
	(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
	parse the options without arguments first, and then handle the options
	with arguments.  Add the new option -Mpriv-spec, which has argument.
	* riscv-dis.c (print_riscv_disassembler_options): Add description
	about the new OBJDUMP option.

ld	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
        priv attributes according to the -mpriv-spec option.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.

bfd 	* elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
	get_default_version.  It is used to find the default version for
	the specific extension.
	* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
	default_major_version and default_minor_version.  Add new bfd_boolean
	parameter *use_default_version.  Set it to TRUE if we need to call
	the callback rps->get_default_version to find the default version.
	(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
	the default version in riscv_parsing_subset_version, and then call
	riscv_add_subset to add the subset into subset list.
	(riscv_parse_prefixed_ext): Likewise.
	(riscv_std_z_ext_strtab): Support Zicsr extensions.
	* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
	strings rather than characters.
	riscv_merge_arch_attr_info): The callback function get_default_version
	is only needed for assembler, so set it to NULL int the linker.
	* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
	* elfxx-riscv.h: Updated.

gas	* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
	* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
	Static variables which are used to set the ISA extensions. You can
	use -march (or ELF build attributes) and -misa-spec to set them,
	respectively.
	(ext_version_hash): The hash table used to handle the extensions
	with versions.
	(init_ext_version_hash): Initialize the ext_version_hash according
	to riscv_ext_version_table.
	(riscv_get_default_ext_version): The callback function of
	riscv_parse_subset_t.  According to the choosed ISA spec,
	get the default version for the specific extension.
	(riscv_set_arch): Set the callback function.
	(enum options, struct option md_longopts): Add new option -misa-spec.
	(md_parse_option): Do not call riscv_set_arch for -march.  We will
	call it later in riscv_after_parse_args.  Call riscv_get_isa_spec_class
	to set default_isa_spec class.
	(riscv_after_parse_args): Call init_ext_version_hash to initialize the
	ext_version_hash, and then call riscv_set_arch to set the architecture
	with versions according to default_arch_with_ext.
	* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
	x extensions.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: New testcase.  For i-ext, we
	already set it's version to 2p1 by march, so no need to use the default
	2p2 version.  For m-ext, we do not set the version by -march and ELF arch
	attribute, so set the default 2p0 to it.  For zicsr, it is not defined in
	ISA spec 2p2, so set 0p0 to it.
	* testsuite/gas/riscv/attribute-10.d: New testcase.  The version of
	zicsr is 2p0 according to ISA spec 20191213.
	* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
	(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
	You can set them by configure options --with-arch and
	--with-isa-spec, respectively.
	(riscv_set_default_isa_spec): New function used to set the
	default ISA spec.
	(md_parse_option): Call riscv_set_default_isa_spec rather than
	call riscv_get_isa_spec_class directly.
	(riscv_after_parse_args): If the -isa-spec is not set, then we
	set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
	calling riscv_set_default_isa_spec.
	* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
	the --with-isa-spec may be set to different ISA spec.
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* configure.ac: Add configure options, --with-arch and
	--with-isa-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (default_priv_spec): Static variable which is
	used to check if the CSR is valid for the chosen privilege spec. You
	can use -mpriv-spec to set it.
	(enum reg_class): We now get the CSR address from csr_extra_hash rather
	than reg_names_hash.  Therefore, move RCLASS_CSR behind RCLASS_MAX.
	(riscv_init_csr_hashes): Only need to initialize one hash table
	csr_extra_hash.
	(riscv_csr_class_check): Change the return type to void.  Don't check
	the ISA dependency if -mcsr-check isn't set.
	(riscv_csr_version_check): New function.  Check and find the CSR address
	from csr_extra_hash, according to default_priv_spec.  Report warning
	for the invalid CSR if -mcsr-check is set.
	(reg_csr_lookup_internal): Updated.
	(reg_lookup_internal): Likewise.
	(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
	(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
	(md_parse_option): Call riscv_set_default_priv_version to set
	default_priv_spec.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
	privilege spec to the newest one.
	(enum riscv_csr_class, struct riscv_csr_extra): Move them to
	include/opcode/riscv.h.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
	to check the ISA dependency for CSR, so fix the spec version by adding
	-mpriv-spec=1.11.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.  There are some
	version warnings for the test case.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
	Check whether the CSR is valid when privilege version 1.9 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
	Check whether the CSR is valid when privilege version 1.9.1 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
	Check whether the CSR is valid when privilege version 1.10 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
	Check whether the CSR is valid when privilege version 1.11 is choosed.
	* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
	setting.  You can set it by configure option --with-priv-spec.
	(riscv_set_default_priv_spec): New function used to set the default
	privilege spec.
	(md_parse_option): Call riscv_set_default_priv_spec rather than
	call riscv_get_priv_spec_class directly.
	(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
	default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
	calling riscv_set_default_priv_spec.
	* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
	the --with-priv-spec may be set to different privilege spec.
	* testsuite/gas/riscv/priv-reg.d: Likewise.
	* configure.ac: Add configure option --with-priv-spec.
	* configure: Regenerated.
	* config.in: Regenerated.
	* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
	explicit_attr.  Set it to TRUE if any ELF attribute is found.
	(riscv_set_default_priv_spec): Try to set the default_priv_spec if
	the priv attributes are set.
	(md_assemble): Set the default_priv_spec according to the priv
	attributes when we start to assemble instruction.
	(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
	riscv_write_out_attrs.  Update the arch and priv attributes.  If we
	don't set the corresponding ELF attributes, then try to output the
	default ones.
	(riscv_set_public_attributes): If any ELF attribute or -march-attr
	options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
	to update the arch and priv attributes.
	(s_riscv_attribute): Make sure all arch and priv attributes are set
	before any instruction.
	* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
	ELF attribute or -march-attr is set.  If the priv attributes are not
	set, then try to update them by the default setting (-mpriv-spec or
	--with-priv-spec).
	* testsuite/gas/riscv/attribute-02.d: Likewise.
	* testsuite/gas/riscv/attribute-03.d: Likewise.
	* testsuite/gas/riscv/attribute-04.d: Likewise.
	* testsuite/gas/riscv/attribute-06.d: Likewise.
	* testsuite/gas/riscv/attribute-07.d: Likewise.
	* testsuite/gas/riscv/attribute-08.d: Likewise.
	* testsuite/gas/riscv/attribute-09.d: Likewise.
	* testsuite/gas/riscv/attribute-10.d: Likewise.
	* testsuite/gas/riscv/attribute-unknown.d: Likewise.
	* testsuite/gas/riscv/attribute-05.d: Likewise.  Also, the priv spec
	set by priv attributes must be supported.
	* testsuite/gas/riscv/attribute-05.s: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise.  Updated
	priv attributes according to the -mpriv-spec option.
	* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
	* testsuite/gas/riscv/priv-reg.d: Removed.
	* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case.  Dump the
	CSR according to the priv spec 1.9.
	* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case.  Dump the
	CSR according to the priv spec 1.9.1.
	* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case.  Dump the
	CSR according to the priv spec 1.10.
	* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case.  Dump the
	CSR according to the priv spec 1.11.
	* config/tc-riscv.c (md_show_usage): Add descriptions about
	the new GAS options.
	* doc/c-riscv.texi: Likewise.
2020-05-20 17:22:48 +01:00
Peter Bergner
3d205eb448 Power10 dcbf, sync, and wait extensions.
opcodes/
	* ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
	WC values on POWER10 sync, dcbf  and wait instructions.
	(insert_pl, extract_pl): New functions.
	(L2OPT, LS, WC): Use insert_ls and extract_ls.
	(LS3): New , 3-bit L for sync.
	(LS3, L3OPT): New, 3-bit L for sync and dcbf.
	(SC2, PL): New, 2-bit SC and PL for sync and wait.
	(XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
	(XOPL3, XWCPL, XSYNCLS): New opcode macros.
	(powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
	plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
	<wait>: Enable PL operand on POWER10.
	<dcbf>: Enable L3OPT operand on POWER10.
	<sync>: Enable SC2 operand on POWER10.

gas/
	* testsuite/gas/ppc/power9.s <dcbf, dcbfl, dcbflp>: Add tests.
	* testsuite/gas/ppc/power9.d: Likewise.
	* testsuite/gas/ppc/power10.s <dcbf, dcbfps, dcbstps, hwsync, lwsync,
	pause_short, phwsync, plwsync, ptesync, stcisync, stncisync, stsync,
	sync, wait, waitrsv>: Add tests.
	* testsuite/gas/ppc/power10.d: Likewise.
2020-05-19 18:09:51 -05:00
Stafford Horne
a501eb446f or1k: Regenerate opcodes after removing 32-bit support
opcodes/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	PR 25184
	* or1k-asm.c: Regenerate.
	* or1k-desc.c: Regenerate.
	* or1k-desc.h: Regenerate.
	* or1k-dis.c: Regenerate.
	* or1k-ibld.c: Regenerate.
	* or1k-opc.c: Regenerate.
	* or1k-opc.h: Regenerate.
	* or1k-opinst.c: Regenerate.
2020-05-19 20:41:03 +09:00
Alan Modra
3b646889b0 Power10 VSX scalar min-max-compare quad precision operations
opcodes/
	* ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
	xsmaxcqp, xsmincqp.
gas/
	* testsuite/gas/ppc/scalarquad.d,
	* testsuite/gas/ppc/scalarquad.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:38 +09:30
Alan Modra
9cc4ce8831 Power10 VSX load/store rightmost element operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
	stxvrbx, stxvrhx, stxvrwx, stxvrdx.
gas/
	* testsuite/gas/ppc/rightmost.d,
	* testsuite/gas/ppc/rightmost.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
5d57bc3ff9 Power10 test lsb by byte operation
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
gas/
	* testsuite/gas/ppc/xvtlsbb.d,
	* testsuite/gas/ppc/xvtlsbb.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
66ef5847c3 Power10 string operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
	vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
gas/
	* testsuite/gas/ppc/stringop.d,
	* testsuite/gas/ppc/stringop.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Peter Bergner
4f3e9537c4 Power10 Set boolean extension
opcodes/
	* ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
	mnemonics.
gas/
	* testsuite/gas/ppc/set_bool.d,
	* testsuite/gas/ppc/set_bool.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
ec40e91c77 Power10 bit manipulation operations
opcodes/
	* ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
	(powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
	vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
	(prefix_opcodes): Add xxeval.
gas/
	* testsuite/gas/ppc/bitmanip.d,
	* testsuite/gas/ppc/bitmanip.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
d7e97a765e Power10 VSX PCV generate operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
	xxgenpcvwm, xxgenpcvdm.
gas/
	* testsuite/gas/ppc/genpcv.d,
	* testsuite/gas/ppc/genpcv.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
fdefed7c26 Power10 VSX Mask Manipulation Operations
opcodes/
	* ppc-opc.c (MP, VXVAM_MASK): Define.
	(VXVAPS_MASK): Use VXVA_MASK.
	(powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
	vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
	vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
	vcntmbb, vcntmbh, vcntmbw, vcntmbd.
gas/
	* testsuite/gas/ppc/maskmanip.d,
	* testsuite/gas/ppc/maskmanip.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
aa3c112fab Power10 Reduced precision outer product operations
include/
	* opcode/ppc.h (PPC_OPERAND_ACC): Define.  Renumber following
	PPC_OPERAND defines.
opcodes/
	* ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
	New functions.
	(powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
	YMSK2, XA6a, XA6ap, XB6a entries.
	(PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
	(P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
	(PPCVSX4): Define.
	(powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
	xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
	xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
	xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
	xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
	xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
	xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
	(prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
	pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
	pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
	pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
	pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
	pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
	pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
gas/
	* config/tc-ppc.c (pre_defined_registers): Add accumulators.
	(md_assemble): Check acc specified in correct operand.
	* testsuite/gas/ppc/outerprod.d,
	* testsuite/gas/ppc/outerprod.s,
	* testsuite/gas/ppc/vsx4.d,
	* testsuite/gas/ppc/vsx4.s: New tests.
	* testsuite/gas/ppc/ppc.exp: Run them.
2020-05-11 21:08:37 +09:30
Alan Modra
6edbfd3beb Power10 SIMD permute class operations
opcodes/
	* ppc-opc.c (insert_imm32, extract_imm32): New functions.
	(insert_xts, extract_xts): New functions.
	(IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
	(P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
	(VXRC_MASK, VXSH_MASK): Define.
	(powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
	vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
	vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
	vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
	vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
	(prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
	xxblendvh, xxblendvw, xxblendvd, xxpermx.
gas/
	* testsuite/gas/ppc/simd_perm.d,
	* testsuite/gas/ppc/simd_perm.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
c7d7aea2f5 Power10 128-bit binary integer operations
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
	vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
	vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
	vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
	xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
gas/
	* testsuite/gas/ppc/int128.d,
	* testsuite/gas/ppc/int128.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Alan Modra
94ba9882d5 Power10 VSX 32-byte storage access
bfd/
	* elf64-ppc.c (xlate_pcrel_opt): Handle lxvp and stxvp.
opcodes/
	* ppc-opc.c (insert_xtp, extract_xtp): New functions.
	(XTP, DQXP, DQXP_MASK): Define.
	(powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
	(prefix_opcodes): Add plxvp and pstxvp.
gas/
	* testsuite/gas/ppc/vsx_32byte.d,
	* testsuite/gas/ppc/vsx_32byte.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
ld/
	* testsuite/ld-powerpc/pcrelopt.s: Add lxvp and stxvp.
	* testsuite/ld-powerpc/pcrelopt.d: Update.
2020-05-11 21:08:37 +09:30
Alan Modra
f4791f1afa Power10 vector integer multiply, divide, modulo insns
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
	vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
	vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
gas/
	* testsuite/gas/ppc/vec_mul.s,
	* testsuite/gas/ppc/vec_mul.d: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:37 +09:30
Peter Bergner
3ff0a5ba64 Power10 byte reverse instructions
opcodes/
	* ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
gas/
	* testsuite/gas/ppc/byte_rev.d,
	* testsuite/gas/ppc/byte_rev.s: New test.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:36 +09:30
Peter Bergner
afef4fe975 Power10 Copy/Paste Extensions
opcodes/
	* opcodes/ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
	(L1OPT): Define.
	(powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
gas/
	* testsuite/gas/ppc/power10.d: Add paste. tests.
	* testsuite/gas/ppc/power10.s: Likewise.
2020-05-11 21:08:36 +09:30
Peter Bergner
1224c05de4 Power10 Add new L operand to the slbiag instruction
opcodes/
	* ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
gas/
	* testsuite/gas/ppc/power10.s: New test.
	* testsuite/gas/ppc/power10.d: Likewise.
	* testsuite/gas/ppc/ppc.exp: Run it.
2020-05-11 21:08:36 +09:30
Alan Modra
6bbb0c0595 PowerPC Default disassembler to -Mpower10
* ppc-dis.c (powerpc_init_dialect): Default to "power10".
2020-05-11 21:08:36 +09:30
Alan Modra
7c1f422735 PowerPC Rename powerxx to power10
Now that ISA3.1 is out we can finish with the powerxx silliness.

bfd/
	* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
	* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
	renaming.
	* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
	place of -mfuture/-Mfuture.
	* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
	* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
	* powerpc.cc: Rename powerxx to power10 throughout.
include/
	* elf/ppc64.h: Update comment.
	* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
	* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
	place of -mfuture/-Mfuture.
	* testsuite/ld-powerpc/notoc2.d: Likewise.
	* testsuite/ld-powerpc/powerpc.exp: Likewise.
	* testsuite/ld-powerpc/tlsgd.d: Likewise.
	* testsuite/ld-powerpc/tlsie.d: Likewise.
	* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
	* ppc-dis.c (ppc_opts): Add "power10" entry.
	(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
	* ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
2020-05-11 21:08:36 +09:30
Nick Clifton
73199c2b7a Updated French translation for the ld sub-directory and an update Spanish translation for the opcodes subdirectory. 2020-05-11 12:02:26 +01:00
Alex Coplan
09c1e68a16 AArch64: add GAS support for UDF instruction
binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
          disassembly.
        * testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.

ld/     * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly.
        * testsuite/ld-aarch64/farcall-b-section.d: Likewise.
        * testsuite/ld-aarch64/farcall-back.d: Likewise.
        * testsuite/ld-aarch64/farcall-bl-section.d: Likewise.

gas/   * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED.
          (parse_operands): Implement for AARCH64_OPND_UNDEFINED.
        * testsuite/gas/aarch64/udf.s: New.
        * testsuite/gas/aarch64/udf.d: New.
        * testsuite/gas/aarch64/udf-invalid.s: New.
        * testsuite/gas/aarch64/udf-invalid.l: New.
        * testsuite/gas/aarch64/udf-invalid.d: New.

include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED.

opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
        * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
          (operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED.
        * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for
          FLD_imm16_2.
        * aarch64-asm-2.c: Regenerated.
        * aarch64-dis-2.c: Regenerated.
        * aarch64-opc-2.c: Regenerated.
2020-04-30 15:47:30 +01:00
Nick Clifton
9654d51a96 Also use unsigned 8-bit immediate values for the LDRC and SETRC insns.
PR 22699
	* sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
	and SETRC insns.
2020-04-29 16:09:38 +01:00
Nick Clifton
c2e71e57a0 Updated Serbian translation for the binutils sub-directory, and Swedish translation for the opcodes sub-directory. 2020-04-29 13:23:32 +01:00
Nick Clifton
5c936ef50f Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate operand.
PR 22699
opcodes	* sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
	IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
	* sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
	IMM0_8U case.

gas	* config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to
	IMM0_8S and add support for IMM0_8U.
	* testsuite/gas/sh/sh4a.s: Add test of a logical insn using an
	unsigned 8-bit immediate.
	* testsuite/gas/sh/sh4a.d: Extended expected disassembly.
2020-04-29 13:13:55 +01:00
Andreas Schwab
bb2a145347 Disallow PC relative for CMPI on MC68000/10
The MC68000/10 decodes the second operand of CMPI strictly as destination
operand, which disallows PC relative addressing, even though the insn
doesn't write to the operand.  This restriction has only been lifted for
the MC68020+ and CPU32.

opcodes:
	PR 25848
	* m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
	cmpi only on m68020up and cpu32.

gas:
	PR 25848
	* testsuite/gas/m68k/operands.s: Add tests for cmpi.
	* testsuite/gas/m68k/operands.d: Update.
	* testsuite/gas/m68k/op68000.d: Update for new error messages.
2020-04-21 16:53:36 +02:00
Sudakshina Das
c2e5c986b3 [AArch64, Binutils] Add missing TSB instruction
This patch implements the TSB instructions:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
tsb-csync-trace-synchronization-barrier
Since TSB and PSB both use the same (and only) argument "CSYNC", this patch
reuses it for TSB. However, the same argument would imply different value
for CRm:Op2 which are anyway fixed values, so I have diverted the
inserter/extracter function to dummy versions instead of the "hint" version.
The operand checker part still uses the existing infratructure for
AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly.

gas/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_barrier_psb): Update error messages
	to include TSB.
	* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
	* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
	* testsuite/gas/aarch64/system.d: Update.

opcodes/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-asm.c (aarch64_ins_none): New.
	* aarch64-asm.h (ins_none): New declaration.
	* aarch64-dis.c (aarch64_ext_none): New.
	* aarch64-dis.h (ext_none): New declaration.
	* aarch64-opc.c (aarch64_print_operand): Update case for
	AARCH64_OPND_BARRIER_PSB.
	* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
	(AARCH64_OPERANDS): Update inserter/extracter for
	AARCH64_OPND_BARRIER_PSB to use new dummy functions.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
2020-04-20 10:58:16 +01:00
Sudakshina Das
8a6e1d1d7f [AArch64, Binutils] Make hint space instructions valid for Armv8-a
There are a few instruction in AArch64 that are in the HINT space. Any of
these instructions should be accepted by the assembler/disassembler at any
architecture version. This patch fixes the existing instructions that are
not behaving accordingly.
I have used all of the instructions mentioned in the following to make the
changes:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
hint-hint-instruction

gas/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/bti.d: Update -march option.
	* testsuite/gas/aarch64/illegal-bti.d: Remove.
	* testsuite/gas/aarch64/illegal-bti.l: Remove.
	* testsuite/gas/aarch64/illegal-ras-1.l: Remove esb.
	* testsuite/gas/aarch64/illegal-ras-1.s: Remove esb.

opcodes/ChangeLog:

2020-04-20  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
	(aarch64_feature_ras, RAS): Likewise.
	(aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
	(aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
	autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
	autiaz, autiasp, autibz, autibsp to be CORE_INSN.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
2020-04-20 10:50:52 +01:00
Fredrik Strupe
e409955ddc [PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs.
VDUP (neon) instructions can be conditional, but this is not taken into
account in the current master. This commit fixes that by i) fixing the
VDUP instruction masks and ii) adding logic for disassembling
conditional neon instructions.

opcodes	* arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
	(print_insn_neon): Support disassembly of conditional
	instructions.

binutils* testsuite/binutils-all/arm/vdup-cond.d: New test for testing that
	conditional VDUP instructions are disassembled correctly.
	* testsuite/binutils-all/arm/vdup-cond.s: New file used by
	vdup-cond.d.
	* testsuite/binutils-all/arm/vdup-thumb.d: New test for testing
	that VDUP instructions (which are conditional in A32) can be
	disassembled in thumb mode.
	* testsuite/binutils-all/arm/vdup-cond.s: New file used by
	vdup-thumb.d.
2020-04-17 17:25:19 +01:00
David Faust
c54a9b5669 cpu,gas,opcodes: support for eBPF JMP32 instruction class
Add support for the JMP32 class of eBPF instructions.

cpu/ChangeLog

	* bpf.cpu (define-cond-jump-insn): Renamed from djci.
	(dcji) New version with support for JMP32

gas/ChangeLog

	* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
	* testsuite/gas/bpf/jump32.s: New file.
	* testsuite/gas/bpf/jump32.d: Likewise.

opcodes/ChangeLog

	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Regenerate.
	* bpf-opc.h: Likewise.
2020-04-16 09:52:57 +02:00
Cui,Lili
bb651e8b7f Add support for intel TSXLDTRK instructions$
gas/

	* config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document TSXLDTRK.
	* testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
	* testsuite/gas/i386/tsxldtrk.d: Likewise.
	* testsuite/gas/i386/tsxldtrk.s: Likewise.
	* testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.

opcodes/

	* i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
	(prefix_table): New instructions (see prefixes above).
	(rm_table): Likewise.
	* i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
	CPU_ANY_TSXLDTRK_FLAGS.
	(cpu_flags): Add CpuTSXLDTRK.
	* i386-opc.h (enum): Add CpuTSXLDTRK.
	(i386_cpu_flags): Add cputsxldtrk.
	* i386-opc.tbl: Add XSUSPLDTRK insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-04-07 13:59:50 +08:00
LiliCui
4b27d27c07 Add support for intel SERIALIZE instruction
gas/

	* config/tc-i386.c (cpu_arch): Add .serialize.
	(cpu_noarch): Likewise.
	* doc/c-i386.texi: Document serialize.
	* testsuite/gas/i386/i386.exp: Run serialize tests
	* testsuite/gas/i386/serialize.d: Likewise.
	* testsuite/gas/i386/x86-64-serialize.d: Likewise.
	* testsuite/gas/i386/serialize.s: Likewise.

opcodes/

	* i386-dis.c (prefix_table): New instructions serialize.
	* i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
	CPU_ANY_SERIALIZE_FLAGS.
	(cpu_flags): Add CpuSERIALIZE.
	* i386-opc.h (enum): Add CpuSERIALIZE.
	(i386_cpu_flags): Add cpuserialize.
	* i386-opc.tbl: Add SERIALIZE insns.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Likewise.
2020-04-02 05:48:36 -07:00
Alan Modra
832a580781 Re: H8300 use of uninitialised value
This patch also had some problems.  Calculation of maxlen was wrong,
and the insn arg loop needed rearranging to work with a correct length.

	* disassemble.h (opcodes_assert): Declare.
	(OPCODES_ASSERT): Define.
	* disassemble.c: Don't include assert.h.  Include opintl.h.
	(opcodes_assert): New function.
	* h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
	(bfd_h8_disassemble): Reduce size of data array.  Correctly
	calculate maxlen.  Omit insn decoding when insn length exceeds
	maxlen.  Exit from nibble loop when looking for E, before
	accessing next data byte.  Move processing of E outside loop.
	Replace tests of maxlen in loop with assertions.
2020-03-26 20:02:42 +10:30
Alan Modra
4c4addbe57 Re: ARC: Use of uninitialised value
git commit beea5cc1bc fixed one use of an uninitialised value but
ignored another one a few lines later.

	* arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
2020-03-26 20:02:42 +10:30
Alan Modra
a18cd0cab4 Uninitialised memory read in z80-dis.c
objdump -d -m ez80-adl testcase:
 .byte 0x40,0xfd

	* z80-dis.c (suffix): Init mybuf.
2020-03-25 08:54:18 +10:30
Alan Modra
57cb32b3c3 H8300 use of uninitialised value
* h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
	successflly read from section.
2020-03-22 23:22:13 +10:30
Alan Modra
beea5cc1bc ARC: Use of uninitialised value
* arc-dis.c (find_format): Use ISO C string concatenation rather
	than line continuation within a string.  Don't access needs_limm
	before testing opcode != NULL.
2020-03-22 23:22:13 +10:30
Alan Modra
03704c7704 NS32K arg_bufs uninitialised
git commit d1e304bc27 was aimed at stopping uninitialised memory
access to the index_offset array.  Unfortunately that patch resulted
in a different array being uninitialised for all instructions with
more than two arguments.

	* ns32k-dis.c (print_insn_arg): Update comment.
	(print_insn_ns32k): Reduce size of index_offset array, and
	initialize, passing -1 to print_insn_arg for args that are not
	an index.  Don't exit arg loop early.  Abort on bad arg number.
2020-03-22 23:22:13 +10:30
Alan Modra
d1023b5d1e s12z disassembler tidy
Don't ignore buffer memory read failure, or malloc failure.  Lots of
functions get a return status to pass these failures up the chain in
this patch.

opcodes/
	* s12z-dis.c (abstract_read_memory): Don't print error on EOI.
	* s12z-opc.c: Formatting.
	(operands_f): Return an int.
	(opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
	(opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
	(shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
	(exg_sex_discrim): Likewise.
	(create_immediate_operand, create_bitfield_operand),
	(create_register_operand_with_size, create_register_all_operand),
	(create_register_all16_operand, create_simple_memory_operand),
	(create_memory_operand, create_memory_auto_operand): Don't
	segfault on malloc failure.
	(z_ext24_decode): Return an int status, negative on fail, zero
	on success.
	(x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
	(imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
	(z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
	(decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
	(ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
	(mov_imm_opr, ld_18bit_decode, exg_sex_decode),
	(loop_primitive_decode, shift_decode, psh_pul_decode),
	(bit_field_decode): Similarly.
	(z_decode_signed_value, decode_signed_value): Similarly.  Add arg
	to return value, update callers.
	(x_opr_decode_with_size): Check all reads, returning NULL on fail.
	Don't segfault on NULL operand.
	(decode_operation): Return OP_INVALID on first fail.
	(decode_s12z): Check all reads, returning -1 on fail.
gas/
	* testsuite/gas/s12z/truncated.d: Update expected output.
2020-03-22 23:20:15 +10:30
Alan Modra
340f3ac808 metag uninitialized memory read
* metag-dis.c (print_insn_metag): Don't ignore status from
	read_memory_func.
2020-03-20 12:35:51 +10:30
Alan Modra
fe90ae8a9f NDS32 disassembly of odd sized sections
* nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
	Initialize parts of buffer not written when handling a possible
	2-byte insn at end of section.  Don't attempt decoding of such
	an insn by the 4-byte machinery.
2020-03-20 12:35:51 +10:30
Alan Modra
833d919c93 PowerPC disassembly of odd sized sections
We shouldn't really decode a 2-byte left-over at the end of a section
as if the section contains two more bytes of zeros.  Not that it
matters very much, but this patch tidies the corner case.

	* ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
	partially filled buffer.  Prevent lookup of 4-byte insns when
	only VLE 2-byte insns are possible due to section size.  Print
	".word" rather than ".long" for 2-byte leftovers.
2020-03-20 12:35:51 +10:30
Nick Clifton
327ef784ba Replace a couple of assertions in the BFD library that can be triggered by attempts to parse corrupt input files.
PR 25633
	* elf.c (_bfd_elf_copy_special_section_fields): Replace assertions
	with error messages.
2020-03-17 17:02:15 +00:00
Sergey Belyashov
68e52bc7ec Fix a small set of Z80 problems.
PR 25641
	PR 25668
	PR 25633
gas	Fix disassembling ED+A4/AC/B4/BC opcodes.
	Fix assembling lines containing colonless label and instruction
	with first operand inside parentheses.
	Fix registration of unsupported by target CPU registers.
	* config/tc-z80.c: See above.
	* config/tc-z80.h: See above.
	* testsuite/gas/z80/colonless.d: Update test.
	* testsuite/gas/z80/colonless.s: Likewise.
	* testsuite/gas/z80/ez80_adl_all.d: Likewise.
	* testsuite/gas/z80/ez80_unsup_regs.d: Likewise.
	* testsuite/gas/z80/ez80_z80_all.d: Likewise.
	* testsuite/gas/z80/gbz80_unsup_regs.d: Likewise.
	* testsuite/gas/z80/r800_unsup_regs.d: Likewise.
	* testsuite/gas/z80/unsup_regs.s: Likewise.
	* testsuite/gas/z80/z180_unsup_regs.d: Likewise.
	* testsuite/gas/z80/z80.exp: Likewise.
	* testsuite/gas/z80/z80_strict_unsup_regs.d: Likewise.
	* testsuite/gas/z80/z80_unsup_regs.d: Likewise.
	* testsuite/gas/z80/z80n_unsup_regs.d: Likewise.

opcodes	* z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2020-03-17 16:55:32 +00:00
Jan Beulich
1673df3278 x86-64: correct mis-named X86_64_0D enumerator
This is for major opcode 0E, so name it accordingly.
2020-03-13 09:57:10 +01:00
H.J. Lu
384f368958 x86: Also pass -P to $(CPP) when processing i386-opc.tbl
Since i386-opc.tbl contains '\' to avoid very long lines and i386-gen
requires that each instruction must be in one line, also pass -P to
$(CPP) to inhibit generation of linemarkers in the output from the
preprocessor to support i386-gen.

	* Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
	* Makefile.in: Regenerated.
2020-03-09 08:23:46 -07:00
Jan Beulich
865e20278c x86: use template for AVX512 integer comparison insns
These all follow a common pattern.
2020-03-09 10:14:55 +01:00
Jan Beulich
2f13234bc5 x86: use template for XOP integer comparison, shift, and rotate insns
These all follow common patterns.
2020-03-09 10:14:17 +01:00
Jan Beulich
3fabc17903 x86: use template for AVX/AVX512 floating point comparison insns
These all follow an almost common pattern, again with the exception of
being commutative, which can be easily taken care of.

Note that, as an intended side effect (and in fact one of the reason to
introduce templates), AVX long-form pseudo-ops get introduced alongside
the already existing AVX512 ones.
2020-03-09 10:13:43 +01:00
Jan Beulich
3677e4c174 x86: use template for SSE floating point comparison insns
These all follow an almost common pattern, with the exception of being
commutative. This exception can be easily taken care of.
2020-03-09 10:13:04 +01:00
Jan Beulich
4c4898e8f5 x86: allow opcode templates to be templated
In order to reduce redundancy as well as the chance of things going out
of sync (see a later patch for an example), make the opcode table
generator capable of recognizing and expanding templated templates. Use
the new capability for compacting the general purpose conditional insns.
2020-03-09 10:12:14 +01:00
Jan Beulich
bc49bfd849 x86: reduce amount of various VCVT* templates
Presumably as a result of various changes over the last several months,
and - for some of them - with a generalization of logic in
match_mem_size() plus mirroring of this generalization into the
broadcast handling logic of check_VecOperands(), various register-only
templates can be foled into their respective memory forms. This in
particular then also allows dropping a few more instances of IgnoreSize.
2020-03-06 08:56:47 +01:00
Jan Beulich
4873e2438c x86: drop/replace IgnoreSize
Even after commit dc2be329b9 ("i386: Only check suffix in instruction
mnemonic"), by which many of its uses have become unnecessary (some were
unnecessary even before), IgnoreSize is still used for various slightly
different purposes:
- to suppress emission of an operand size prefix,
- in Intel syntax mode to zap "derived" suffixes in certain cases and to
  skip certain checks of remaining "derived" suffixes,
- to suppress ambiguous operand size / missing suffix diagnostics,
- for prefixes to suppress the "stand-alone ... prefix" warning.
Drop entirely unnecessary ones and where possible also replace instances
by the more focused (because of having just a single purpose) NoRex64.

To further restrict when IgnoreSize is needed, also generalize the logic
when to skip a template because of a present or derived L or Q suffix,
by skipping immediate operands. Additionally consider mask registers and
VecSIB there.

Note that for the time being the attribute needs to be kept in place on
MMX/SSE/etc insns (but not on VEX/EVEX encoded ones unless an operand
template of them allows for only non-SIMD-register actuals) allowing for
Dword operands - the logic when to emit a data size prefix would need
further adjustment first.

Note also that the memory forms of {,v}pinsrw get their permission for
an L or Q suffix dropped. I can only assume that it being this way was a
cut-and-paste mistake from the register forms, as the latter
specifically have NoRex64 set, and the {,v}pextrw counterparts don't
allow these suffixes either.

Convert VexW= again to their respective VexW* on lines touched anyway.
2020-03-06 08:55:52 +01:00
Jan Beulich
672a349b01 x86: don't accept FI{LD,STP,STTP}LL in Intel syntax mode
As of commit dc2be329b9 ("i386: Only check suffix in instruction
mnemonic") these have been accepted even with "qword ptr" operand size
specifier, but in 64-bit mode they're now wrongly having a REX prefix
(with REX.W set) emitted in this case. These aren't Intel syntax
mnemonics, so rather than fixing code generation, let's simply reject
them. As a result, the Qword attribute can then be dropped, too.
2020-03-06 08:53:56 +01:00
Jan Beulich
4ed21b58d4 x86: replace NoRex64 on VEX-encoded insns
When the template specifies any of the possible VexW settings, we can
use this instead of a separate NoRex64 to suppress the setting of REX_W.
Note that this ends up addressing an inconsistency between VEX- and
EVEX-encoded VEXTRACTPS, VPEXTR{B,W}, and VPINSR{B,W} - while the former
avoided setting VEX.W, the latter pointlessly set EVEX.W when there is a
64-bit GPR operand. Adjust the testcase to cover both cases.

Convert VexW= to their respective VexW* on lines touched anyway.
2020-03-06 08:53:18 +01:00
Jan Beulich
643bb87079 x86: drop Rex64 attribute
It is almost entirely redundant with Size64, and the sole case (CRC32)
where direct replacement isn't possible can easily be taken care of in
another way.
2020-03-06 08:52:12 +01:00
Jan Beulich
a23b33b3d1 x86: correct MPX insn w/o base or index encoding in 16-bit mode
Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16
fails to match the templates.

The SDM leaves open whether BNDC[LNU] with a GPR operand require an
operand size override; this aspect is therefore left untouched here.
2020-03-06 08:50:56 +01:00
Jan Beulich
a04973848d x86: add missing IgnoreSize
For proper code generation in 16-bit mode (or to avoid the "same type of
prefix used twice" diagnostic there), IgnoreSize is needed on certain
templates allowing for just 32-(and maybe 64-)bit operands.

Beyond adding tests for the previously broken cases, also add ones for
the previously working cases where IgnoreSize is needed for the same
reason (leaving out MPX for now, as that'll require an assembler change
first). Some minor adjustments to tests get done such that re-use of the
same code for 16-bit code generation testing becomes easier.
2020-03-06 08:49:45 +01:00
Jan Beulich
b630c145c0 x86: refine TPAUSE and UMWAIT
Allowing 64-bit registers is misleading here: Elsewhere these get allowed
when there's no difference between either variant, because of 32-bit
destination registers having their upper halves zeroed in 64-bit mode.
Here, however, they're source registers, and hence specifying 64-bit
registers would lead to the ambiguity of whether the upper 32 bits
actually matter.

Additionally, for proper code generation in 16-bit mode, IgnoreSize is
needed on both.

And finally, just like for e.g. MONITOR/MWAIT, add variants with all
input registers explicitly specified.
2020-03-06 08:48:48 +01:00
Jan Beulich
a847e32224 x86: support VMGEXIT
It has been publicly documented for quite some time, albeit not in the
"General-Purpose and System Instructions" volume:
https://www.amd.com/system/files/TechDocs/24593.pdf.
2020-03-04 08:58:13 +01:00
H.J. Lu
3cd7f3e3bd x86: Replace IgnoreSize/DefaultSize with MnemonicSize
Since an instruction template can't have both IgnoreSize and DefaultSize,
this patch replaces IgnoreSize and DefaultSize with MnemonicSize.

gas/

	* config/tc-i386.c (match_template): Replace ignoresize and
	defaultsize with mnemonicsize.
	(process_suffix): Likewise.

opcodes/

	* i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
	with MnemonicSize.
	* i386-opc.h (IGNORESIZE): New.
	(DEFAULTSIZE): Likewise.
	(IgnoreSize): Removed.
	(DefaultSize): Likewise.
	(MnemonicSize): New.
	(i386_opcode_modifier): Replace ignoresize/defaultsize with
	mnemonicsize.
	* i386-opc.tbl (IgnoreSize): New.
	(DefaultSize): Likewise.
	* i386-tbl.h: Regenerated.
2020-03-03 11:24:26 -08:00
Sergey Belyashov
b8ba138563 The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble of this and LD (HL),IX instruction. Also it update testsuit.
PR 25627
opcodes	* z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
	instructions.

gas	* config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of
	instruction LD IY,(HL).
	* testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly.
	* testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction.
	* testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly.
	* testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
2020-03-03 16:32:52 +00:00
H.J. Lu
10d97a0f99 x86: Allow integer conversion without suffix in AT&T syntax
According to gas manual, suffix in instruction mnemonics isn't always
required:

When there is no sizing suffix and no (suitable) register operands to
deduce the size of memory operands, with a few exceptions and where long
operand size is possible in the first place, operand size will default
to long in 32- and 64-bit modes.

This includes cvtsi2sd, cvtsi2ss, vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and
vcvtusi2ss.  Since they are used in GCC 8 and older GCC releases, they
must be allowed without suffix in AT&T syntax.

gas/

	PR gas/25622
	* testsuite/gas/i386/i386.exp: Run x86-64-default-suffix and
	x86-64-default-suffix-avx.
	* testsuite/gas/i386/noreg64.s: Remove cvtsi2sd, cvtsi2ss,
	vcvtsi2sd, vcvtsi2ss, vcvtusi2sd and vcvtusi2ss entries.
	* testsuite/gas/i386/noreg64.d: Updated.
	* testsuite/gas/i386/noreg64.l: Likewise.
	* testsuite/gas/i386/x86-64-default-suffix-avx.d: New file.
	* testsuite/gas/i386/x86-64-default-suffix.d: Likewise.
	* testsuite/gas/i386/x86-64-default-suffix.s: Likewise.

opcodes/

	PR gas/25622
	* i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
	vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
	* i386-tbl.h: Regenerated.
2020-03-03 07:39:35 -08:00
Alan Modra
dc1e8a474f Indent labels
Labels don't go in the first column according to standard emacs C
indent rules, and I got annoyed enough at seeing diff -p show a label
rather than the function name to fix this.

bfd/
	* aoutx.h: Indent labels correctly.  Format error strings.
	* archive.c: Likewise.
	* archive64.c: Likewise.
	* coff-arm.c: Likewise.
	* coff-rs6000.c: Likewise.
	* coff-stgo32.c: Likewise.
	* cpu-arm.c: Likewise.
	* dwarf2.c: Likewise.
	* elf-ifunc.c: Likewise.
	* elf-properties.c: Likewise.
	* elf-s390-common.c: Likewise.
	* elf-strtab.c: Likewise.
	* elf.c: Likewise.
	* elf32-arm.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-cr16.c: Likewise.
	* elf32-csky.c: Likewise.
	* elf32-i386.c: Likewise.
	* elf32-m68k.c: Likewise.
	* elf32-msp430.c: Likewise.
	* elf32-nds32.c: Likewise.
	* elf32-nios2.c: Likewise.
	* elf32-pru.c: Likewise.
	* elf32-xtensa.c: Likewise.
	* elf64-ia64-vms.c: Likewise.
	* elf64-x86-64.c: Likewise.
	* elfcode.h: Likewise.
	* elfcore.h: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-ia64.c: Likewise.
	* elfnn-riscv.c: Likewise.
	* elfxx-mips.c: Likewise.
	* elfxx-sparc.c: Likewise.
	* elfxx-x86.c: Likewise.
	* i386lynx.c: Likewise.
	* merge.c: Likewise.
	* pdp11.c: Likewise.
	* plugin.c: Likewise.
	* reloc.c: Likewise.
binutils/
	* elfedit.c: Indent labels correctly.
	* readelf.c: Likewise.
	* resres.c: Likewise.
gas/
	* config/obj-elf.c: Indent labels correctly.
	* config/obj-macho.c: Likewise.
	* config/tc-aarch64.c: Likewise.
	* config/tc-alpha.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-crx.c: Likewise.
	* config/tc-frv.c: Likewise.
	* config/tc-i386-intel.c: Likewise.
	* config/tc-i386.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-mn10200.c: Likewise.
	* config/tc-mn10300.c: Likewise.
	* config/tc-nds32.c: Likewise.
	* config/tc-riscv.c: Likewise.
	* config/tc-s12z.c: Likewise.
	* config/tc-xtensa.c: Likewise.
	* config/tc-z80.c: Likewise.
	* read.c: Likewise.
	* symbols.c: Likewise.
	* write.c: Likewise.
ld/
	* emultempl/cskyelf.em: Indent labels correctly.
	* ldfile.c: Likewise.
	* ldlang.c: Likewise.
	* plugin.c: Likewise.
opcodes/
	* aarch64-asm.c: Indent labels correctly.
	* aarch64-dis.c: Likewise.
	* aarch64-gen.c: Likewise.
	* aarch64-opc.c: Likewise.
	* alpha-dis.c: Likewise.
	* i386-dis.c: Likewise.
	* nds32-asm.c: Likewise.
	* nfp-dis.c: Likewise.
	* visium-dis.c: Likewise.
2020-02-26 10:37:25 +10:30
Claudiu Zissulescu
265b467340 [ARC][committed] Update int_vector_base aux register.
INT_VECTOR_BASE auxiliary register is available across all ARC
architectures.

xxxx-xx-xx  Claudiu Zissulescu <claziss@gmail.com>

	* arc-regs.h (int_vector_base): Make it available for all ARC
	CPUs.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
2020-02-25 10:27:07 +02:00
Nelson Chu
bd0cf5a6ba RISC-V: Support the ISA-dependent CSR checking.
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set.  We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information.  We report warning message when the CSR is
invalid, so we have a choice between error and warning by --fatal-warnings
option.  Also, a --no-warn/-W option is used to turn the warnings off, if
people don't want the warnings.

	gas/
	* config/tc-riscv.c (enum riscv_csr_class): New enum.  Used to decide
	whether or not this CSR is legal in the current ISA string.
	(struct riscv_csr_extra): New structure to hold all extra information
	of CSR.
	(riscv_init_csr_hash): New function.  According to the DECLARE_CSR and
	DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
	Call hash_reg_name to insert CSR address into reg_names_hash.
	(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
	(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
	Decide whether the CSR is valid according to the csr_extra_hash.
	(init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is
	not a boolean.  This is same as riscv_init_csr_hash, so keep the
	consistent usage.

	* testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option.
	* testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option.
	* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase.  The source
	file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the
	f-ext CSR are not allowed.
	* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase.  The
	source file is `priv-reg.s`, and the ISA is rv64if, so the
	rv32-only CSR are not allowed.
	* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.

	include/
	* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
	record riscv_csr_class.

	opcodes/
	* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.

	gdb/
	* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
	* riscv-tdep.h: Likewise.
	* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
	rv32-only CSR.
	* features/riscv/64bit-csr.xml: Regernated.

	binutils/
	* dwarf.c: Updated since the DECLARE_CSR is changed.
2020-02-20 16:49:09 -08:00
Jim Wilson
fa16423949 RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.
2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
	gas/
	* testsuite/gas/riscv/c-add-addi.d: New testcase.
	* testsuite/gas/riscv/c-add-addi.s: Likewise.
	opcodes/
	* riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
	c.mv/c.li if rs1 is zero.

Change-Id: Id939b5e6db80d267a832545f3ffef7b9ba881f7d
2020-02-19 14:51:07 -08:00
H.J. Lu
272a84b120 x86: Remove CpuABM and add CpuPOPCNT
AMD ABM has 2 instructions: popcnt and lzcnt.  ABM CPUID feature bit has
been reused for lzcnt and a POPCNT CPUID feature bit is added for popcnt
which used to be the part of SSE4.2.  This patch removes CpuABM and adds
CpuPOPCNT.  It changes ABM to enable both lzcnt and popcnt, changes SSE4.2
to also enable popcnt.

gas/

	* config/tc-i386.c (cpu_arch): Add .popcnt.
	* doc/c-i386.texi: Remove abm and .abm.  Add popcnt and .popcnt.
	Add a tab before @samp{.sse4a}.

opcodes/

	* i386-gen.c (cpu_flag_init): Replace CpuABM with
	CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
	CPU_POPCNT_FLAGS.
	(cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
	* i386-opc.h (CpuABM): Removed.
	(CpuPOPCNT): New.
	(i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
	* i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
	popcnt.  Remove CpuABM from lzcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2020-02-17 07:31:28 -08:00
Jan Beulich
1f730c4614 x86: fold certain VCVT{,U}SI2S{S,D} templates
There don't really need to be separate Cpu64 and CpuNo64 templates for
these. One small issue with this is that slightly strange code

	.intel_syntax noprefix
	.code16
	.arch i286
	.arch .avx
	vcvtsi2sd xmm0, xmm0, dword ptr [bx]
	vcvtsi2sd xmm0, xmm0, qword ptr [bx]

	vcvtsi2sd xmm0, xmm0, ebx
	vcvtsi2sd xmm0, xmm0, rbx

now will match in behavior with the AVX512 counterparts in that not
only the 2nd vcvtsi2sd won't assemble, but also the first. The last
two, otoh, will continue to assemble fine (due to the lack of any
memory operand size specifier). As a result, another way to make
things behave more consistently would be to avoid the folding and
add IgnoreSize to the CpuNo64 AVX512 variants. A 3rd way to do so
would be to add Cpu386 to any such insn template.

While doing this also make the usual cosmetic adjustments for the
insns touched anyway. Additionally drop the redundant Cpu64 from
the SAE forms of VCVT{,U}SI2SD - they won't assemble outside of
64-bit mode due to there not being anything to match the Reg64
operand.
2020-02-17 08:59:52 +01:00
Jan Beulich
c8f8eebc3f x86: fold AddrPrefixOpReg templates
There's no need to have separate Cpu64 and CpuNo64 templates: There
already is special logic handling the attribute, and all that's needed
is rejecting 16-bit address registers in 64-bit mode. Suppress suffix
guessing and group all involved logic together, outside of suffix
processing (arguably it doesn't even belong in process_suffix()).

Also, since no AddrPrefixOpReg template permits any suffixes, move the
No_*Suf specifiers for them to a central place. Along with this drop
the no longer relevant NoRex64 from there.
2020-02-17 08:59:07 +01:00
Jan Beulich
b9915cbc7d x86/Intel: improve diagnostics for ambiguous VCVT* operands
Conversions which shrink element size and which have a memory source
can't be disambiguated between their 128- and 256-bit variants by
looking at the register operand. "operand size mismatch", however, is a
pretty misleading diagnostic. Generalize the logic introduced for
VFPCLASSP{S,D} such that, with suitable similar adjustments to the
respective templates, it'll cover these cases too.

For VCVTNEPS2BF16 also fold the two previously separate AVX512VL
templates to achieve the intended effect. This is then also accompanied
by a respective addition to the inval-avx512f testcase.
2020-02-17 08:56:18 +01:00
H.J. Lu
ce504911e5 x86: Don't disable SSE3 when disabling SSE4a
Since SSE3 is independent of SSE4a, don't disable SSE3 when disabling
SSE4a.

	* i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
	CPU_ANY_SSE4A_FLAGS.
2020-02-16 20:10:20 -08:00
Alan Modra
dabec65da1 Re: x86: Don't disable SSE4a when disabling SSE4
* i386-gen.c (cpu_flag_init): Correct last change.
2020-02-17 13:14:00 +10:30
H.J. Lu
af5c13b01e x86: Don't disable SSE4a when disabling SSE4
commit 7deea9aad8 changed nosse4 to include CpuSSE4a.  But AMD SSE4a is
a superset of SSE3 and Intel SSE4 is a superset of SSSE3.  Disable Intel
SSE4 shouldn't disable AMD SSE4a.  This patch restores nosse4.  It also
adds .sse4a and nosse4a.

gas/

	* config/tc-i386.c (cpu_arch): Add .sse4a and nosse4a.  Restore
	nosse4.
	* doc/c-i386.texi: Document sse4a and nosse4a.

opcodes/

	* i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
	CPU_ANY_SSE4_FLAGS.
2020-02-16 08:45:34 -08:00
H.J. Lu
6867aac05b Remove Intel syntax comments on movsx and movzx
Since movsx and movzx are valid mnemonic in AT&T syntax, remove Intel
syntax comments on movsx and movzx to avoid confusing other readers.

	* i386-opc.tbl (movsx): Remove Intel syntax comments.
	(movzx): Likewise.
2020-02-14 05:45:14 -08:00
Jan Beulich
65fca0597f x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX
For these to get treatment consistent with other operand size checking
the special logic shouldn't live in md_assemble(), but process_suffix().
And there's more logic involved than simply zapping the suffix.

Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully
consistent, due to the objection to fold MOVS* templates just like was
done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit
movzb").

Note further that it is against my own intentions to have MOVSX/MOVZX
silently default to a byte source in AT&T mode. This should happen only
when the destination register is a 16-bit one. In all other cases there
is an ambiguity, and the user should be warned. But it was explicitly
requested for this to be done in a way inconsistent with everything
else.

Note finally that the assembler change points out (and this patch fixes)
a wrong Intel syntax test introduced by bc31405ebb ("x86-64: Properly
encode and decode movsxd"): When source code specifies a 16-bit
destination register, disassembly expectations shouldn't have been to
find a 32-bit one.
2020-02-14 14:27:28 +01:00
Jan Beulich
7deea9aad8 x86: fix SSE4a dependencies of ".arch .nosse*"
Since ".arch .sse4a" enables SSE3 and earlier, disabling SSE3 should
also disable SSE4a. And as per its name, ".arch .nosse4" should also do
so.
2020-02-13 10:19:28 +01:00
Jan Beulich
6c0946d0d2 x86: correct VFPCLASSP{S,D} operand size handling
With AVX512VL disabled (e.g. when writing code for the Knights family
of processors) these insns aren't ambiguous when used with a memory
source, and hence should be accepted without suffix or operand size
specifier. When AVX512VL is enabled, to be consistent with this as
well as other ambiguous operand size handling it would seem better to
just warn about the ambiguity in AT&T mode, and still default to 512-bit
operands (on the assumption that the code may have been written without
AVX512VL in mind yet), but it was requested to leave AT&T syntax mode
alone here.
2020-02-12 16:20:56 +01:00
Jan Beulich
ddb56fe600 x86: fold two JMP templates
Now that the AMD64 check in match_template() applies to 64-bit code
only, the non-64-bit and the Amd64 template can be folded, as being
otherwise compatible with one another. (Oddly enough the same doesn't
apply to CALL, due to the suffixes it permits, while JMP doesn't
allow for any.)
2020-02-12 16:19:52 +01:00
Jan Beulich
5990e377e5 x86-64: Intel64 adjustments for insns dealing with far pointers
AMD and Intel differ in their handling of far indirect branches as well
as LFS/LGS/LSS: AMD CPUs ignore REX.W while Intel ones honors it. (Note
how the latter three were hybrids so far, while far branches were fully
AMD-like.)
2020-02-12 16:19:03 +01:00
Jan Beulich
50128d0cab x86: drop ShortForm attribute
It is very simple to derive from other template properties, and hence
there's little point wasting storage for it.
2020-02-11 11:20:55 +01:00
Jan Beulich
1e05b5c489 x86: drop stray ShortForm attributes
This attribute is meaningless when there are no operands to encode.
2020-02-11 11:20:05 +01:00
Alan Modra
2f5dd314d6 Ensure *valuep always written by extract_normal return
* cgen-ibld.in (extract_normal): Set *valuep on all return paths.
	* bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
	* ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
	* m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
	* xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2020-02-11 12:14:01 +10:30
Matthew Malcomson
5aae9ae97f [binutils][arm] Implement Custom Datapath Extensions for MVE
Here we implement the custom datapath extensions for MVE.

This required the following changes:

- Adding a new register argument type (that takes either an MVE vector or
  a Neon S or D register).
- Adding two new immediate operands types (0-127 and 0-4095).
- Using the Neon type machinery to distinguish between instruction
  types.  This required the introduction of new neon shapes to account
  for the coprocessor operands to these instructions.
- Adding a new disassembly character to `print_insn_cde` to handle the
  new register types.

Specification can be found at
https://developer.arm.com/docs/ddi0607/latest

Successfully regression tested on arm-none-eabi, and arm-wince-pe.

gas/ChangeLog:

2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for
	instructions that can have 5 arguments.
	(enum operand_parse_code): Add new operands.
	(parse_operands): Account for new operands.
	(S5): New macro.
	(enum neon_shape_el): Introduce P suffixes for coprocessor.
	(neon_select_shape): Account for P suffix.
	(LOW1): Move macro to global position.
	(HI4): Move macro to global position.
	(vcx_assign_vec_d): New.
	(vcx_assign_vec_m): New.
	(vcx_assign_vec_n): New.
	(enum vcx_reg_type): New.
	(vcx_get_reg_type): New.
	(vcx_size_pos): New.
	(vcx_vec_pos): New.
	(vcx_handle_shape): New.
	(vcx_ensure_register_in_range): New.
	(vcx_handle_register_arguments): New.
	(vcx_handle_insn_block): New.
	(vcx_handle_common_checks): New.
	(do_vcx1): New.
	(do_vcx2): New.
	(do_vcx3): New.
	* testsuite/gas/arm/cde-missing-fp.d: New test.
	* testsuite/gas/arm/cde-missing-fp.l: New test.
	* testsuite/gas/arm/cde-missing-mve.d: New test.
	* testsuite/gas/arm/cde-missing-mve.l: New test.
	* testsuite/gas/arm/cde-mve-or-neon.d: New test.
	* testsuite/gas/arm/cde-mve-or-neon.s: New test.
	* testsuite/gas/arm/cde-mve.s: New test.
	* testsuite/gas/arm/cde-warnings.l:
	* testsuite/gas/arm/cde-warnings.s:
	* testsuite/gas/arm/cde.d:
	* testsuite/gas/arm/cde.s:

opcodes/ChangeLog:

2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (print_insn_cde): Define 'V' parse character.
	(cde_opcodes): Add VCX* instructions.
2020-02-10 16:50:14 +00:00
Matthew Malcomson
4934a27c8c [binutils][arm] arm support for ARMv8.m Custom Datapath Extension
This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.

This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.

The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.

Specification can be found at
https://developer.arm.com/docs/ddi0607/latest

This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags.  This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.

We introduce a new IT block state to indicate the behaviour of these
instructions.  This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them.  Hence
we need to mark an instruction as allowed in either position.

We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.

Successfully regression tested on arm-none-eabi, and arm-wince-pe.

gas/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (arm_ext_cde*): New feature sets for each
	CDE coprocessor that can be enabled.
	(enum pred_instruction_type): New pred type.
	(BAD_NO_VPT): New error message.
	(BAD_CDE): New error message.
	(BAD_CDE_COPROC): New error message.
	(enum operand_parse_code): Add new immediate operands.
	(parse_operands): Account for new immediate operands.
	(check_cde_operand): New.
	(cde_coproc_enabled): New.
	(cde_coproc_pos): New.
	(cde_handle_coproc): New.
	(cxn_handle_predication): New.
	(do_custom_instruction_1): New.
	(do_custom_instruction_2): New.
	(do_custom_instruction_3): New.
	(do_cx1): New.
	(do_cx1a): New.
	(do_cx1d): New.
	(do_cx1da): New.
	(do_cx2): New.
	(do_cx2a): New.
	(do_cx2d): New.
	(do_cx2da): New.
	(do_cx3): New.
	(do_cx3a): New.
	(do_cx3d): New.
	(do_cx3da): New.
	(handle_pred_state): Define new IT block behaviour.
	(insns): Add newn CX*{,d}{,a} instructions.
	(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
	Define new cdecp extension strings.
	* doc/c-arm.texi: Document new cdecp extension arguments.
	* testsuite/gas/arm/cde-scalar.d: New test.
	* testsuite/gas/arm/cde-scalar.s: New test.
	* testsuite/gas/arm/cde-warnings.d: New test.
	* testsuite/gas/arm/cde-warnings.l: New test.
	* testsuite/gas/arm/cde-warnings.s: New test.
	* testsuite/gas/arm/cde.d: New test.
	* testsuite/gas/arm/cde.s: New test.

include/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
	(ARM_EXT2_CDE0): New extension macro.
	(ARM_EXT2_CDE1): New extension macro.
	(ARM_EXT2_CDE2): New extension macro.
	(ARM_EXT2_CDE3): New extension macro.
	(ARM_EXT2_CDE4): New extension macro.
	(ARM_EXT2_CDE5): New extension macro.
	(ARM_EXT2_CDE6): New extension macro.
	(ARM_EXT2_CDE7): New extension macro.

opcodes/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (struct cdeopcode32): New.
	(CDE_OPCODE): New macro.
	(cde_opcodes): New disassembly table.
	(regnames): New option to table.
	(cde_coprocs): New global variable.
	(print_insn_cde): New
	(print_insn_thumb32): Use print_insn_cde.
	(parse_arm_disassembler_options): Parse coprocN args.
2020-02-10 16:50:14 +00:00
H.J. Lu
4b5aaf5f69 x86: Accept Intel64 only instruction by default
Commit d835a58baa disabled sysenter/sysenter in 64-bit mode by
default.  By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.

gas/

	PR gas/25516
	* config/tc-i386.c (intel64): Renamed to ...
	(isa64): This.
	(match_template): Accept Intel64 only instruction by default.
	(i386_displacement): Updated.
	(md_parse_option): Updated.
	* c-i386.texi: Update -mamd64/-mintel64 documentation.
	* testsuite/gas/i386/i386.exp: Run x86-64-sysenter.  Pass
	-mamd64 to x86-64-sysenter-amd.
	* testsuite/gas/i386/x86-64-sysenter.d: New file.

opcodes/

	PR gas/25516
	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	with ISA64.
	* i386-opc.h (AMD64): Removed.
	(Intel64): Likewose.
	(AMD64): New.
	(INTEL64): Likewise.
	(INTEL64ONLY): Likewise.
	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	* i386-opc.tbl (Amd64): New.
	(Intel64): Likewise.
	(Intel64Only): Likewise.
	Replace AMD64 with Amd64.  Update sysenter/sysenter with
	Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
	* i386-tbl.h: Regenerated.
2020-02-10 08:37:36 -08:00
Sergey Belyashov
9fc0b501af Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add DWARF debug info support to the Z80 assembler.
PR 25469
bfd	* archures.c: Add GBZ80 and Z80N machine values.
	* reloc.c: Add BFD_RELOC_Z80_16_BE.
	* coff-z80.c: Add support for new reloc.
	* coffcode.h: Add support for new machine values.
	* cpu-z80.c: Add support for new machine names.
	* elf32-z80.c: Add support for new reloc.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

binutils* readelf.c (get_machine_flags): Add support for Z80N machine
	number.

gas	* config/tc-z80.c: Add -gbz80 command line option to generate code
	for the GameBoy Z80.  Add support for generating DWARF.
	* config/tc-z80.h: Add support for DWARF debug information
	generation.
	* doc/c-z80.texi: Document new command line option.
	* testsuite/gas/z80/gbz80_all.d: New file.
	* testsuite/gas/z80/gbz80_all.s: New file.
	* testsuite/gas/z80/z80.exp: Run the new tests.
	* testsuite/gas/z80/z80n_all.d: New file.
	* testsuite/gas/z80/z80n_all.s: New file.
	* testsuite/gas/z80/z80n_reloc.d: New file.

include	* coff/internal.h (R_IMM16BE): Define.
	* elf/z80.h (EF_Z80_MACH_Z80N): Define.
	(R_Z80_16_BE): New reloc.

ld	* emulparams/elf32z80.sh: Use z80 emulation.
	* emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations.
	* emultempl/z80elf.em: Delete.
	* testsuite/ld-elf/pr22450.d: Expect to fail for the Z80.
	* testsuite/ld-elf/sec64k.exp: Fix Z80 assembly.
	* testsuite/ld-unique/pr21529.s: Avoid register name conflict.
	* testsuite/ld-unique/unique.s: Likewise.
	* testsuite/ld-unique/unique_empty.s: Likewise.
	* testsuite/ld-unique/unique_shared.s: Likewise.
	* testsuite/ld-unique/unique.d: Updated expected output.
	* testsuite/ld-z80/arch_z80n.d: New file.
	* testsuite/ld-z80/comb_arch_z80_z80n.d: New file.
	* testsuite/ld-z80/labels.s: Add more labels.
	* testsuite/ld-z80/relocs.s: Add more reloc tests.
	* testsuite/ld-z80/relocs_f_z80n.d: New file

opcodes	* z80-dis.c: Add support for GBZ80 opcodes.
2020-02-07 14:53:46 +00:00
Alan Modra
c5d7be0c97 ubsan: d30v: negation of -2147483648
include/
	* opcode/d30v.h (struct pd_reg): Make value field unsigned.
opcodes/
	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2020-02-04 14:10:40 +10:30
Alan Modra
44e4546fa2 ubsan: m32c: left shift of negative value
cpu/
	* m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-02-03 15:59:08 +10:30
Alan Modra
b2b1453ad4 ubsan: frv: left shift of negative value
More non-bugs flagged by ubsan, unless you happen to be compiling for
a 1's complement host.

cpu/
	* frv.cpu (f-u12): Multiply rather than left shift signed values.
	(f-label16, f-label24): Likewise.
opcodes/
	* frv-ibld.c: Regenerate.
2020-02-01 23:23:18 +10:30
Jan Beulich
4102be5cf9 x86: replace EXxmm_mdq by EXVexWdqScalar
There's no need to have two operand specifiers / enumerators for the
same purpose. This then renders xmm_mdq_mode unused.
2020-01-31 14:29:18 +01:00
Jan Beulich
825bd36cea x86: drop unused EXVexWdq / vex_w_dq_mode 2020-01-31 14:28:43 +01:00
Richard Sandiford
c3036ed063 aarch64: Fix MOVPRFX markup for bf16 conversions
bfcvt converts a .S input to a .H output, so any predicated movprfx
needs to operate on .S rather than .H.  In common with SVE2 narrowing
top operations, bfcvtnt doesn't accept movprfx.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.

gas/
	* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
	.s for the movprfx.
	* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_28.d,
	* testsuite/gas/aarch64/sve-movprfx_28.l,
	* testsuite/gas/aarch64/sve-movprfx_28.s: New test.
2020-01-31 13:22:46 +00:00
Alan Modra
0c115f8483 ubsan: m32c: left shift of negative value
More nonsense fixing "bugs" with left shifts of signed values.  Yes,
the C standard does say this is undefined (and right shifts of signed
values are implementation defined BTW) but in practice there is no
problem with current machines.  1's complement is a thing of the past.

cpu/
	* m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
	(f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise.
	(f-dst32-rn-prefixed-QI): Likewise.
	(f-dsp-32-s32): Mask before shifting left.
	(f-dsp-48-u32, f-dsp-48-s32): Likewise.
	(f-bitbase32-16-s11-unprefixed): Multiply signed field rather than
	shifting left.
	(f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise.
	(h-gr-SI): Mask before shifting.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-01-30 23:39:55 +10:30
Jose E. Marchesi
bd434cc4d9 cpu,opcodes,gas: fix neg and neg32 instructions in BPF
This patch fixes the neg/neg32 BPF instructions, which have K (=0)
instead of X (=1) in their header source bit, despite operating on
registes.

cpu/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (define-alu-insn-un): The unary BPF instructions
	(neg and neg32) use OP_SRC_K even if they operate only in
	registers.

opcodes/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c: Regenerate.

gas/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Update expected opcode for `neg'.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise for `neg32'.
	* testsuite/gas/bpf/alu32-be.d: Likewise.
2020-01-30 13:59:04 +01:00
Jan Beulich
aeab2b26db x86-64: honor vendor specifics for near RET
While vendors agree about default operand size (64 bits) and hence
unavilability of a 32-bit form, AMD honors a 16-bit operand size
override (0x66) while Intel doesn't.
2020-01-30 11:36:33 +01:00
Jan Beulich
62b3f54810 x86: drop further pointless/bogus DefaultSize
- 64-bit CALL permitting just a single operand size doesn't need it.
- FLDENV et al should never have had it.

It remains suspicious that a number of 64-bit only insns continue to
have the attribute, despite this being intended for .code16gcc handling
only.
2020-01-30 11:33:53 +01:00
Alan Modra
1bd8ae1004 ubsan: tic4x: left shift cannot be represented in type 'int'
The patch also fixes a case where libopcodes built for a 64-bit
bfd_vma may print different results to libopcodes built for a 32-bit
bfd_vma.

	* tic4x-dis.c (tic4x_dp): Make unsigned.
2020-01-30 17:06:54 +10:30
H.J. Lu
bc31405ebb x86-64: Properly encode and decode movsxd
movsxd is a 64-bit only instruction.  It supports both 16-bit and 32-bit
destination registers.  Its AT&T mnemonic is movslq which only supports
64-bit destination register.  There is also a discrepancy between AMD64
and Intel64 on movsxd with 16-bit destination register.  AMD64 supports
32-bit source operand and Intel64 supports 16-bit source operand.

This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit
destination registers.  It also handles movsxd with 16-bit destination
register for AMD64 and Intel 64.

gas/

	PR binutils/25445
	* config/tc-i386.c (check_long_reg): Also convert to QWORD for
	movsxd.
	* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
	differences.  Document movslq and movsxd.
	* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
	* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
	* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd.s: Likewise.

opcodes/

	PR binutils/25445
	* i386-dis.c (MOVSXD_Fixup): New function.
	(movsxd_mode): New enum.
	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	(intel_operand_size): Handle movsxd_mode.
	(OP_E_register): Likewise.
	(OP_G): Likewise.
	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	register on movsxd.  Add movsxd with 16-bit destination register
	for AMD64 and Intel64 ISAs.
	* i386-tbl.h: Regenerated.
2020-01-27 04:38:29 -08:00
Tamar Christina
7568c93bf9 AArch64: Fix cfinv disassembly issues
This fixes the preferred disassembly for cfinv.  The Armv8.4-a instruction
overlaps with the possible encoding space for msr.  This because msr allows you
to use unallocated encoding space using the general sA_B_cC_cD_E form.

However when an encoding does become allocated then we need to ensure that it's
used as the preferred disassembly.  The problem with cfinv is that its mask has
all bits sets because it has no arguments.

This causes issues for the Alias resolver in gas as it uses the mask to build
alias graph.  In this case it can't do it since it thinks almost everything
would alias with cfinv.  So instead we can only fix this by moving cfinv before
msr.

gas/ChangeLog:

	PR 25403
	* testsuite/gas/aarch64/armv8_4-a.d: Add cfinv.
	* testsuite/gas/aarch64/armv8_4-a.s: Likewise.

opcodes/ChangeLog:

	PR 25403
	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	* aarch64-asm-2.c: Regenerate
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
2020-01-27 10:55:41 +00:00
Jan Beulich
c006a730e9 x86: improve handling of insns with ambiguous operand sizes
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).

While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.

No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).

As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).

Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.

Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.

Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
2020-01-21 08:28:25 +01:00
Jan Beulich
c906a69a1f x86: VCVTNEPS2BF16{X,Y} should permit broadcasting
Just like other VCVT*{X,Y} templates do, and to allow the programmer
flexibility (might be relevant in particular when heavily macro-izing
code), the two templates should also have Broadcast set, just like their
X/Y-suffix-less counterparts. This in turn requires them to also have
* Dword set on their memory operands, to cover the logic added to
  i386gen by 4a1b91eabb ("x86: Expand Broadcast to 3 bits"),
* RegXMM/RegYMM set on their source operands, to satisfy broadcast
  sizing logic in gas itself.
Otherwise ATTSyntax templates wouldn't need such operand size attributes.

While extending the test cases, also add Intel syntax broadcast forms
without explicit size specifiers.
2020-01-21 08:25:31 +01:00
Nick Clifton
26916852e1 Updated translations for various binutils sub-directories 2020-01-20 15:10:23 +00:00
Alan Modra
4d6cbb6442 ubsan: hppa: negation of -2147483648
* hppa-dis.c (fput_const): Remove useless cast.
2020-01-20 15:45:50 +10:30
Alan Modra
2bddb71a74 ubsan: arm: out of bounds array access
.inst 0x81bdfe9f

disassembles as
   0:	81bdfe9f 	ldaexdhi	pc, reg-names-std, [sp]

I'm quite sure "reg-names-std" isn't an ARM register.

	* arm-dis.c (print_insn_arm): Wrap 'T' value.
2020-01-20 15:45:50 +10:30
Nick Clifton
1b1bb2c67b Update version to 2.34.50. Regenerate configure and .pot files. 2020-01-18 14:12:07 +00:00
Nick Clifton
ae77468624 Add markers for 2.34 branch to the NEWS files and ChangeLogs. 2020-01-18 13:50:25 +00:00
Christian Biesinger
07f1f3aa53 Fix spelling errors
seperate -> separate

bfd/ChangeLog:

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* coff-arm.c: Fix spelling error (seperate).
	* elfxx-riscv.c (riscv_parse_sv_or_non_std_ext): Fix spelling
	error (seperate).
	* sysdep.h (strnlen): Fix spelling error (seperate).

opcodes/ChangeLog:

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* opintl.h: Fix spelling error (seperate).

sim/arm/ChangeLog:

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* iwmmxt.c: Fix spelling error (seperate).

Change-Id: I55e5f47bcf3cf3533d2acb7ad338f1be0d5f30f9
2020-01-17 12:34:03 -06:00
H.J. Lu
42e04b3601 x86: Add {vex} pseudo prefix
There are 2-byte VEX prefix and 3-byte VEX prefix.  2-byte VEX prefix
can't encode all operands.  By default, assembler tries 2-byte VEX prefix
first.  {vex3} can be used to force 3-byte VEX prefix.  This patch adds
{vex} pseudo prefix and keeps {vex2} for backward compatibility.

gas/

	* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
	with vex_encoding_vex.
	(parse_insn): Likewise.
	* doc/c-i386.texi: Replace {vex2} with {vex}.  Update {vex}
	and {vex3} documentation.
	* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
	{vex}.
	* testsuite/gas/i386/x86-64-pseudos.s: Likewise.

opcodes/

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.
2020-01-17 07:07:55 -08:00
Andre Vieira
2da2eaf4ce [binutils][arm] PR25376 Change MVE into a CORE_HIGH feature
This patch moves MVE feature bits into the CORE_HIGH section.  This makes sure
.fpu and -mfpu does not reset the bits set by MVE. This is important because
.fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose
to define MVE as an architecture extension rather than put it together with
other the legacy fpu features.

This will enable the following behavior:
.arch armv8.1-m.main
.arch mve
.fpu fpv5-sp-d16               #does not disable mve.
vadd.i32 q0, q1, q2

This patch also makes sure MVE is not taken into account during auto-detect.
This was already the case, but because we moved the MVE bits to the
architecture feature space we must make sure ARM_ANY does not include MVE.

gas/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
	(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
	* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.

include/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
	(ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
	(ARM_ANY): Redefine to not include any MVE bits.
	(ARM_FEATURE_ALL): Removed.

opcodes/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.
2020-01-16 14:33:01 +00:00
Jan Beulich
d0849eed78 x86: drop stale Vec_Imm4 related comment
I overlooked this in commit 9d3bf266fd ("x86: drop Vec_Imm4"), presumably
because of the mis-spelling.
2020-01-16 10:07:05 +01:00
Jan Beulich
9cf70a448b x86: add a few more missing VexWIG
Alternatively it could also be VexW0 (to match other SSE2AVX), but the
VexW attribute shouldn't be left unset.
2020-01-16 10:06:21 +01:00
Jan Beulich
4814632e69 x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit mode
The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand
forms accepted even outside of 64-bit mode, and this even without any
{evex} pseudo-prefix (otherwise one could argue that this is an attempt
to follow one possible, albeit somewhat odd, interpretation of the SDM
wording to this effect).

For consistency between the various involved templates drop the
* (now) unnecessary IgnoreSize attributes
* unnecessary (due to VexW1) Size64 attributes from VEX encoded forms
* redundant (with Reg64) Qword operand attributes
uniformly.
2020-01-16 10:05:35 +01:00
Alan Modra
aad09917e0 tic4x disassembly static variables
tic4x uses a number of static variables for tables that are generated
depending on the current machine (tic4x vs. tic3x).  However, it is
possible to change the machine from one invocation of print_insn_tic4x
to the next.  This patch throws away the old state if that happens,
and uses a relatively small known size array of register names rather
than a malloc'd table.

	* tic4x-dis.c (tic4x_version): Make unsigned long.
	(optab, optab_special, registernames): New file scope vars.
	(tic4x_print_register): Set up registernames rather than
	malloc'd registertable.
	(tic4x_disassemble): Delete optable and optable_special.  Use
	optab and optab_special instead.  Throw away old optab,
	optab_special and registernames when info->mach changes.
2020-01-16 00:01:13 +10:30
Sergey Belyashov
7a6bf3becb Fix various assembler testsuite failures for the Z80 target.
PR 25377
gas	* config/tc-z80.c: Add support for half precision, single
	precision and double precision floating point values.
	* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
	* doc/as.texi: Add new z80 command line options.
	* doc/c-z80.texi: Document new z80 command line options.
	* testsuite/gas/z80/ez80_pref_dis.s: New test.
	* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
	* testsuite/gas/z80/z80.exp: Run the new test.
	* testsuite/gas/z80/fp_math48.d: Use correct command line option.
	* testsuite/gas/z80/fp_zeda32.d: Likewise.
	* testsuite/gas/z80/strings.d: Update expected output.

opcodes	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.
2020-01-14 13:13:57 +00:00
Alan Modra
ca1eaac0ed ubsan: z8k: left shift cannot be represented in type 'int'
* z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
	values to unsigned before shifting.
2020-01-14 10:57:52 +10:30
Thomas Troeger
1d67fe3b6e Add an option to objdump's disassembler to generate ascii art diagrams showing the destinations of flow control instructions.
binutils* objdump.c (visualize_jumps, color_output, extended_color_output)
	(detected_jumps): New variables.
	(usage): Add the new jump visualization options.
	(option_values): Add new option value.
	(long_options): Add the new option.
	(jump_info_new, jump_info_free): New functions.
	(jump_info_min_address, jump_info_max_address): Likewise.
	(jump_info_end_address, jump_info_is_start_address): Likewise.
	(jump_info_is_end_address, jump_info_size): Likewise.
	(jump_info_unlink, jump_info_insert): Likewise.
	(jump_info_add_front, jump_info_move_linked): Likewise.
	(jump_info_intersect, jump_info_merge): Likewise.
	(jump_info_sort, jump_info_visualize_address): Likewise.
	(disassemble_jumps): New function - used to locate jumps.
	(disassemble_bytes): Add ascii art generation.
	(disassemble_section): Add scan to locate jumps.
	(main): Parse the new visualization option.
	* doc/binutils.texi: Document the new feature.
	* NEWS: Mention the new feature.

opcodes	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	flow instructions.
	(print_insn_thumb16, print_insn_thumb32): Likewise.
	(print_insn): Initialize the insn info.
	* i386-dis.c (print_insn): Initialize the insn info fields, and
	detect jumps.
2020-01-13 12:36:55 +00:00
Claudiu Zissulescu
5e4f7e0518 [ARC][committed] Code cleanup and improvements.
Code clean up and improvements when changing the cpu from command
line. Also, remove unused/old emulations.

gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change
	the CPU.
	* config/tc-arc.h: Add header if/defs.
	* testsuite/gas/arc/pseudos.d: Improve matching pattern.

ls/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* Makefile.am: Remove earcelf_prof.c and earclinux_prof.c
	emulations.
	* Makefile.in: Regenerate.
	* configure.tgt: Likewise.
	* emulparams/arcelf_prof.sh: Remove file.
	* emulparams/arclinux_prof.sh: Likewise.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (C_NE): Make it required.
2020-01-13 11:16:47 +02:00
Claudiu Zissulescu
b9fe6b8aa6 [ARC] [COMMITTED] Change ACCL/ACCH reg name to generic.
ACCL/ACCH register names are only available for ARCv2 architecture,
leading to a confusion when disassembling for any other ARC
variants. This patch is changing the default names for ACCL/ACCH to
generic r58/r59.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

        * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	reserved register name.
2020-01-13 10:25:50 +02:00
Alan Modra
90dee485e5 asan: ns32k: wild memory write
index_offset isn't set up for "sfsr", resulting in a random offset
being used when trying to disassemble the following.

 .byte 0x3e, 0xf7, 0x07, 0x00

	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2020-01-13 18:43:34 +10:30
Alan Modra
febda64f15 ubsan: wasm32: signed integer overflow
The signed integer overflow occurred when adding one to target_count
  for (i = 0; i < target_count + 1; i++)
but that's the least of the worries here.  target_count was long and i
int, leading to the possibility of a loop that never ended.

So to avoid this type of vulnerability, this patch uses what I believe
to be the proper types for arguments of various wasm32 opcodes, rather
than using "long" which may change in size.

gas/
	* testsuite/gas/wasm32/allinsn.d: Update expected output.
opcodes/
	* wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
	result of wasm_read_leb128 in a uint64_t and check that bits
	are not lost when copying to other locals.  Use uint32_t for
	most locals.  Use PRId64 when printing int64_t.
2020-01-13 16:44:27 +10:30
Alan Modra
df08b5881b score formatting
* score-dis.c: Formatting.
	* score7-dis.c: Formatting.
2020-01-13 12:12:41 +10:30
Alan Modra
b2c759ce68 ubsan: score: left shift of negative value
* score-dis.c (print_insn_score48): Use unsigned variables for
	unsigned values.  Don't left shift negative values.
	(print_insn_score32): Likewise.
	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2020-01-13 12:12:30 +10:30
Alan Modra
5496abe1c5 tic4x: sign extension using shifts
Don't do that.  Especially don't use shift counts that assume the type
being shifted is 32 bits when the type is long/unsigned long.  Also
reverts part of a change I made on 2019-12-11 to tic4x_print_register
that on closer inspection turns out to be unnecessary.

include/
	* opcode/tic4x.h (EXTR): Delete.
	(EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign
	extension using shifts.  Do trim INSERTU value to specified bitfield.
opcodes/
	* tic4x-dis.c (tic4x_print_register): Remove dead code.
gas/
	* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
	insertion.
2020-01-13 12:12:05 +10:30
Alan Modra
202e762b32 ubsan: fr30: left shift of negative value
cpu/
	* fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't
	left shift signed values.
opcodes/
	* fr30-ibld.c: Regenerate.
2020-01-13 12:12:05 +10:30
Alan Modra
7ef412cf72 ubsan: xgate: left shift of negative value
* xgate-dis.c (print_insn): Don't left shift signed value.
	(ripBits): Formatting, use 1u.
2020-01-13 12:12:05 +10:30
Alan Modra
7f578b959c ubsan: tilepro: signed integer overflow
* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
2020-01-10 17:32:33 +10:30
Alan Modra
441af85bd9 ubsan: m10300: shift exponent -4
* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	and XRREG value earlier to avoid a shift with negative exponent.
	* m10200-dis.c (disassemble): Similarly.
2020-01-10 17:32:33 +10:30
Nick Clifton
bce58db4fb Fix the cast used to prevent compile time warning about an always false test.
PR 25224
	* z80-dis.c (ld_ii_ii): Use correct cast.
2020-01-09 14:32:49 +00:00
Sergey Belyashov
40c75bc8b0 Fix compile time warnings about comparisons always being false.
PR 25224
gas	* config/tc-z80.c (emit_ld_m_rr): Use integer types when checking
	opcode byte values.
	(emit_ld_r_r): Likewise.
	(emit_ld_rr_m): Likewise.
	(emit_ld_rr_nn): Likewise.

opcodes	* z80-dis.c (ld_ii_ii): Use character constant when checking
	opcode byte value.
2020-01-09 11:49:18 +00:00
Jan Beulich
d835a58baa x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD
The disassembler change is such that in default mode we'd disassemble
the insns (for there not ebing any conflicts), but when AMD64 mode was
explicitly requested, we'd show them as "(bad)".
2020-01-09 11:38:01 +01:00
Alan Modra
030a2e78ac ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]'
The fix is the additional ARRAY_SIZE test, the rest just tidies
variable types rather than adding a cast to avoid warnings.

opcodes/
	* z8k-dis.c: Include libiberty.h
	(instr_data_s): Make max_fetched unsigned.
	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	Don't exceed byte_info bounds.
	(output_instr): Make num_bytes unsigned.
	(unpack_instr): Likewise for nibl_count and loop.
	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	idx unsigned.
	* z8k-opc.h: Regenerate.
gas/
	* config/tc-z8k.c (md_begin): Make idx unsigned.
	(get_specific): Likewise for this_index.
2020-01-08 21:51:32 +10:30
Shahab Vahedi
bb82aefe17 [ARC] Add finer details for LLOCK and SCOND
This patch changes the "class" of LLOCK/SCOND from "MEMORY" to
"LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode".

These changes are necessary for GDB's atmoic sequence handler.

Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
2020-01-07 15:25:34 +02:00
Alan Modra
cc6aa1a6e0 ubsan: m32c: left shift of negative value
There are probably a lot more of these still here.

cpu/
	* m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign
	bits before shifting rather than masking after shifting.
	(f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise.
	(f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise.
	(f-dsp-64-u16, f-dsp-8-s24): Likewise.
	(f-bitbase32-16-s19-unprefixed): Avoid signed left shift.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-01-06 21:53:51 +10:30
Alan Modra
660e62b1d9 PR25344, z80 disassembler recursion
PR 25344
	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	Peek at next byte to prevent recursion on repeated prefix bytes.
	Ensure uninitialised "mybuf" is not accessed.
	(print_insn_z80): Don't zero n_fetch and n_used here,..
	(print_insn_z80_buf): ..do it here instead.
2020-01-06 21:53:16 +10:30
Alan Modra
c9ae58fe32 ubsan: m32r: left shift of negative value
cpu/
	* m32r.cpu (f-disp8): Avoid left shift of negative values.
	(f-disp16, f-disp24): Likewise.
opcodes/
	* m32r-ibld.c: Regenerate.
2020-01-04 19:20:33 +10:30
Alan Modra
5f57d4ecf5 ubsan: cr16: left shift cannot be represented in type 'int'
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2020-01-04 19:20:33 +10:30
Alan Modra
2c5c119630 ubsan: crx: left shift cannot be represented in type 'int'
* crx-dis.c (match_opcode): Avoid shift left of signed value.
2020-01-04 19:20:33 +10:30
Alan Modra
2e98c6c5c5 ubsan: d30v: left shift cannot be represented in type 'int'
* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2020-01-04 19:20:33 +10:30
Jan Beulich
5437a02abc Arm64: correct address index operands for LD1RO{H,W,D}
Just like their LD1RQ{H,W,D} counterparts, as per the specification the
index registers get scaled by element size.
2020-01-03 10:16:44 +01:00
Jan Beulich
567dfba2be Arm64: correct {su,us}dot SIMD encodings
According to the specification these permit the Q bit to control the
vector length operated on, and hence this bit should not already be set
in the opcode table entries (it rather needs setting dynamically). Note
how the test case output did also not match its input. Besides
correcting the test case also extend it to cover both forms.
2020-01-03 10:14:16 +01:00
Jan Beulich
8c45011acd Arm64: correct uzp{1,2} mnemonics
According to the specification, and in line with the pre-existing
predicate forms, the mnemonics do not include an 'i'.
2020-01-03 10:13:31 +01:00
Jan Beulich
f4950f76fa Arm64: correct 64-bit element fmmla encoding
There's just one bit of difference to the 32-bit element form, as
per the documentation.
2020-01-03 10:12:49 +01:00
Sergey Belyashov
6655dba246 Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. Add an ELF based target for these as well.
PR 25224
bfd	* Makefile.am: Add z80-elf target support.
	* configure.ac: Likewise.
	* targets.c: Likewise.
	* config.bfd: Add z80-elf target support and new arches: ez80 and z180.
	* elf32-z80.c: New file.
	* archures.c: Add new z80 architectures: eZ80 and Z180.
	* coffcode.h: Likewise.
	* cpu-z80.c: Likewise.
	* bfd-in2.h: Likewise plus additional Z80 relocations.
	* coff-z80.c: Add new relocations for Z80 target and local label check.

gas	* config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support
	for assembler code generated by SDCC. Add new relocation types. Add
	z80-elf target support.
	* config/tc-z80.h: Add z80-elf target support. Enable dollar local
	labels. Local labels starts from ".L".
	* testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict.
	* testsuite/gas/all/fwdexp.s: Likewise.
	* testsuite/gas/z80/suffix.d: Fix failure on ELF target.
	* testsuite/gas/z80/z80.exp: Add new tests
	* testsuite/gas/z80/dollar.d: New file.
	* testsuite/gas/z80/dollar.s: New file.
	* testsuite/gas/z80/ez80_adl_all.d: New file.
	* testsuite/gas/z80/ez80_adl_all.s: New file.
	* testsuite/gas/z80/ez80_adl_suf.d: New file.
	* testsuite/gas/z80/ez80_isuf.s: New file.
	* testsuite/gas/z80/ez80_z80_all.d: New file.
	* testsuite/gas/z80/ez80_z80_all.s: New file.
	* testsuite/gas/z80/ez80_z80_suf.d: New file.
	* testsuite/gas/z80/r800_extra.d: New file.
	* testsuite/gas/z80/r800_extra.s: New file.
	* testsuite/gas/z80/r800_ii8.d: New file.
	* testsuite/gas/z80/r800_z80_doc.d: New file.
	* testsuite/gas/z80/z180.d: New file.
	* testsuite/gas/z80/z180.s: New file.
	* testsuite/gas/z80/z180_z80_doc.d: New file.
	* testsuite/gas/z80/z80_doc.d: New file.
	* testsuite/gas/z80/z80_doc.s: New file.
	* testsuite/gas/z80/z80_ii8.d: New file.
	* testsuite/gas/z80/z80_ii8.s: New file.
	* testsuite/gas/z80/z80_in_f_c.d: New file.
	* testsuite/gas/z80/z80_in_f_c.s: New file.
	* testsuite/gas/z80/z80_op_ii_ld.d: New file.
	* testsuite/gas/z80/z80_op_ii_ld.s: New file.
	* testsuite/gas/z80/z80_out_c_0.d: New file.
	* testsuite/gas/z80/z80_out_c_0.s: New file.
	* testsuite/gas/z80/z80_reloc.d: New file.
	* testsuite/gas/z80/z80_reloc.s: New file.
	* testsuite/gas/z80/z80_sli.d: New file.
	* testsuite/gas/z80/z80_sli.s: New file.

ld	* Makefile.am: Add new target z80-elf
	* configure.tgt: Likewise.
	* emultempl/z80.em: Add support for eZ80 and Z180 architectures.
	* emulparams/elf32z80.sh: New file.
	* emultempl/z80elf.em: Likewise.
	* testsuite/ld-z80/arch_ez80_adl.d: Likewise.
	* testsuite/ld-z80/arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/arch_r800.d: Likewise.
	* testsuite/ld-z80/arch_z180.d: Likewise.
	* testsuite/ld-z80/arch_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise.
	* testsuite/ld-z80/comb_arch_z180.d: Likewise.
	* testsuite/ld-z80/labels.s: Likewise.
	* testsuite/ld-z80/relocs.s: Likewise.
	* testsuite/ld-z80/relocs_b_ez80.d: Likewise.
	* testsuite/ld-z80/relocs_b_z80.d: Likewise.
	* testsuite/ld-z80/relocs_f_z80.d: Likewise.
	* testsuite/ld-z80/z80.exp: Likewise.

opcodes	* z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-02 14:14:59 +00:00
Alan Modra
b14ce8bfe1 Re: Update year range in copyright notice of binutils files
Add the ChangeLog entry.
2020-01-01 18:55:18 +10:30
Alan Modra
b3adc24a07 Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
Alan Modra
0b11474080 ChangeLog rotation 2020-01-01 18:12:08 +10:30
Alan Modra
2c5b6e1a1c Re: Usage of unitialized heap in tic4x_print_cond
PR 25319
	* tic4x-dis.c (tic4x_print_cond): Correct order of xcalloc args.
2019-12-30 09:35:29 +10:30
Alan Modra
4383e1fc3b ubsan: sparc: left shift cannot be represented in type 'int'
* sparc-dis.c (SEX): Don't use left and right shift to sign extend.
	(compare_opcodes): Avoid signed shift left overflow.
	(print_insn_sparc): Likewise.
2019-12-29 22:13:27 +10:30
Alan Modra
8c5e259235 Usage of unitialized heap in tic4x_print_cond
PR 25319
	* tic4x-dis.c (tic4x_print_cond): Init all of condtable.
2019-12-29 22:13:12 +10:30
Jan Beulich
376cd05610 x86-64: fix Intel64 handling of branch with data16 prefix
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious
direct destination to translate to an indirect _far_ branch is plain
wrong. The operand size prefix should have no effect at all on the
interpretation of the operand. The main underlying issue here is that
the Intel64 templates of the direct branches don't include Disp16, yet
various assumptions exist that it would always be there when there's
also Disp32/Disp32S, toggled by the operand size prefix (which is
being ignored by direct branches in Intel64 mode).

Along these lines it was also wrong to base the displacement width
decision solely on the operand size prefix: REX.W cancels this effect
and hence needs taking into consideration, too.

A disassembler change is needed here as well: XBEGIN was wrongly treated
the same as direct CALL/JMP, which isn't the case - the operand size
prefix does affect displacement size there, it's merely ignored when it
comes to updating [ER]IP.
2019-12-27 09:38:34 +01:00
Jan Beulich
48bcea9f48 x86: consolidate Disp<NN> handling a little
In memory operand addressing, which forms of displacement are permitted
besides Disp8 is pretty clearly limited
- outside of 64-bit mode, Disp16 or Disp32 only, depending on address
  size (MPX being special in not allowing Disp16),
- in 64-bit mode, Disp32s or Disp64 without address size override, and
  solely Disp32 with one.
Adjust assembler and i386-gen to match this, observing that templates
already get adjusted before trying to match them against input depending
on the presence of an address size prefix.

This adjustment logic gets extended to all cases, as certain DispNN
values should also be dropped when there's no such prefix. In fact
behavior of the assembler, perhaps besides the exact diagnostics wording,
should not differ between there being templates applicable to 64-bit and
non-64-bit at the same time, or there being fully separate sets of
templates, with their DispNN settings already reduced accordingly.

This adjustment logic further gets guarded such that there wouldn't be
and Disp<N> conversion based on address size prefix when this prefix
doesn't control the width of the displacement (on branches other than
absolute ones).

These adjustments then also allow folding two MOV templates, which had
been split between 64-bit and non-64-bits variants so far.

Once in this area also
- drop the bogus DispNN from JumpByte templates, leaving just the
  correct Disp8 there (compensated by i386_finalize_displacement()
  now setting Disp8 on their operands),
- add the missing Disp32S to XBEGIN.

Note that the changes make it necessary to temporarily mark a test as
XFAIL; this will get taken care of by a subsequent patch. The failing
parts are entirely bogus and will get replaced.
2019-12-27 09:22:03 +01:00
Alan Modra
100b122fc1 ubsan: crx: index 5 out of bounds for type 'operand_desc const[5]'
* crx-dis.c (get_number_of_operands): Don't access operands[]
	out of bounds.
2019-12-26 17:49:03 +10:30
Alan Modra
6c2ca6c25d ubsan: v850: left shift cannot be represented in type 'int'
Another 1 << 31 complaint.

	* v850-dis.c (disassemble): Avoid signed overflow.  Don't use
	long vars when unsigned int will do.
2019-12-26 17:49:03 +10:30
Alan Modra
ebd1c6d1d3 ubsan: arm: shift exponent 32 is too large for 32-bit type 'unsigned int'
* arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
2019-12-24 12:01:42 +10:30
Jan Beulich
0e62b37a3f ppc: misc minor build corrections
Avoid shadowing a libiberty symbol (which oldish gcc warns about by
default), and allow building cleanly on 32-bit distros.
2019-12-23 11:53:10 +01:00
Alan Modra
7936714c0c ubsan: score: left shift of 2 by 31 places cannot be represented in type 'int'
* score-dis.c (print_insn_score32): Avoid signed overflow.
	(print_insn_score48): Likewise.  Don't cast to int when printing
	hex values.
2019-12-23 18:05:19 +10:30
Alan Modra
3e1056a1a6 ubsan: iq2000: left shift of negative value
cpu/
	* iq2000.cpu (f-offset): Avoid left shift of negative values.
opcodes/
	* iq2000-ibld.c: Regenerate.
2019-12-23 18:04:12 +10:30
Alan Modra
1a1e2852a5 ubsan: d30v: left shift cannot be represented in type 'long long'
* d30v-dis.c (extract_value): Make num param a uint64_t, constify
	oper.  Use unsigned vars.
	(print_insn): Make num var uint64_t.  Constify oper and remove now
	unnecessary casts on extract_value calls.
	(print_insn_d30v): Use unsigned vars.  Adjust printf formats.
2019-12-23 18:02:44 +10:30
Alan Modra
27c1c4271a ubsan: wasm: shift is too large for 64-bit type 'bfd_vma'
bfd/
	* wasm-module.c (wasm_read_leb128): Don't allow oversize shifts.
	Catch value overflow.  Sign extend only on terminating byte.
opcodes/
	* wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
	Catch value overflow.  Sign extend only on terminating byte.
2019-12-23 17:58:09 +10:30
Alan Modra
cda8d785b3 PR25281, sh disassembler abort
PR 25281
	* sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
	and MOVY_NOPX insns.  For invalid cases include 0xf000 in the word
	printed.  Print .word in more cases.
2019-12-20 17:57:58 +10:30
Alan Modra
bcd9f578a9 ubsan: or1k: left shift of negative value
cpu/
	* or1korbis.cpu (f-disp26, f-disp21): Don't left shift negative values.
opcodes/
	* or1k-ibld.c: Regenerate.
2019-12-20 17:57:58 +10:30
Alan Modra
15d2859fdd ubsan: hppa: left shift of negative value
bfd/
	* libhppa.h (hppa_field_adjust, bfd_hppa_insn2fmt): Delete forward
	declaration.  Move ATTRIBUTE_UNUSED to definition.
	(sign_extend, low_sign_extend, sign_unext, low_sign_unext),
	(re_assemble_3, re_assemble_12, re_assemble_14, re_assemble_16),
	(re_assemble_17, re_assemble_21, re_assemble_22): Likewise.  Make
	args and return value unsigned.  Use unsigned variables.
	(hppa_rebuild_insn): Similarly.
opcodes/
	* hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
	unsigned variables.
2019-12-20 13:36:06 +10:30
Alan Modra
000fe1a756 ubsan: m68hc1x: left shift of negative value
* m68hc11-dis.c (read_memory): Delete forward decls.
	(print_indexed_operand, print_insn): Likewise.
	(print_indexed_operand): Formatting.  Don't rely on short being
	exactly 16 bits, make sign extension explicit.
	(print_insn): Likewise.  Avoid signed overflow.
2019-12-20 13:36:06 +10:30
Alan Modra
f00901886d vax decoding of indexed addressing mode
This patch prevents print_insn_mode recursing into another index mode
byte, which if repeated enough times will overflow private.the_buffer
and scribble over other memory.

	* vax-dis.c (print_insn_mode): Stop index mode recursion.
2019-12-19 15:38:39 +10:30
Dr N.W. Filardo
1d29ab86cb PR25277, microblaze opcode enumeration vs ISO/IEC TS 18661-3:2015
fadd, fmul, and fdiv are now, by ISO/IEC TS 18661-3:2015, defined to
refer to functions from the runtime subsystem.

	PR 25277
	* microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
	fdiv with "mbi_".
	* microblaze-opc.h (opcodes): Adjust to suit.
2019-12-19 10:54:47 +10:30
Alan Modra
2480b6fa94 More signed overflow fixes
The arc fix in create_map avoiding signed overflow by casting an
unsigned char to unsigned int before shifting, shows one of the
dangers of blinding doing that.  The problem in this case was that the
variable storing the value, newAuxRegister->address, was a long.
Using the unsigned cast meant that the 32-bit value was zero extended
when long is 64 bits.  Previously we had a sign extension.  Net result
was that comparisons in arcExtMap_auxRegName didn't match.  Of course,
I could have cast the 32-bit unsigned value back to signed before
storing in a long, but it's neater to just use an unsigned int for the
address.

opcodes/
	* alpha-opc.c (OP): Avoid signed overflow.
	* arm-dis.c (print_insn): Likewise.
	* mcore-dis.c (print_insn_mcore): Likewise.
	* pj-dis.c (get_int): Likewise.
	* ppc-opc.c (EBD15, EBD15BI): Likewise.
	* score7-dis.c (s7_print_insn): Likewise.
	* tic30-dis.c (print_insn_tic30): Likewise.
	* v850-opc.c (insert_SELID): Likewise.
	* vax-dis.c (print_insn_vax): Likewise.
	* arc-ext.c (create_map): Likewise.
	(struct ExtAuxRegister): Make "address" field unsigned int.
	(arcExtMap_auxRegName): Pass unsigned address.
	(dump_ARC_extmap): Adjust.
	* arc-ext.h (arcExtMap_auxRegName): Update prototype.
2019-12-18 18:38:13 +10:30
Alan Modra
eb7b504651 ubsan: visium: left shift cannot be represented in type 'int'
* visium-dis.c (print_insn_visium): Avoid signed overflow.
2019-12-17 23:15:12 +10:30
Alan Modra
29298bf66f ubsan: aarch64: left shift cannot be represented in type 'int64_t'
* aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
	(value_fit_unsigned_field_p): Likewise.
	(aarch64_wide_constant_p): Likewise.
	(operand_general_constraint_met_p): Likewise.
	* aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
2019-12-17 22:58:19 +10:30
Alan Modra
e46d79a76e ubsan: nds32: left shift cannot be represented in type 'int'
Yet more.

	* nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
	(print_insn_nds32): Use uint64_t for "given" and "given1".
2019-12-17 22:58:11 +10:30
Alan Modra
5b660084e2 Remove tic80 support
This is one way of fixing ubsan bug reports, just delete the code.

The assembler support was removed back in 2005 along with other
non-BFD assemblers, but somehow the remainder of the port stayed in.

bfd/
	* coff-tic80.c: Delete file.
	* cpu-tic80.c: Delete file.
	* archures.c: Remove tic80 support.
	* coffcode.h: Likewise.
	* coffswap.h: Likewise.
	* targets.c: Likewise.
	* config.bfd: Likewise.
	* configure.ac: Likewise.
	* Makefile.am: Likewise.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* po/SRC-POTFILES.in: Regenerate.
binutils/
	* testsuite/binutils-all/objcopy.exp: Remove tic80 support.
	* testsuite/binutils-all/objdump.exp: Likewise.
gas/
	* doc/as.texi: Remove mention of tic80.
include/
	* coff/tic80.h: Delete file.
	* opcode/tic80.h: Delete file.
ld/
	* emulparams/tic80coff.sh: Delete file.
	* scripttempl/tic80coff.sc: Delete file.
	* configure.tgt: Remove tic80 support.
	* Makefile.am: Likewise.
	* Makefile.in: Regenerate.
	* po/BLD-POTFILES.in: Regenerate.
opcodes/
	* tic80-dis.c: Delete file.
	* tic80-opc.c: Delete file.
	* disassemble.c: Remove tic80 support.
	* disassemble.h: Likewise.
	* Makefile.am: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.
2019-12-17 16:36:54 +10:30
Alan Modra
62e6599087 ubsan: bpf: left shift cannot be represented in type 'DI' (aka 'long')
cpu/
	* bpf.cpu (f-imm64): Avoid signed overflow.
opcodes/
	* bpf-ibld.c: Regenerate.
2019-12-17 14:32:23 +10:30
Alan Modra
f81e7e2db6 ubsan: aarch64: left shift of negative value
* aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
	conditional.
	(aarch64_ext_imm): Avoid signed overflow.
2019-12-16 17:35:13 +10:30
Alan Modra
488d02fe77 ubsan: microblaze: left shift cannot be represented in type 'int'
* microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
2019-12-16 17:35:13 +10:30
Alan Modra
8a92faab92 ubsan: nios2: left shift cannot be represented in type 'int'
* nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
2019-12-16 17:35:13 +10:30
Alan Modra
e6ced26afd ubsan: xstormy16: left shift of negative value
cpu/
	* xstormy16.cpu (f-rel12a): Avoid signed overflow.
opcodes/
	* xstormy16-ibld.c: Regenerate.
2019-12-16 17:35:13 +10:30
Alan Modra
84e098cdea asan: score: global-buffer-overflow
I'm flying blind here, not having an s+core s3 insn set reference,
but this seems reasonably obvious from what is done by the assembler.
s3_do16_rpop does some mixing of imm and reg values to place in the
rpop reg field, but I'm not going to try to fix the disassembly
there.

	* score-dis.c (print_insn_score16): Move rpush/rpop imm field
	value adjustment so that it doesn't affect reg field too.
2019-12-16 17:34:29 +10:30
Alan Modra
36bd8ea7f0 ubsan: crx: left shift cannot be represented in type 'int'
The ubsan complaint is fixed by the SBM change, with similar possible
complaints fixed by the EXTRACT change.  The rest is just cleanup.

include/
	* opcode/crx.h (inst <match>): Make unsigned int.
opcodes/
	* crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
	(get_number_of_operands, getargtype, getbits, getregname),
	(getcopregname, getprocregname, gettrapstring, getcinvstring),
	(getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
	(powerof2, match_opcode, make_instruction, print_arguments),
	(print_arg): Delete forward declarations, moving static to..
	(getregname, getcopregname, getregliststring): ..these definitions.
	(build_mask): Return unsigned int mask.
	(match_opcode): Use unsigned int vars.
2019-12-16 17:33:53 +10:30
Alan Modra
cedfc77485 ubsan: bfin: left shift of negative value
* bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
2019-12-16 17:33:53 +10:30
Alan Modra
4bdb25fe69 ubsan: nds32: left shift cannot be represented in type 'int'
Note that using 1u in N32_BIT makes all of N32_BIT, __MASK, __MF, __GF
and __SEXT evaluate as unsigned int (the latter three when when their
v arg is int or smaller).  This would be a problem if assigning the
result to a bfd_vma, long, or other type wider than an int since the
__SEXT result would be zero extended to the wider type.  Fortunately
nds32 target code doesn't use wider types unnecessarily.

include/
	* opcode/nds32.h (N32_BIT): Define using 1u.
	(__SEXT): Use __MASK and N32_BIT.
	(N32_IMMS): Remove duplicate mask.
opcodes/
	* nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
	(struct objdump_disasm_info): Delete.
	(nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
	N32_IMMS to unsigned before shifting left.
2019-12-16 17:33:53 +10:30