This patch adds new to Armv8.7 WFIT instruction which take one operand:
WFIT <Xt>
Where:
<Xt> is 64-bit name of the general-purpose source register, encoded in the
"Rd" field.
For more details regarding WFIT (Wait For Interrupt with Timeout) instruction for
Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A
architecture profile, see document pages 570 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* testsuite/gas/aarch64/system-5.d: Update test with WFIT insn.
* testsuite/gas/aarch64/system-5.s: Update test with WFIT insn.
opcodes/ChangeLog:
2020-10-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (struct aarch64_opcode): New instruction WFIT.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch adds:
+ New feature +csre to -march command line.
+ New instruction CSR PDEC associated with CSRE feature.
Please note that CSRE system registers were already upstreamed. This patch
should finalize CSRE feature implementation.
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of
a Call stack record) instruction. Although this instruction has operand
(PDEC) it's instruction's only operand. PDEC forces instruction field Rt
to be set to 0b1111. This results in fixed opcode of the instruction.
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* config/tc-aarch64.c (parse_csr_operand): New operand parser.
(parse_operands): Call to CSR operand parser.
* testsuite/gas/aarch64/csre_csr-invalid.d: New test.
* testsuite/gas/aarch64/csre_csr-invalid.l: New test.
* testsuite/gas/aarch64/csre_csr-invalid.s: New test.
* testsuite/gas/aarch64/csre_csr.d: New test.
* testsuite/gas/aarch64/csre_csr.s: New test.
include/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
* aarch64-tbl.h (CSRE): New CSRE feature handler.
(_CSRE_INSN): New CSRE instruction type.
(struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch adds new to Armv8.7 WFET instruction which take one operand:
WFET <Xt>
Where:
<Xt> is 64-bit name of the general-purpose source register, encoded in the
"Rd" field.
For more details regarding WFET (Wait For Event with Timeout) instruction for
Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A
architecture profile, see document pages 565 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* testsuite/gas/aarch64/system-5.d: New test.
* testsuite/gas/aarch64/system-5.s: New test.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
and operand description.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch adds new variant (nXS) of DSB memory barrier instruction
available in Armv8.7-a. New nXS variant has different encoding in
comparison with pre Armv8.7-a DSB memory barrier variant thus new
instruction and new operand was added.
DSB memory nXS barrier variant specifies the limitation on the barrier
operation. Allowed values are:
DSB SYnXS|#28
DSB ISHnXS|#24
DSB NSHnXS|#20
DSB OSHnXS|#16
Please note that till now, for barriers, barrier operation was encoded in
4-bit unsigned immediate CRm field (in the range 0 to 15).
For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned
assembly instruction immediate, encoded in instruction in two bits CRm<3:2>:
CRm<3:2> #imm
00 16
01 20
10 24
11 28
This patch extends current AArch64 barrier instructions with above mapping.
Notable patch changes include:
+ New DSB memory barrier variant encoding for Armv8.7-a.
+ New operand BARRIER_DSB_NXS for above instruction in order to
distinguish between existing and new DSB instruction flavour.
+ New set of DSB nXS barrier options.
+ New instruction inserter and extractor map between instruction
immediate 5-bit value and 2-bit CRm field of the instruction itself (see
FLD_CRm_dsb_nxs).
+ Regeneration of aarch64-[asm|dis|opc]-2.c files.
+ Test cases to cover new instruction assembling and disassembling.
For more details regarding DSB memory barrier instruction and its
Armv8.7-a flavour please refer to Arm A64 Instruction set documentation
for Armv8-A architecture profile, see document pages 132-133 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* config/tc-aarch64.c (parse_operands): Add
AARCH64_OPND_BARRIER_DSB_NXS handler.
(md_begin): Add content of aarch64_barrier_dsb_nxs_options to
aarch64_barrier_opt_hsh hash.
* testsuite/gas/aarch64/system-4-invalid.d: New test.
* testsuite/gas/aarch64/system-4-invalid.l: New test.
* testsuite/gas/aarch64/system-4-invalid.s: New test.
* testsuite/gas/aarch64/system-4.d: New test.
* testsuite/gas/aarch64/system-4.s: New test.
include/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_BARRIER_DSB_NXS.
(aarch64_barrier_dsb_nxs_options): Declare DSB nXS options.
opcodes/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
ins_barrier_dsb_nx.
* aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
ext_barrier_dsb_nx.
* aarch64-opc.c (aarch64_print_operand): New options table
aarch64_barrier_dsb_nxs_options.
* aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
* aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
Armv8.7-a instruction.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This patch adds support for AArch64 -march=armv8.7-a command line option
in GAS.
Please note that this change ONLY extends -march= command line interface
with a new "armv8.7-a" option. Architectural changes like new instructions
will be added in following patches.
gas/ChangeLog:
2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* config/tc-aarch64.c (armv8.7-a): New arch.
* doc/c-aarch64.texi (-march=armv8.7-a): Update docs.
include/ChangeLog:
2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_7): New feature bitmask.
(AARCH64_ARCH_V8_7): New arch feature set.
opcodes/ChangeLog:
2020-10-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (ARMV8_7): New macro.
gas/
* config/tc-csky.c (get_operand_value): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* testsuite/gas/csky/csky_vdsp.d : Fix the disassembling
for vector register.
opcodes/
* csky-dis.c (csky_output_operand): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
(OPRND_TYPE_IMM5b_VSH): New enum.
(csky_v2_opcodes): Fix and add some instructions for VDSPV1.
Change-Id: Ia5675d7b716fe5c331e6121ad8f83061ef6454bb
This patch introduces BRBE (Branch Record Buffer Extension) system
registers.
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
gas/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* testsuite/gas/aarch64/brbe-invalid.d: New test.
* testsuite/gas/aarch64/brbe-invalid.l: New test.
* testsuite/gas/aarch64/brbe-invalid.s: New test.
* testsuite/gas/aarch64/brbe.d: New test.
* testsuite/gas/aarch64/brbe.s: New test.
opcodes/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add BRBE system registers.
This patch introduces CSRE (Call Stack Recorder Extension) system
registers.
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size
of a Call stack record) instruction. This instruction will be added in
a following, separate patch. This change only adds CSRE system
registers.
gas/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* testsuite/gas/aarch64/csre-invalid.d: New test.
* testsuite/gas/aarch64/csre-invalid.l: New test.
* testsuite/gas/aarch64/csre-invalid.s: New test.
* testsuite/gas/aarch64/csre.d: New test.
* testsuite/gas/aarch64/csre.s: New test.
opcodes/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: New CSRE system registers defined.
Remove the duplicated entry in opcodes/po/es.po:
binutils-gdb/opcodes/po/es.po:749: duplicate message definition...
binutils-gdb/opcodes/po/es.po:742: ...this is the location of the first definition
* po/es.po: Remove the duplicated entry.
bfd * po/es.po: Fix printf format
binutils * windmc.c: Fix printf format
gas * config/tc-arc.c: Fix printf format
opcodes * po/es.po: Fix printf format
sim * arm/armos.c: Fix printf format
* ppc/emul_netbsd.c: Fix printf format
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
Rename VexOpcode to OpcodePrefix so that OpcodePrefix can be used for
regular encoding prefix.
gas/
* config/tc-i386.c (build_vex_prefix): Replace vexopcode with
opcodeprefix.
(build_evex_prefix): Likewise.
(is_any_vex_encoding): Don't check vexopcode.
(output_insn): Handle opcodeprefix.
opcodes/
* i386-gen.c (opcode_modifiers): Replace VexOpcode with
OpcodePrefix.
* i386-opc.h (VexOpcode): Renamed to ...
(OpcodePrefix): This.
(PREFIX_NONE): New.
(PREFIX_0X66): Likewise.
(PREFIX_0XF2): Likewise.
(PREFIX_0XF3): Likewise.
* i386-opc.tbl (Prefix_0X66): New.
(Prefix_0XF2): Likewise.
(Prefix_0XF3): Likewise.
Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
* i386-tbl.h: Regenerated.
In 64bit, assembler generates a warning for "sysret":
$ echo sysret | as --64 -o x.o -
{standard input}: Assembler messages:
{standard input}:1: Warning: no instruction mnemonic suffix given and no register operands; using default for `sysret'
Always display suffix for %LQ in 64bit to display "sysretl".
gas/
PR binutils/26704
* testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of
sysret.
* testsuite/gas/i386/noreg64.d: Likewise.
* testsuite/gas/i386/x86-64-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
opcodes/
PR binutils/26704
* i386-dis.c (putop): Always display suffix for %LQ in 64bit.
The MODRM byte can be checked to display the instruction name only if the
MODRM byte needed. Clear modrm if the MODRM byte isn't needed so that
modrm field checks in putop like, modrm.mod == N with N != 0, can be done
without checking need_modrm.
gas/
PR binutils/26705
* testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before
sysretq.
* testsuite/gas/i386/x86-64-suffix-intel.d: Updated.
* testsuite/gas/i386/x86-64-suffix.d: Likewise.
opcodes/
PR binutils/26705
* i386-dis.c (print_insn): Clear modrm if not needed.
(putop): Check need_modrm for modrm.mod != 3. Don't check
need_modrm for modrm.mod == 3.
gas * testsuite/gas/aarch64/ete.d: New test.
* testsuite/gas/aarch64/ete.s: New test.
opcodes * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
gas * testsuite/gas/aarch64/trbe-invalid.d: New test.
* testsuite/gas/aarch64/trbe-invalid.l: New test.
* testsuite/gas/aarch64/trbe-invalid.s: New test.
* testsuite/gas/aarch64/trbe.d: New test.
* testsuite/gas/aarch64/trbe.s: New test.
opcodes * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
There are 11 MOD_VEX_0F38* inserted in MOD_0F38* group,
which should be placed in MOD_VEX_0F38* group.
opcode/
PR 26654
*i386-dis.c (enum): Put MOD_VEX_0F38* together.
This commit:
commit afdcafe891
Date: Thu Sep 17 14:30:28 2020 +0800
CSKY: Add objdump option -M abi-names.
cases the build of GDB (configured with --enabled-targets=all) to fail
with this error:
libtool: compile: gcc -DHAVE_CONFIG_H -I. -I../../src/opcodes -I. -I../../src/opcodes -I../bfd -I../../src/opcodes/../include -I../../src/opcodes/../bfd -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow -Wstack-usage=262144 -Werror -O0 -g3 -D_GLIBCXX_DEBUG=1 -MT csky-dis.lo -MD -MP -MF .deps/csky-dis.Tpo -c ../../src/opcodes/csky-dis.c -o csky-dis.o
../../src/opcodes/csky-dis.c: In function 'csky_output_operand':
../../src/opcodes/csky-dis.c:849:7: error: this 'if' clause does not guard... [-Werror=misleading-indentation]
849 | if (IS_CSKY_V1 (mach_flag))
| ^~
../../src/opcodes/csky-dis.c:851:2: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the 'if'
851 | strcat (str, buf);
| ^~~~~~
this commit adds { ... } around the if body to resolve this issue.
opcodes/ChangeLog:
* csky-dis.c (csky_output_operand): Enclose body of if in curly
braces.
Add option parser for disassembler, and refine the codes of
parse register operand and disassemble register operand.
While strengthen the operands legality check of some instructions.
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (parse_type_ctrlreg): Use function
csky_get_control_regno to operand.
(csky_get_reg_val): Likewise.
(is_reg_sp_with_bracket): Use function csky_get_reg_val
to parse operand.
(is_reg_sp): Refine.
(is_oimm_within_range): Fix, report error when operand
is not constant.
(parse_type_cpreg): Refine.
(parse_type_cpcreg): Refine.
(get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS.
(md_assemble): Fix no error reporting somtimes when
operands number are not fit.
(csky_addc64): Refine.
(csky_subc64): Refine.
(csky_or64): Refine.
(v1_work_fpu_fo): Refine.
(v1_work_fpu_read): Refine.
(v1_work_fpu_writed): Refine.
(v1_work_fpu_readd): Refine.
(v2_work_addc): New function, strengthen the operands legality
check of addc.
* gas/testsuite/gas/csky/all.d : Use register number format when
disassemble register name by default.
* gas/testsuite/gas/csky/cskyv2_all.d : Likewise.
* gas/testsuite/gas/csky/trust.d: Likewise.
* gas/testsuite/gas/csky/cskyv2_ck860.d : Fix.
* gas/testsuite/gas/csky/trust.s : Fix.
opcodes/
* csky-dis.c (using_abi): New.
(parse_csky_dis_options): New function.
(get_gr_name): New function.
(get_cr_name): New function.
(csky_output_operand): Use get_gr_name and get_cr_name to
disassemble and add handle of OPRND_TYPE_IMM5b_LS.
(print_insn_csky): Parse disassembler options.
* opcodes/csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
(GENARAL_REG_BANK): Define.
(REG_SUPPORT_ALL): Define.
(REG_SUPPORT_ALL): New.
(ASH): Define.
(REG_SUPPORT_A): Define.
(REG_SUPPORT_B): Define.
(REG_SUPPORT_C): Define.
(REG_SUPPORT_D): Define.
(REG_SUPPORT_E): Define.
(csky_abiv1_general_regs): New.
(csky_abiv1_control_regs): New.
(csky_abiv2_general_regs): New.
(csky_abiv2_control_regs): New.
(get_register_name): New function.
(get_register_number): New function.
(csky_get_general_reg_name): New function.
(csky_get_general_regno): New function.
(csky_get_control_reg_name): New function.
(csky_get_control_regno): New function.
(csky_v2_opcodes): Prefer two oprerans format for bclri and
bseti, strengthen the operands legality check of addc, zext
and sext.
Add gas and opcodes support for two xBPF-exclusive ALU operations:
SDIV (signed division) and SMOD (signed modulo), and add tests for
them in gas.
cpu/
* bpf.cpu (insn-op-code-alu): Add SDIV and SMOD.
(define-alu-insn-bin, daib): Take ISAs as an argument.
(define-alu-instructions): Update calls to daib pmacro with
ISAs; add sdiv and smod.
gas/
* testsuite/gas/bpf/alu-xbpf.d: New file.
* testsuite/gas/bpf/alu-xbpf.s: Likewise.
* testsuite/gas/bpf/alu32-xbpf.d: Likewise.
* testsuite/gas/bpf/alu32-xbpf.d: Likewise.
* testuiste/gas/bpf/bpf.exp: Run new tests.
opcodes/
* bpf-desc.c: Regenerate.
* bpf-desc.h: Likewise.
* bpf-opc.c: Likewise.
* bpf-opc.h: Likewise.
The disassembler function should return a valid disassembler function
even when there is no BFD present. This is implied (I believe) by the
comment in dis-asm.h which says the BFD may be NULL. Further, it
makes sense when considering that the disassembler is used in GDB, and
GDB may connect to a target and perform debugging even without a BFD
being supplied.
This commit makes the csky_get_disassembler function return the
default disassembler configuration when no bfd is supplied, this is
the same default configuration as is used when a BFD is supplied, but
the BFD has no attributes section.
Before the change configuring GDB with --enable-targets=all and
running the tests gdb.base/all-architectures-2.exp results in many
errors, but after this change there are no failures.
opcodes/ChangeLog:
* csky-dis.c (csky_get_disassembler): Don't return NULL when there
is no BFD.
* ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
for hidden, local, no-type symbols.
(disassemble_init_powerpc): Point the symbol_is_valid field in the
info structure at the new function.
Add arches CK804, CK805 and CK800. CK800 is an special arch which
support all instructions for CSKYV2. Refine the cpu tables to
simplify adding a new cpu.
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (struct csky_cpu_info): Add new members
isa_flag, features and ver.
(struct csky_cpu_feature): New.
(struct csky_cpu_version): New.
(CSKY_FEATURE_MAX): Define.
(CSKY_CPU_REVERISON_MAX): Define.
(FEATURE_DSP_EXT, FEATURE_DSP, FEATURE_MMU, FEATURE_VDSP,
FEATURE_FLOAT, FEATURE_TRUST, FEATURE_JAVA, FEATURE_SHIELD):
Define, each standard one collection of instructions.
(CSKY_FEATURES_DEF_NULL, CSKY_FEATURES_DEF_e,
CSKY_FEATURES_DEF_t, CSKY_FEATURES_DEF_f, CSKY_FEATURES_DEF_v,
CSKY_FEATURES_DEF_ef, CSKY_FEATURES_DEF_jt,
CSKY_FEATURES_DEF_efht, CSKY_FEATURES_DEF_efv,
CSKY_FEATURES_DEF_eft, CSKY_FEATURES_DEF_d,
CSKY_FEATURES_DEF_df, CSKY_FEATURES_DEF_ft,
CSKY_FEATURES_DEF_tv, CSKY_FEATURES_DEF_fv,
CSKY_FEATURES_DEF_dft, CSKY_FEATURES_DEF_dfv,
CSKY_FEATURES_DEF_ftv, CSKY_FEATURES_DEF_eftv): Define,
the features combination used by cpu.
(CSKY_CPU_REVERISON_r0p0, CSKY_CPU_REVERISON_r1p0,
CSKY_CPU_REVERISON_r2p0, CSKY_CPU_REVERISON_r3p0,
CSKY_CPU_REVERISON_RESERVED, CSKY_CPU_REVERISON_R3):
Define, version information used by cpu.
(csky_cpus): Refine, and add CK804, CK805 and CK800.
(parse_cpu): Refine.
(parse_arch): Refine.
(md_show_usage): Refine.
(md_begin): Refine.
include/
* opcode/csky.h (CSKY_ARCH_804): Define.
(CSKY_ARCH_805): Define.
(CSKY_ARCH_800): Define.
incldue * opcode/csky.h (CSKY_ISA_FLOAT_7E60): Use a long long type for
this value.
opcodes * csky-dis.c (csky_output_operand): Coerce the immediate values to
long before printing.
This patch adds support for the system registers introduced in Armv8-R
AArch64.
gas/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to
validation function.
(parse_sys_ins_reg): Likewise.
(print_operands): Pass CPU features to aarch64_print_operand().
* testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test.
* testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output.
* testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input.
* testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test.
* testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output.
* testsuite/gas/aarch64/v8-r-sysregs.d: New test.
* testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests.
include/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (aarch64_sys_ins_reg_supported_p): Also take
system register name in order to simplify validation for v8-R.
(aarch64_print_operand): Also take CPU feature set, as disassembly for
system registers now depends on arch variant.
opcodes/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* aarch64-dis.c (print_operands): Pass CPU features to
aarch64_print_operand().
* aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
preferred disassembly of system registers.
(SR_RNG): Refactor to use new SR_FEAT2 macro.
(SR_FEAT2): New.
(SR_V8_1_A): New.
(SR_V8_4_A): New.
(SR_V8_A): New.
(SR_V8_R): New.
(SR_EXPAND_ELx): New.
(SR_EXPAND_EL12): New.
(aarch64_sys_regs): Specify which registers are only on
A-profile, add R-profile system registers.
(ENC_BARLAR): New.
(PRBARn_ELx): New.
(PRLARn_ELx): New.
(aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
Armv8-R AArch64.
This patch adds the basic infrastructure needed to support Armv8-R in
AArch64 binutils: new command-line flags, new feature bits, a new BFD
architecture, and support for differentiating between architecture
variants in the disassembler.
The new command-line options added by this patch are -march=armv8-r in
GAS and -m aarch64:armv8-r in objdump.
The disassembler support is necessary since Armv8-R AArch64 introduces a
system register (VSCTLR_EL2) which shares an encoding with a different
system register (TTBR0_EL2) in Armv8-A. This also allows us to use the
correct preferred disassembly for the new DFB alias introduced in
Armv8-R.
bfd/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* archures.c (bfd_mach_aarch64_8R): New.
* bfd-in2.h: Regenerate.
* cpu-aarch64.c (bfd_aarch64_arch_v8_r): New.
(bfd_aarch64_arch_ilp32): Update tail pointer.
gas/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (aarch64_archs): Add armv8-r.
* doc/c-aarch64.texi: Document -march=armv8-r.
include/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_V8_A): New.
(AARCH64_FEATURE_V8_R): New.
(AARCH64_ARCH_V8): Include new A-profile feature bit.
(AARCH64_ARCH_V8_R): New.
opcodes/ChangeLog:
2020-09-08 Alex Coplan <alex.coplan@arm.com>
* aarch64-dis.c (arch_variant): New.
(determine_disassembling_preference): Disassemble according to
arch variant.
(select_aarch64_variant): New.
(print_insn_aarch64): Set feature set.
i386-dis.c:12207 left shift of 128 by 24 places cannot be represented in type 'long int'
i386-dis.c:12220 left shift of 128 by 24 places cannot be represented in type 'long int'
i386-dis.c:12222 left shift of 1 by 31 places cannot be represented in type 'long int'
i386-dis.c:12222 signed integer overflow: 162254319 - -2147483648 cannot be represented in type 'long int'
* i386-dis.c (OP_E_memory): Don't cast to signed type when
negating.
(get32, get32s): Use unsigned types in shift expressions.
bfin-dis.c:160 shift exponent 32 is too large for 32-bit type 'long unsigned int'
bpf-ibld.c:196 left shift of 1 by 31 places cannot be represented in type 'long int'
bpf-ibld.c:196 negation of -2147483648 cannot be represented in type 'long int'; cast to an unsigned type to negate this
itself
bpf-ibld.c:197 left shift of 1 by 31 places cannot be represented in type 'long int'
bpf-ibld.c:197 signed integer overflow: -2147483648 - 1 cannot be represented in type 'long int'
bpf-ibld.c:501 left shift of 1 by 31 places cannot be represented in type 'long int'
* cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
* bpf-ibld.c: Regenerate.
* epiphany-ibld.c: Regenerate.
* fr30-ibld.c: Regenerate.
* frv-ibld.c: Regenerate.
* ip2k-ibld.c: Regenerate.
* iq2000-ibld.c: Regenerate.
* lm32-ibld.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32r-ibld.c: Regenerate.
* mep-ibld.c: Regenerate.
* mt-ibld.c: Regenerate.
* or1k-ibld.c: Regenerate.
* xc16x-ibld.c: Regenerate.
* xstormy16-ibld.c: Regenerate.
